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net: sparx5: add registers required by lan969x
Lan969x will require a few additional registers for certain operations. Some are shared, some are not. Add these. Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-5-a0b5fae88a0f@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Machon
Jakub Kicinski
parent
ead854c463
commit
199498490c
@ -2666,6 +2666,44 @@ extern const struct sparx5_regs *regs;
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#define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
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FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
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/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */
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#define DEV2G5_PHAD_CTRL(t, g) \
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__REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \
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regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
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#define DEV2G5_PHAD_CTRL_PHAD_ENA\
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BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA])
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#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
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spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
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#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
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spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
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/* LAN969X ONLY */
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#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9)
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#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
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FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
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#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
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FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
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/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */
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#define DEV2G5_PHAD_CTRL(t, g) \
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__REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \
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regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
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#define DEV2G5_PHAD_CTRL_PHAD_ENA\
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BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA])
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#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
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spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
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#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
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spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
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/* LAN969X ONLY */
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#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9)
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#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
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FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
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#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
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FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
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/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
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#define DEV10G_MAC_ENA_CFG(t) \
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__REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \
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@ -2869,6 +2907,11 @@ extern const struct sparx5_regs *regs;
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#define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
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FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
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/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */
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#define DEV10G_PTP_STAMPER_CFG(t) \
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__REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \
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1, 4)
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/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
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#define DEV10G_PCS25G_CFG(t) \
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__REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\
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@ -4267,6 +4310,11 @@ extern const struct sparx5_regs *regs;
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#define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
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FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
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/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */
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#define DEV5G_PTP_STAMPER_CFG(t) \
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__REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \
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4)
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/* DSM:RAM_CTRL:RAM_INIT */
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#define DSM_RAM_INIT \
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__REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
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@ -4444,6 +4492,27 @@ extern const struct sparx5_regs *regs;
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#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
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FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
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/* LAN969X ONLY */
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#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23)
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#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\
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FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
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#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\
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FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
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/* LAN969X ONLY */
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#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22)
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#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\
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FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
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#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\
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FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
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/* LAN969X ONLY */
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#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21)
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#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\
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FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
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#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\
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FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
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/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */
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#define EACL_VCAP_ES2_KEY_SEL(g, r) \
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__REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \
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@ -6720,6 +6789,69 @@ extern const struct sparx5_regs *regs;
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regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \
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regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4)
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/* LAN969X ONLY */
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/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */
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#define PTP_TWOSTEP_CTRL \
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__REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4)
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#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12)
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#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
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#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
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FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
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#define PTP_TWOSTEP_CTRL_PTP_NXT BIT(11)
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#define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x)
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#define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
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FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x)
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#define PTP_TWOSTEP_CTRL_PTP_VLD BIT(10)
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#define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x)
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#define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
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FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x)
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#define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9)
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#define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
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#define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
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FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)
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#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
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#define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
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#define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
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FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
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#define PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0)
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#define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x)
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#define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
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FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x)
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/* LAN969X ONLY */
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/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */
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#define PTP_TWOSTEP_STAMP_NSEC \
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__REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4)
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#define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0)
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#define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x)
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#define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\
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FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x)
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/* LAN969X ONLY */
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/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */
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#define PTP_TWOSTEP_STAMP_SUBNS \
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__REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4)
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#define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0)
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#define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\
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FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x)
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#define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\
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FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x)
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/* QFWD:SYSTEM:SWITCH_PORT_MODE */
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#define QFWD_SWITCH_PORT_MODE(r) \
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__REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \
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