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iio: dac: adi-axi-dac: update register names
Non functional, readability change. Update register names so that register bitfields can be more easily linked to the register name. Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> Link: https://patch.msgid.link/20241008-wip-bl-ad3552r-axi-v0-iio-testing-v5-2-3d410944a63d@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Angelo Dureghello
Jonathan Cameron
parent
70602f529e
commit
1a811e1be7
@ -35,35 +35,37 @@
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*/
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/* Base controls */
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#define AXI_DAC_REG_CONFIG 0x0c
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#define AXI_DDS_DISABLE BIT(6)
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#define AXI_DAC_CONFIG_REG 0x0c
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#define AXI_DAC_CONFIG_DDS_DISABLE BIT(6)
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/* DAC controls */
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#define AXI_DAC_REG_RSTN 0x0040
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#define AXI_DAC_RSTN_CE_N BIT(2)
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#define AXI_DAC_RSTN_MMCM_RSTN BIT(1)
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#define AXI_DAC_RSTN_RSTN BIT(0)
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#define AXI_DAC_REG_CNTRL_1 0x0044
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#define AXI_DAC_SYNC BIT(0)
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#define AXI_DAC_REG_CNTRL_2 0x0048
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#define ADI_DAC_R1_MODE BIT(5)
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#define AXI_DAC_DRP_STATUS 0x0074
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#define AXI_DAC_DRP_LOCKED BIT(17)
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#define AXI_DAC_RSTN_REG 0x0040
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#define AXI_DAC_RSTN_CE_N BIT(2)
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#define AXI_DAC_RSTN_MMCM_RSTN BIT(1)
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#define AXI_DAC_RSTN_RSTN BIT(0)
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#define AXI_DAC_CNTRL_1_REG 0x0044
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#define AXI_DAC_CNTRL_1_SYNC BIT(0)
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#define AXI_DAC_CNTRL_2_REG 0x0048
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#define ADI_DAC_CNTRL_2_R1_MODE BIT(5)
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#define AXI_DAC_DRP_STATUS_REG 0x0074
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#define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17)
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/* DAC Channel controls */
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#define AXI_DAC_REG_CHAN_CNTRL_1(c) (0x0400 + (c) * 0x40)
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#define AXI_DAC_REG_CHAN_CNTRL_3(c) (0x0408 + (c) * 0x40)
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#define AXI_DAC_SCALE_SIGN BIT(15)
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#define AXI_DAC_SCALE_INT BIT(14)
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#define AXI_DAC_SCALE GENMASK(14, 0)
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#define AXI_DAC_REG_CHAN_CNTRL_2(c) (0x0404 + (c) * 0x40)
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#define AXI_DAC_REG_CHAN_CNTRL_4(c) (0x040c + (c) * 0x40)
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#define AXI_DAC_PHASE GENMASK(31, 16)
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#define AXI_DAC_FREQUENCY GENMASK(15, 0)
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#define AXI_DAC_REG_CHAN_CNTRL_7(c) (0x0418 + (c) * 0x40)
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#define AXI_DAC_DATA_SEL GENMASK(3, 0)
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#define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40)
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#define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40)
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#define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15)
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#define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14)
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#define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0)
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#define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40)
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#define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16)
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#define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0)
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#define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40)
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#define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40)
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#define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0)
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/* 360 degrees in rad */
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#define AXI_DAC_2_PI_MEGA 6283190
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#define AXI_DAC_2_PI_MEGA 6283190
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enum {
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AXI_DAC_DATA_INTERNAL_TONE,
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AXI_DAC_DATA_DMA = 2,
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@ -89,7 +91,7 @@ static int axi_dac_enable(struct iio_backend *back)
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int ret;
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guard(mutex)(&st->lock);
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ret = regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN,
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ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
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AXI_DAC_RSTN_MMCM_RSTN);
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if (ret)
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return ret;
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@ -98,12 +100,14 @@ static int axi_dac_enable(struct iio_backend *back)
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* designs really use it but if they don't we still get the lock bit
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* set. So let's do it all the time so the code is generic.
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*/
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ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS, __val,
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__val & AXI_DAC_DRP_LOCKED, 100, 1000);
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ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG,
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__val,
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__val & AXI_DAC_DRP_STATUS_DRP_LOCKED,
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100, 1000);
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if (ret)
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return ret;
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return regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN,
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return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
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AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN);
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}
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@ -112,7 +116,7 @@ static void axi_dac_disable(struct iio_backend *back)
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struct axi_dac_state *st = iio_backend_get_priv(back);
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guard(mutex)(&st->lock);
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regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0);
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regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
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}
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static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back,
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@ -155,15 +159,15 @@ static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan,
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}
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if (tone_2)
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reg = AXI_DAC_REG_CHAN_CNTRL_4(chan);
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reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
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else
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reg = AXI_DAC_REG_CHAN_CNTRL_2(chan);
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reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
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ret = regmap_read(st->regmap, reg, &raw);
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if (ret)
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return ret;
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raw = FIELD_GET(AXI_DAC_FREQUENCY, raw);
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raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
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*freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16));
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return 0;
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@ -194,17 +198,18 @@ static int axi_dac_scale_get(struct axi_dac_state *st,
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u32 reg, raw;
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if (tone_2)
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reg = AXI_DAC_REG_CHAN_CNTRL_3(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
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else
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reg = AXI_DAC_REG_CHAN_CNTRL_1(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
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ret = regmap_read(st->regmap, reg, &raw);
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if (ret)
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return ret;
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sign = FIELD_GET(AXI_DAC_SCALE_SIGN, raw);
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raw = FIELD_GET(AXI_DAC_SCALE, raw);
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scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, AXI_DAC_SCALE_INT);
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sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw);
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raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw);
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scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA,
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AXI_DAC_CHAN_CNTRL_3_SCALE_INT);
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vals[0] = scale / MEGA;
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vals[1] = scale % MEGA;
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@ -227,15 +232,15 @@ static int axi_dac_phase_get(struct axi_dac_state *st,
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int ret, vals[2];
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if (tone_2)
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reg = AXI_DAC_REG_CHAN_CNTRL_4(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
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else
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reg = AXI_DAC_REG_CHAN_CNTRL_2(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
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ret = regmap_read(st->regmap, reg, &raw);
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if (ret)
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return ret;
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raw = FIELD_GET(AXI_DAC_PHASE, raw);
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raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw);
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phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX);
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vals[0] = phase / MEGA;
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@ -260,18 +265,20 @@ static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan,
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}
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if (tone_2)
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reg = AXI_DAC_REG_CHAN_CNTRL_4(chan);
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reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
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else
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reg = AXI_DAC_REG_CHAN_CNTRL_2(chan);
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reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
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raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate);
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ret = regmap_update_bits(st->regmap, reg, AXI_DAC_FREQUENCY, raw);
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ret = regmap_update_bits(st->regmap, reg,
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AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
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if (ret)
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return ret;
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/* synchronize channels */
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return regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC);
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return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
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AXI_DAC_CNTRL_1_SYNC);
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}
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static int axi_dac_frequency_set(struct axi_dac_state *st,
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@ -312,16 +319,16 @@ static int axi_dac_scale_set(struct axi_dac_state *st,
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/* format is 1.1.14 (sign, integer and fractional bits) */
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if (scale < 0) {
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raw = FIELD_PREP(AXI_DAC_SCALE_SIGN, 1);
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raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1);
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scale *= -1;
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}
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raw |= div_u64((u64)scale * AXI_DAC_SCALE_INT, MEGA);
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raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA);
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if (tone_2)
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reg = AXI_DAC_REG_CHAN_CNTRL_3(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
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else
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reg = AXI_DAC_REG_CHAN_CNTRL_1(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
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guard(mutex)(&st->lock);
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ret = regmap_write(st->regmap, reg, raw);
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@ -329,7 +336,8 @@ static int axi_dac_scale_set(struct axi_dac_state *st,
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return ret;
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/* synchronize channels */
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ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC);
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ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
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AXI_DAC_CNTRL_1_SYNC);
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if (ret)
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return ret;
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@ -355,18 +363,19 @@ static int axi_dac_phase_set(struct axi_dac_state *st,
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raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA);
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if (tone_2)
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reg = AXI_DAC_REG_CHAN_CNTRL_4(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
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else
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reg = AXI_DAC_REG_CHAN_CNTRL_2(chan->channel);
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reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
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guard(mutex)(&st->lock);
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ret = regmap_update_bits(st->regmap, reg, AXI_DAC_PHASE,
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FIELD_PREP(AXI_DAC_PHASE, raw));
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ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE,
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FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw));
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if (ret)
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return ret;
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/* synchronize channels */
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ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC);
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ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
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AXI_DAC_CNTRL_1_SYNC);
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if (ret)
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return ret;
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@ -437,7 +446,7 @@ static int axi_dac_extend_chan(struct iio_backend *back,
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if (chan->type != IIO_ALTVOLTAGE)
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return -EINVAL;
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if (st->reg_config & AXI_DDS_DISABLE)
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if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
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/* nothing to extend */
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return 0;
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@ -454,13 +463,14 @@ static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan,
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switch (data) {
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case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE:
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return regmap_update_bits(st->regmap,
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AXI_DAC_REG_CHAN_CNTRL_7(chan),
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AXI_DAC_DATA_SEL,
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AXI_DAC_CHAN_CNTRL_7_REG(chan),
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AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
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AXI_DAC_DATA_INTERNAL_TONE);
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case IIO_BACKEND_EXTERNAL:
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return regmap_update_bits(st->regmap,
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AXI_DAC_REG_CHAN_CNTRL_7(chan),
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AXI_DAC_DATA_SEL, AXI_DAC_DATA_DMA);
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AXI_DAC_CHAN_CNTRL_7_REG(chan),
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AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
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AXI_DAC_DATA_DMA);
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default:
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return -EINVAL;
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}
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@ -475,7 +485,7 @@ static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan,
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if (!sample_rate)
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return -EINVAL;
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if (st->reg_config & AXI_DDS_DISABLE)
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if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
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/* sample_rate has no meaning if DDS is disabled */
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return 0;
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@ -580,7 +590,7 @@ static int axi_dac_probe(struct platform_device *pdev)
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* Force disable the core. Up to the frontend to enable us. And we can
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* still read/write registers...
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*/
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ret = regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0);
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ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
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if (ret)
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return ret;
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@ -601,7 +611,7 @@ static int axi_dac_probe(struct platform_device *pdev)
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}
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/* Let's get the core read only configuration */
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ret = regmap_read(st->regmap, AXI_DAC_REG_CONFIG, &st->reg_config);
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ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config);
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if (ret)
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return ret;
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@ -613,7 +623,8 @@ static int axi_dac_probe(struct platform_device *pdev)
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* want independent channels let's override the core's default value and
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* set the R1_MODE bit.
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*/
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ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_2, ADI_DAC_R1_MODE);
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ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
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ADI_DAC_CNTRL_2_R1_MODE);
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if (ret)
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return ret;
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