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wifi: rtw89: pci: consolidate PCI basic configurations for probe and resume
The PCI settings aren't always persistent after chip suspends, so reconfigure the settings after chip resumes. Since most of these settings are the same, consolidate them into a function to avoid missing somewhere. Fix the missing case of 8922AE resume flow. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20240925013901.9835-2-pkshih@realtek.com
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@ -4188,6 +4188,17 @@ static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev)
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RTW89_PCIE_BIT_CFG_RST_MSTATE);
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}
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void rtw89_pci_basic_cfg(struct rtw89_dev *rtwdev, bool resume)
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{
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if (resume)
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rtw89_pci_cfg_dac(rtwdev);
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rtw89_pci_disable_eq(rtwdev);
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rtw89_pci_filter_out(rtwdev);
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rtw89_pci_link_cfg(rtwdev);
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rtw89_pci_l1ss_cfg(rtwdev);
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}
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static int __maybe_unused rtw89_pci_resume(struct device *dev)
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{
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struct ieee80211_hw *hw = dev_get_drvdata(dev);
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@ -4209,11 +4220,8 @@ static int __maybe_unused rtw89_pci_resume(struct device *dev)
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B_AX_SEL_REQ_ENTR_L1);
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}
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rtw89_pci_l2_hci_ldo(rtwdev);
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rtw89_pci_disable_eq(rtwdev);
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rtw89_pci_cfg_dac(rtwdev);
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rtw89_pci_filter_out(rtwdev);
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rtw89_pci_link_cfg(rtwdev);
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rtw89_pci_l1ss_cfg(rtwdev);
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rtw89_pci_basic_cfg(rtwdev, true);
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return 0;
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}
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@ -4345,10 +4353,7 @@ int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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goto err_clear_resource;
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}
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rtw89_pci_disable_eq(rtwdev);
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rtw89_pci_filter_out(rtwdev);
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rtw89_pci_link_cfg(rtwdev);
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rtw89_pci_l1ss_cfg(rtwdev);
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rtw89_pci_basic_cfg(rtwdev, false);
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ret = rtw89_core_napi_init(rtwdev);
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if (ret) {
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@ -1600,6 +1600,7 @@ struct pci_device_id;
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int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
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void rtw89_pci_remove(struct pci_dev *pdev);
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void rtw89_pci_basic_cfg(struct rtw89_dev *rtwdev, bool resume);
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void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev);
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int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
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int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
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@ -584,6 +584,8 @@ static int __maybe_unused rtw89_pci_resume_be(struct device *dev)
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rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
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rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR);
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rtw89_pci_basic_cfg(rtwdev, true);
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return 0;
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}
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