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MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks

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Change the declaration of clocks: remove all fixed clocks and declare
system-controllers (OLB) as clock providers.

Remove eyeq6h-fixed-clocks.dtsi and move the crystal clock to the main
eyeq6h.dtsi file.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Théo Lebrun 2024-11-06 17:04:01 +01:00 committed by Thomas Bogendoerfer
parent d3c3c283af
commit 1be858f7fa
2 changed files with 69 additions and 56 deletions
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52
arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi
View File

@ -1,52 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright 2023 Mobileye Vision Technologies Ltd.
*/
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
/ {
xtal: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
};
pll_west: clock-2000000000-west {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
};
pll_cpu: clock-2000000000-cpu {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
};
/* pll-cpu derivatives */
occ_cpu: clock-2000000000-occ-cpu {
compatible = "fixed-factor-clock";
clocks = <&pll_cpu>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
/* pll-west derivatives */
occ_periph_w: clock-200000000 {
compatible = "fixed-factor-clock";
clocks = <&pll_west>;
#clock-cells = <0>;
clock-div = <10>;
clock-mult = <1>;
};
uart_clk: clock-200000000-uart {
compatible = "fixed-factor-clock";
clocks = <&occ_periph_w>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
};

73
arch/mips/boot/dts/mobileye/eyeq6h.dtsi
View File

@ -5,7 +5,7 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include "eyeq6h-fixed-clocks.dtsi"
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
/ {
#address-cells = <2>;
@ -17,7 +17,7 @@ cpu@0 {
device_type = "cpu";
compatible = "img,i6500";
reg = <0>;
clocks = <&occ_cpu>;
clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
};
};
@ -32,19 +32,42 @@ cpu_intc: interrupt-controller {
#interrupt-cells = <1>;
};
xtal: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
olb_acc: system-controller@d2003000 {
compatible = "mobileye,eyeq6h-acc-olb", "syscon";
reg = <0x0 0xd2003000 0x0 0x1000>;
#reset-cells = <1>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
olb_central: system-controller@d3100000 {
compatible = "mobileye,eyeq6h-central-olb", "syscon";
reg = <0x0 0xd3100000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
uart0: serial@d3331000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0xd3331000 0x0 0x1000>;
reg-io-width = <4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&occ_periph_w>, <&occ_periph_w>;
clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
clock-names = "uartclk", "apb_pclk";
};
@ -56,6 +79,15 @@ pinctrl_west: pinctrl@d3337000 {
pinctrl-single,function-mask = <0xffff>;
};
olb_west: system-controller@d3338000 {
compatible = "mobileye,eyeq6h-west-olb", "syscon";
reg = <0x0 0xd3338000 0x0 0x1000>;
#reset-cells = <1>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
pinctrl_east: pinctrl@d3357000 {
compatible = "pinctrl-single";
reg = <0x0 0xd3357000 0x0 0xb0>;
@ -64,6 +96,23 @@ pinctrl_east: pinctrl@d3357000 {
pinctrl-single,function-mask = <0xffff>;
};
olb_east: system-controller@d3358000 {
compatible = "mobileye,eyeq6h-east-olb", "syscon";
reg = <0x0 0xd3358000 0x0 0x1000>;
#reset-cells = <1>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
olb_south: system-controller@d8013000 {
compatible = "mobileye,eyeq6h-south-olb", "syscon";
reg = <0x0 0xd8013000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
pinctrl_south: pinctrl@d8014000 {
compatible = "pinctrl-single";
reg = <0x0 0xd8014000 0x0 0xf8>;
@ -72,6 +121,22 @@ pinctrl_south: pinctrl@d8014000 {
pinctrl-single,function-mask = <0xffff>;
};
olb_ddr0: system-controller@e4080000 {
compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
reg = <0x0 0xe4080000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
olb_ddr1: system-controller@e4081000 {
compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
reg = <0x0 0xe4081000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
gic: interrupt-controller@f0920000 {
compatible = "mti,gic";
reg = <0x0 0xf0920000 0x0 0x20000>;
@ -89,7 +154,7 @@ gic: interrupt-controller@f0920000 {
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&occ_cpu>;
clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
};
};
};