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IDE: Coding Style fixes to drivers/ide/pci/sis5513.c

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About 300 errors and warnings fixed.
File is now error free.
Compile tested.

[bart: minor fixes, md5sum checked]

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Paolo Ciarrocchi 2008-04-26 17:36:39 +02:00 committed by Bartlomiej Zolnierkiewicz
parent 5749c84740
commit 1eb3c2ee1d
1 changed files with 96 additions and 98 deletions
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194
drivers/ide/pci/sis5513.c
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@ -59,10 +59,10 @@
#define ATA_16 0x01 #define ATA_16 0x01
#define ATA_33 0x02 #define ATA_33 0x02
#define ATA_66 0x03 #define ATA_66 0x03
#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout #define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
#define ATA_100 0x05 #define ATA_100 0x05
#define ATA_133a 0x06 // SiS961b with 133 support #define ATA_133a 0x06 /* SiS961b with 133 support */
#define ATA_133 0x07 // SiS962/963 #define ATA_133 0x07 /* SiS962/963 */
static u8 chipset_family; static u8 chipset_family;
@ -111,69 +111,70 @@ static const struct {
Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */ Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */ /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
static u8 cycle_time_offset[] = {0,0,5,4,4,0,0}; static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
static u8 cycle_time_range[] = {0,0,2,3,3,4,4}; static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
{0,0,0,0,0,0,0}, /* no udma */ { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
{0,0,0,0,0,0,0}, /* no udma */ { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
{3,2,1,0,0,0,0}, /* ATA_33 */ { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
{7,5,3,2,1,0,0}, /* ATA_66 */ { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
{7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */ { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
{11,7,5,4,2,1,0}, /* ATA_100 */ different cycle_time range and offset */
{15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */ { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
{15,10,7,5,3,2,1}, /* ATA_133 */ { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
}; };
/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
See SiS962 data sheet for more detail */ See SiS962 data sheet for more detail */
static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
{0,0,0,0,0,0,0}, /* no udma */ { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
{0,0,0,0,0,0,0}, /* no udma */ { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
{2,1,1,0,0,0,0}, { 2, 1, 1, 0, 0, 0, 0 },
{4,3,2,1,0,0,0}, { 4, 3, 2, 1, 0, 0, 0 },
{4,3,2,1,0,0,0}, { 4, 3, 2, 1, 0, 0, 0 },
{6,4,3,1,1,1,0}, { 6, 4, 3, 1, 1, 1, 0 },
{9,6,4,2,2,2,2}, { 9, 6, 4, 2, 2, 2, 2 },
{9,6,4,2,2,2,2}, { 9, 6, 4, 2, 2, 2, 2 },
}; };
/* Initialize time, Active time, Recovery time vary across /* Initialize time, Active time, Recovery time vary across
IDE clock settings. These 3 arrays hold the register value IDE clock settings. These 3 arrays hold the register value
for PIO0/1/2/3/4 and DMA0/1/2 mode in order */ for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
static u8 ini_time_value[][8] = { static u8 ini_time_value[][8] = {
{0,0,0,0,0,0,0,0}, { 0, 0, 0, 0, 0, 0, 0, 0 },
{0,0,0,0,0,0,0,0}, { 0, 0, 0, 0, 0, 0, 0, 0 },
{2,1,0,0,0,1,0,0}, { 2, 1, 0, 0, 0, 1, 0, 0 },
{4,3,1,1,1,3,1,1}, { 4, 3, 1, 1, 1, 3, 1, 1 },
{4,3,1,1,1,3,1,1}, { 4, 3, 1, 1, 1, 3, 1, 1 },
{6,4,2,2,2,4,2,2}, { 6, 4, 2, 2, 2, 4, 2, 2 },
{9,6,3,3,3,6,3,3}, { 9, 6, 3, 3, 3, 6, 3, 3 },
{9,6,3,3,3,6,3,3}, { 9, 6, 3, 3, 3, 6, 3, 3 },
}; };
static u8 act_time_value[][8] = { static u8 act_time_value[][8] = {
{0,0,0,0,0,0,0,0}, { 0, 0, 0, 0, 0, 0, 0, 0 },
{0,0,0,0,0,0,0,0}, { 0, 0, 0, 0, 0, 0, 0, 0 },
{9,9,9,2,2,7,2,2}, { 9, 9, 9, 2, 2, 7, 2, 2 },
{19,19,19,5,4,14,5,4}, { 19, 19, 19, 5, 4, 14, 5, 4 },
{19,19,19,5,4,14,5,4}, { 19, 19, 19, 5, 4, 14, 5, 4 },
{28,28,28,7,6,21,7,6}, { 28, 28, 28, 7, 6, 21, 7, 6 },
{38,38,38,10,9,28,10,9}, { 38, 38, 38, 10, 9, 28, 10, 9 },
{38,38,38,10,9,28,10,9}, { 38, 38, 38, 10, 9, 28, 10, 9 },
}; };
static u8 rco_time_value[][8] = { static u8 rco_time_value[][8] = {
{0,0,0,0,0,0,0,0}, { 0, 0, 0, 0, 0, 0, 0, 0 },
{0,0,0,0,0,0,0,0}, { 0, 0, 0, 0, 0, 0, 0, 0 },
{9,2,0,2,0,7,1,1}, { 9, 2, 0, 2, 0, 7, 1, 1 },
{19,5,1,5,2,16,3,2}, { 19, 5, 1, 5, 2, 16, 3, 2 },
{19,5,1,5,2,16,3,2}, { 19, 5, 1, 5, 2, 16, 3, 2 },
{30,9,3,9,4,25,6,4}, { 30, 9, 3, 9, 4, 25, 6, 4 },
{40,12,4,12,5,34,12,5}, { 40, 12, 4, 12, 5, 34, 12, 5 },
{40,12,4,12,5,34,12,5}, { 40, 12, 4, 12, 5, 34, 12, 5 },
}; };
/* /*
* Printing configuration * Printing configuration
*/ */
/* Used for chipset type printing at boot time */ /* Used for chipset type printing at boot time */
static char* chipset_capability[] = { static char *chipset_capability[] = {
"ATA", "ATA 16", "ATA", "ATA 16",
"ATA 33", "ATA 66", "ATA 33", "ATA 66",
"ATA 100 (1st gen)", "ATA 100 (2nd gen)", "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
@ -272,7 +273,7 @@ static void sis_program_timings(ide_drive_t *drive, const u8 mode)
sis_ata133_program_timings(drive, mode); sis_ata133_program_timings(drive, mode);
} }
static void config_drive_art_rwp (ide_drive_t *drive) static void config_drive_art_rwp(ide_drive_t *drive)
{ {
ide_hwif_t *hwif = HWIF(drive); ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = to_pci_dev(hwif->dev); struct pci_dev *dev = to_pci_dev(hwif->dev);
@ -359,7 +360,8 @@ static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
} }
/* Chip detection and general config */ /* Chip detection and general config */
static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name) static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev,
const char *name)
{ {
struct pci_dev *host; struct pci_dev *host;
int i = 0; int i = 0;
@ -381,7 +383,7 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
chipset_family = ATA_100a; chipset_family = ATA_100a;
} }
pci_dev_put(host); pci_dev_put(host);
printk(KERN_INFO "SIS5513: %s %s controller\n", printk(KERN_INFO "SIS5513: %s %s controller\n",
SiSHostChipInfo[i].name, chipset_capability[chipset_family]); SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
} }
@ -448,55 +450,51 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
2/ tell old chips to allow per drive IDE timings */ 2/ tell old chips to allow per drive IDE timings */
{ {
u8 reg; u8 reg;
u16 regw; u16 regw;
switch(chipset_family) { switch (chipset_family) {
case ATA_133: case ATA_133:
/* SiS962 operation mode */ /* SiS962 operation mode */
pci_read_config_word(dev, 0x50, &regw); pci_read_config_word(dev, 0x50, &regw);
if (regw & 0x08) if (regw & 0x08)
pci_write_config_word(dev, 0x50, regw&0xfff7); pci_write_config_word(dev, 0x50, regw&0xfff7);
pci_read_config_word(dev, 0x52, &regw); pci_read_config_word(dev, 0x52, &regw);
if (regw & 0x08) if (regw & 0x08)
pci_write_config_word(dev, 0x52, regw&0xfff7); pci_write_config_word(dev, 0x52, regw&0xfff7);
break; break;
case ATA_133a: case ATA_133a:
case ATA_100: case ATA_100:
/* Fixup latency */ /* Fixup latency */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
/* Set compatibility bit */ /* Set compatibility bit */
pci_read_config_byte(dev, 0x49, &reg); pci_read_config_byte(dev, 0x49, &reg);
if (!(reg & 0x01)) { if (!(reg & 0x01))
pci_write_config_byte(dev, 0x49, reg|0x01); pci_write_config_byte(dev, 0x49, reg|0x01);
} break;
break; case ATA_100a:
case ATA_100a: case ATA_66:
case ATA_66: /* Fixup latency */
/* Fixup latency */ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
/* On ATA_66 chips the bit was elsewhere */ /* On ATA_66 chips the bit was elsewhere */
pci_read_config_byte(dev, 0x52, &reg); pci_read_config_byte(dev, 0x52, &reg);
if (!(reg & 0x04)) { if (!(reg & 0x04))
pci_write_config_byte(dev, 0x52, reg|0x04); pci_write_config_byte(dev, 0x52, reg|0x04);
} break;
break; case ATA_33:
case ATA_33: /* On ATA_33 we didn't have a single bit to set */
/* On ATA_33 we didn't have a single bit to set */ pci_read_config_byte(dev, 0x09, &reg);
pci_read_config_byte(dev, 0x09, &reg); if ((reg & 0x0f) != 0x00)
if ((reg & 0x0f) != 0x00) { pci_write_config_byte(dev, 0x09, reg&0xf0);
pci_write_config_byte(dev, 0x09, reg&0xf0); case ATA_16:
} /* force per drive recovery and active timings
case ATA_16: needed on ATA_33 and below chips */
/* force per drive recovery and active timings pci_read_config_byte(dev, 0x52, &reg);
needed on ATA_33 and below chips */ if (!(reg & 0x08))
pci_read_config_byte(dev, 0x52, &reg); pci_write_config_byte(dev, 0x52, reg|0x08);
if (!(reg & 0x08)) { break;
pci_write_config_byte(dev, 0x52, reg|0x08); }
}
break;
}
} }
return 0; return 0;
@ -546,7 +544,7 @@ static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
} }
static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif) static void __devinit init_hwif_sis5513(ide_hwif_t *hwif)
{ {
u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
@ -568,7 +566,7 @@ static const struct ide_port_info sis5513_chipset __devinitdata = {
.name = "SIS5513", .name = "SIS5513",
.init_chipset = init_chipset_sis5513, .init_chipset = init_chipset_sis5513,
.init_hwif = init_hwif_sis5513, .init_hwif = init_hwif_sis5513,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA, .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,