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IDE: Coding Style fixes to drivers/ide/pci/sis5513.c
About 300 errors and warnings fixed. File is now error free. Compile tested. [bart: minor fixes, md5sum checked] Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Paolo Ciarrocchi
Bartlomiej Zolnierkiewicz
parent
5749c84740
commit
1eb3c2ee1d
@ -59,10 +59,10 @@
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#define ATA_16 0x01
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#define ATA_33 0x02
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#define ATA_66 0x03
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#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
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#define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
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#define ATA_100 0x05
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#define ATA_133a 0x06 // SiS961b with 133 support
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#define ATA_133 0x07 // SiS962/963
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#define ATA_133a 0x06 /* SiS961b with 133 support */
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#define ATA_133 0x07 /* SiS962/963 */
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static u8 chipset_family;
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@ -111,69 +111,70 @@ static const struct {
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Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
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/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
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static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
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static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
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static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
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static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
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static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
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{0,0,0,0,0,0,0}, /* no udma */
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{0,0,0,0,0,0,0}, /* no udma */
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{3,2,1,0,0,0,0}, /* ATA_33 */
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{7,5,3,2,1,0,0}, /* ATA_66 */
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{7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
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{11,7,5,4,2,1,0}, /* ATA_100 */
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{15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
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{15,10,7,5,3,2,1}, /* ATA_133 */
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{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
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{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
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{ 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
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{ 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
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{ 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
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different cycle_time range and offset */
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{ 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
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{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
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{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
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};
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/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
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See SiS962 data sheet for more detail */
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static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
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{0,0,0,0,0,0,0}, /* no udma */
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{0,0,0,0,0,0,0}, /* no udma */
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{2,1,1,0,0,0,0},
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{4,3,2,1,0,0,0},
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{4,3,2,1,0,0,0},
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{6,4,3,1,1,1,0},
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{9,6,4,2,2,2,2},
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{9,6,4,2,2,2,2},
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{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
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{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
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{ 2, 1, 1, 0, 0, 0, 0 },
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{ 4, 3, 2, 1, 0, 0, 0 },
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{ 4, 3, 2, 1, 0, 0, 0 },
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{ 6, 4, 3, 1, 1, 1, 0 },
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{ 9, 6, 4, 2, 2, 2, 2 },
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{ 9, 6, 4, 2, 2, 2, 2 },
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};
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/* Initialize time, Active time, Recovery time vary across
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IDE clock settings. These 3 arrays hold the register value
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for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
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static u8 ini_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{2,1,0,0,0,1,0,0},
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{4,3,1,1,1,3,1,1},
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{4,3,1,1,1,3,1,1},
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{6,4,2,2,2,4,2,2},
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{9,6,3,3,3,6,3,3},
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{9,6,3,3,3,6,3,3},
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{ 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 2, 1, 0, 0, 0, 1, 0, 0 },
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{ 4, 3, 1, 1, 1, 3, 1, 1 },
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{ 4, 3, 1, 1, 1, 3, 1, 1 },
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{ 6, 4, 2, 2, 2, 4, 2, 2 },
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{ 9, 6, 3, 3, 3, 6, 3, 3 },
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{ 9, 6, 3, 3, 3, 6, 3, 3 },
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};
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static u8 act_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{9,9,9,2,2,7,2,2},
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{19,19,19,5,4,14,5,4},
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{19,19,19,5,4,14,5,4},
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{28,28,28,7,6,21,7,6},
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{38,38,38,10,9,28,10,9},
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{38,38,38,10,9,28,10,9},
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{ 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 9, 9, 9, 2, 2, 7, 2, 2 },
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{ 19, 19, 19, 5, 4, 14, 5, 4 },
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{ 19, 19, 19, 5, 4, 14, 5, 4 },
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{ 28, 28, 28, 7, 6, 21, 7, 6 },
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{ 38, 38, 38, 10, 9, 28, 10, 9 },
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{ 38, 38, 38, 10, 9, 28, 10, 9 },
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};
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static u8 rco_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{9,2,0,2,0,7,1,1},
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{19,5,1,5,2,16,3,2},
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{19,5,1,5,2,16,3,2},
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{30,9,3,9,4,25,6,4},
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{40,12,4,12,5,34,12,5},
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{40,12,4,12,5,34,12,5},
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{ 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 9, 2, 0, 2, 0, 7, 1, 1 },
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{ 19, 5, 1, 5, 2, 16, 3, 2 },
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{ 19, 5, 1, 5, 2, 16, 3, 2 },
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{ 30, 9, 3, 9, 4, 25, 6, 4 },
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{ 40, 12, 4, 12, 5, 34, 12, 5 },
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{ 40, 12, 4, 12, 5, 34, 12, 5 },
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};
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/*
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* Printing configuration
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*/
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/* Used for chipset type printing at boot time */
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static char* chipset_capability[] = {
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static char *chipset_capability[] = {
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"ATA", "ATA 16",
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"ATA 33", "ATA 66",
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"ATA 100 (1st gen)", "ATA 100 (2nd gen)",
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@ -272,7 +273,7 @@ static void sis_program_timings(ide_drive_t *drive, const u8 mode)
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sis_ata133_program_timings(drive, mode);
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}
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static void config_drive_art_rwp (ide_drive_t *drive)
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static void config_drive_art_rwp(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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@ -359,7 +360,8 @@ static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
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}
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/* Chip detection and general config */
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static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
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static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev,
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const char *name)
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{
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struct pci_dev *host;
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int i = 0;
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@ -381,7 +383,7 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
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chipset_family = ATA_100a;
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}
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pci_dev_put(host);
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printk(KERN_INFO "SIS5513: %s %s controller\n",
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SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
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}
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@ -448,55 +450,51 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
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2/ tell old chips to allow per drive IDE timings */
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{
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u8 reg;
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u16 regw;
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u8 reg;
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u16 regw;
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switch(chipset_family) {
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case ATA_133:
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/* SiS962 operation mode */
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pci_read_config_word(dev, 0x50, ®w);
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if (regw & 0x08)
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pci_write_config_word(dev, 0x50, regw&0xfff7);
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pci_read_config_word(dev, 0x52, ®w);
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if (regw & 0x08)
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pci_write_config_word(dev, 0x52, regw&0xfff7);
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break;
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case ATA_133a:
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case ATA_100:
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/* Fixup latency */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
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/* Set compatibility bit */
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pci_read_config_byte(dev, 0x49, ®);
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if (!(reg & 0x01)) {
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pci_write_config_byte(dev, 0x49, reg|0x01);
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}
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break;
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case ATA_100a:
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case ATA_66:
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/* Fixup latency */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
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switch (chipset_family) {
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case ATA_133:
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/* SiS962 operation mode */
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pci_read_config_word(dev, 0x50, ®w);
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if (regw & 0x08)
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pci_write_config_word(dev, 0x50, regw&0xfff7);
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pci_read_config_word(dev, 0x52, ®w);
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if (regw & 0x08)
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pci_write_config_word(dev, 0x52, regw&0xfff7);
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break;
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case ATA_133a:
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case ATA_100:
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/* Fixup latency */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
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/* Set compatibility bit */
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pci_read_config_byte(dev, 0x49, ®);
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if (!(reg & 0x01))
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pci_write_config_byte(dev, 0x49, reg|0x01);
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break;
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case ATA_100a:
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case ATA_66:
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/* Fixup latency */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
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/* On ATA_66 chips the bit was elsewhere */
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pci_read_config_byte(dev, 0x52, ®);
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if (!(reg & 0x04)) {
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pci_write_config_byte(dev, 0x52, reg|0x04);
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}
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break;
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case ATA_33:
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/* On ATA_33 we didn't have a single bit to set */
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pci_read_config_byte(dev, 0x09, ®);
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if ((reg & 0x0f) != 0x00) {
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pci_write_config_byte(dev, 0x09, reg&0xf0);
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}
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case ATA_16:
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/* force per drive recovery and active timings
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needed on ATA_33 and below chips */
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pci_read_config_byte(dev, 0x52, ®);
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if (!(reg & 0x08)) {
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pci_write_config_byte(dev, 0x52, reg|0x08);
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}
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break;
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}
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/* On ATA_66 chips the bit was elsewhere */
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pci_read_config_byte(dev, 0x52, ®);
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if (!(reg & 0x04))
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pci_write_config_byte(dev, 0x52, reg|0x04);
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break;
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case ATA_33:
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/* On ATA_33 we didn't have a single bit to set */
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pci_read_config_byte(dev, 0x09, ®);
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if ((reg & 0x0f) != 0x00)
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pci_write_config_byte(dev, 0x09, reg&0xf0);
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case ATA_16:
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/* force per drive recovery and active timings
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needed on ATA_33 and below chips */
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pci_read_config_byte(dev, 0x52, ®);
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if (!(reg & 0x08))
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pci_write_config_byte(dev, 0x52, reg|0x08);
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break;
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}
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}
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return 0;
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@ -546,7 +544,7 @@ static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
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return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
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}
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static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
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static void __devinit init_hwif_sis5513(ide_hwif_t *hwif)
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{
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u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
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@ -568,7 +566,7 @@ static const struct ide_port_info sis5513_chipset __devinitdata = {
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.name = "SIS5513",
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.init_chipset = init_chipset_sis5513,
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.init_hwif = init_hwif_sis5513,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
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.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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