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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (68 commits)
  [MIPS] remove Documentation/mips/GT64120.README
  [MIPS] Malta: remaining bits of the board support code cleanup
  [MIPS] Malta: make the helper function static
  [MIPS] Malta: fix braces at single statement blocks
  [MIPS] Malta, Atlas: move an extern function declaration to the header file
  [MIPS] Malta: Use C89 style for comments
  [MIPS] Malta: else should follow close brace in malta_int.c
  [MIPS] Malta: remove a superfluous comment
  [MIPS] Malta: include <linux/cpu.h> instead of <asm/cpu.h>
  [MIPS] Malta, Atlas, Sead: remove an extern from .c files
  [MIPS] Malta: fix oversized lines in malta_int.c
  [MIPS] Malta: remove a dead function declaration
  [MIPS] Malta: use tabs not spaces
  [MIPS] Malta: set up the screen info in a separate function
  [MIPS] Malta: check the PCI clock frequency in a separate function
  [MIPS] Malta: use the KERN_ facility level in printk()
  [MIPS] Malta: use Linux kernel style for structure initialization
  [MIPS]: constify function pointer tables
  [MIPS] compat: handle argument endianess of sys32_(f)truncate64 with merge_64
  [MIPS] Cobalt 64-bits kernels can be safely unmarked experimental
  ...
This commit is contained in:
Linus Torvalds 2008-01-29 22:48:03 +11:00
commit 21af0297c7
198 changed files with 3763 additions and 3078 deletions
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2
Documentation/mips/00-INDEX
View File

@ -2,5 +2,3 @@
- this file.
AU1xxx_IDE.README
- README for MIPS AU1XXX IDE driver.
GT64120.README
- README for dir with info on MIPS boards using GT-64120 or GT-64120A.

65
Documentation/mips/GT64120.README
View File

@ -1,65 +0,0 @@
README for arch/mips/gt64120 directory and subdirectories
Jun Sun, jsun@mvista.com or jsun@junsun.net
01/27, 2001
MOTIVATION
----------
Many MIPS boards share the same system controller (or CPU companian chip),
such as GT-64120. It is highly desirable to let these boards share
the same controller code instead of duplicating them.
This directory is meant to hold all MIPS boards that use GT-64120 or GT-64120A.
HOW TO ADD A BOARD
------------------
. Create a subdirectory include/asm/gt64120/<board>.
. Create a file called gt64120_dep.h under that directory.
. Modify include/asm/gt64120/gt64120.h file to include the new gt64120_dep.h
based on config options. The board-dep section is at the end of
include/asm/gt64120/gt64120.h file. There you can find all required
definitions include/asm/gt64120/<board>/gt64120_dep.h file must supply.
. Create a subdirectory arch/mips/gt64120/<board> directory to hold
board specific routines.
. The GT-64120 common code is supplied under arch/mips/gt64120/common directory.
It includes:
1) arch/mips/gt64120/pci.c -
common PCI routine, include the top-level pcibios_init()
2) arch/mips/gt64120/irq.c -
common IRQ routine, include the top-level do_IRQ()
[This part really belongs to arch/mips/kernel. jsun]
3) arch/mips/gt64120/gt_irq.c -
common IRQ routines for GT-64120 chip. Currently it only handles
the timer interrupt.
. Board-specific routines are supplied under arch/mips/gt64120/<board> dir.
1) arch/mips/gt64120/<board>/pci.c - it provides bus fixup routine
2) arch/mips/gt64120/<board>/irq.c - it provides enable/disable irqs
and board irq setup routine (irq_setup)
3) arch/mips/gt64120/<board>/int-handler.S -
The first-level interrupt dispatching routine.
4) a bunch of other "normal" stuff (setup, prom, dbg_io, reset, etc)
. Follow other "normal" procedure to modify configuration files, etc.
TO-DO LIST
----------
. Expand arch/mips/gt64120/gt_irq.c to handle all GT-64120 interrupts.
We probably need to introduce GT_IRQ_BASE in board-dep header file,
which is used the starting irq_nr for all GT irqs.
A function, gt64120_handle_irq(), will be added so that the first-level
irq dispatcher will call this function if it detects an interrupt
from GT-64120.
. More support for GT-64120 PCI features (2nd PCI bus, perhaps)

181
arch/mips/Kconfig
View File

@ -37,16 +37,6 @@ config BASLER_EXCITE
The eXcite is a smart camera platform manufactured by
Basler Vision Technologies AG.
config BASLER_EXCITE_PROTOTYPE
bool "Support for pre-release units"
depends on BASLER_EXCITE
default n
help
Pre-series (prototype) units are different from later ones in
some ways. Select this option if you have one of these. Please
note that a kernel built with this option selected will not be
able to run on normal units.
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
@ -82,7 +72,7 @@ config MIPS_COBALT
select SYS_HAS_CPU_NEVADA
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
@ -91,6 +81,9 @@ config MACH_DECSTATION
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select CPU_DADDI_WORKAROUNDS if 64BIT
select CPU_R4000_WORKAROUNDS if 64BIT
select CPU_R4400_WORKAROUNDS if 64BIT
select DMA_NONCOHERENT
select NO_IOPORT
select IRQ_CPU
@ -124,12 +117,12 @@ config MACH_JAZZ
select ARCH_MAY_HAVE_PC_FDC
select CEVT_R4K
select CSRC_R4K
select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
select GENERIC_ISA_DMA
select IRQ_CPU
select I8253
select I8259
select ISA
select PCSPEAKER
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
@ -187,6 +180,7 @@ config LEMOTE_FULONG
config MIPS_ATLAS
bool "MIPS Atlas board"
select BOOT_ELF32
select BOOT_RAW
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
@ -219,6 +213,7 @@ config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select BOOT_RAW
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
@ -364,35 +359,6 @@ config PMC_YOSEMITE
Yosemite is an evaluation board for the RM9000x2 processor
manufactured by PMC-Sierra.
config QEMU
bool "Qemu"
select CEVT_R4K
select CSRC_R4K
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
select I8253
select I8259
select IRQ_CPU
select ISA
select PCSPEAKER
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
select NR_CPUS_DEFAULT_1
select SYS_SUPPORTS_SMP
help
Qemu is a software emulator which among other architectures also
can simulate a MIPS32 4Kc system. This patch adds support for the
system architecture that currently is being simulated by Qemu. It
will eventually be removed again when Qemu has the capability to
simulate actual MIPS hardware platforms. More information on Qemu
can be found at http://www.linux-mips.org/wiki/Qemu.
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
select ARC
@ -400,6 +366,7 @@ config SGI_IP22
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DEFAULT_SGI_PARTITION
select DMA_NONCOHERENT
select HW_HAS_EISA
select I8253
@ -407,6 +374,12 @@ config SGI_IP22
select IP22_CPU_SCACHE
select IRQ_CPU
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select SGI_HAS_DS1286
select SGI_HAS_I8042
select SGI_HAS_INDYDOG
select SGI_HAS_SEEQ
select SGI_HAS_WD93
select SGI_HAS_ZILOG
select SWAP_IO_SPACE
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
@ -424,6 +397,7 @@ config SGI_IP27
select ARC
select ARC64
select BOOT_ELF64
select DEFAULT_SGI_PARTITION
select DMA_IP27
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
@ -440,6 +414,36 @@ config SGI_IP27
workstations. To compile a Linux kernel that runs on these, say Y
here.
config SGI_IP28
bool "SGI IP28 (Indigo2 R10k) (EXPERIMENTAL)"
depends on EXPERIMENTAL
select ARC
select ARC64
select BOOT_ELF64
select CEVT_R4K
select CSRC_R4K
select DEFAULT_SGI_PARTITION
select DMA_NONCOHERENT
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select IRQ_CPU
select HW_HAS_EISA
select I8253
select I8259
select SGI_HAS_DS1286
select SGI_HAS_I8042
select SGI_HAS_INDYDOG
select SGI_HAS_SEEQ
select SGI_HAS_WD93
select SGI_HAS_ZILOG
select SWAP_IO_SPACE
select SYS_HAS_CPU_R10000
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
This is the SGI Indigo2 with R10000 processor. To compile a Linux
kernel that runs on these, say Y here.
config SGI_IP32
bool "SGI IP32 (O2)"
select ARC
@ -545,19 +549,6 @@ config SIBYTE_SENTOSA
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_PTSWARM
bool "Sibyte BCM91250PT-PTSWARM"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_BIGSUR
bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32
@ -575,10 +566,12 @@ config SNI_RM
bool "SNI RM200/300/400"
select ARC if CPU_LITTLE_ENDIAN
select ARC32 if CPU_LITTLE_ENDIAN
select SNIPROM if CPU_BIG_ENDIAN
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HW_HAS_EISA
@ -587,7 +580,6 @@ config SNI_RM
select I8253
select I8259
select ISA
select PCSPEAKER
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
@ -690,6 +682,7 @@ config WR_PPMC
endchoice
source "arch/mips/au1000/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
@ -797,10 +790,6 @@ config DMA_COHERENT
config DMA_IP27
bool
config DMA_IP32
bool
select DMA_NEED_PCI_MAP_STATE
config DMA_NONCOHERENT
bool
select DMA_NEED_PCI_MAP_STATE
@ -956,16 +945,40 @@ config EMMA2RH
config SERIAL_RM9000
bool
config SGI_HAS_DS1286
bool
config SGI_HAS_INDYDOG
bool
config SGI_HAS_SEEQ
bool
config SGI_HAS_WD93
bool
config SGI_HAS_ZILOG
bool
config SGI_HAS_I8042
bool
config DEFAULT_SGI_PARTITION
bool
config ARC32
bool
config SNIPROM
bool
config BOOT_ELF32
bool
config MIPS_L1_CACHE_SHIFT
int
default "4" if MACH_DECSTATION
default "7" if SGI_IP27 || SNI_RM
default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
default "4" if PMC_MSP4200_EVAL
default "5"
@ -974,7 +987,7 @@ config HAVE_STD_PC_SERIAL_PORT
config ARC_CONSOLE
bool "ARC console support"
depends on SGI_IP22 || (SNI_RM && CPU_LITTLE_ENDIAN)
depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
config ARC_MEMORY
bool
@ -983,7 +996,7 @@ config ARC_MEMORY
config ARC_PROMLIB
bool
depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32
depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
default y
config ARC64
@ -1443,7 +1456,9 @@ config MIPS_MT_SMP
select MIPS_MT
select NR_CPUS_DEFAULT_2
select SMP
select SYS_SUPPORTS_SCHED_SMT if SMP
select SYS_SUPPORTS_SMP
select SMP_UP
help
This is a kernel model which is also known a VSMP or lately
has been marketesed into SMVP.
@ -1460,6 +1475,7 @@ config MIPS_MT_SMTC
select NR_CPUS_DEFAULT_8
select SMP
select SYS_SUPPORTS_SMP
select SMP_UP
help
This is a kernel model which is known a SMTC or lately has been
marketesed into SMVP.
@ -1469,6 +1485,19 @@ endchoice
config MIPS_MT
bool
config SCHED_SMT
bool "SMT (multithreading) scheduler support"
depends on SYS_SUPPORTS_SCHED_SMT
default n
help
SMT scheduler support improves the CPU scheduler's decision making
when dealing with MIPS MT enabled cores at a cost of slightly
increased overhead in some places. If unsure say N here.
config SYS_SUPPORTS_SCHED_SMT
bool
config SYS_SUPPORTS_MULTITHREADING
bool
@ -1589,15 +1618,6 @@ config CPU_HAS_SMARTMIPS
config CPU_HAS_WB
bool
config 64BIT_CONTEXT
bool "Save 64bit integer registers"
depends on 32BIT && CPU_LOONGSON2
help
Loongson2 CPU is 64bit , when used in 32BIT mode, its integer
registers can still be accessed as 64bit, mainly for multimedia
instructions. We must have all 64bit save/restored to make sure
those instructions to get correct result.
#
# Vectored interrupt mode is an R2 feature
#
@ -1618,6 +1638,19 @@ config CPU_HAS_SYNC
config GENERIC_CLOCKEVENTS_BROADCAST
bool
#
# CPU non-features
#
config CPU_DADDI_WORKAROUNDS
bool
config CPU_R4000_WORKAROUNDS
bool
select CPU_R4400_WORKAROUNDS
config CPU_R4400_WORKAROUNDS
bool
#
# Use the generic interrupt handling code in kernel/irq/:
#
@ -1721,6 +1754,9 @@ config SMP
If you don't know what to do here, say N.
config SMP_UP
bool
config SYS_SUPPORTS_SMP
bool
@ -1978,9 +2014,6 @@ config MMU
config I8253
bool
config PCSPEAKER
bool
config ZONE_DMA32
bool

40
arch/mips/Makefile
View File

@ -141,6 +141,10 @@ cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
-Wa,--trap
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
ifdef CONFIG_CPU_SB1
ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
MODFLAGS += -msb1-pass1-workarounds
@ -152,6 +156,8 @@ endif
#
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
libs-y += arch/mips/fw/lib/
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
#
@ -308,7 +314,7 @@ core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/
cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas
cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips
load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000
all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec
all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin
#
# MIPS Malta board
@ -316,7 +322,7 @@ all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec
core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/
cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips
load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
all-$(CONFIG_MIPS_MALTA) := vmlinux.srec
all-$(CONFIG_MIPS_MALTA) := vmlinux.bin
#
# MIPS SEAD board
@ -348,14 +354,6 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/
cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite
load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
#
# Qemu simulating MIPS32 4Kc
#
core-$(CONFIG_QEMU) += arch/mips/qemu/
cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu
load-$(CONFIG_QEMU) += 0xffffffff80010000
all-$(CONFIG_QEMU) := vmlinux.bin
#
# Basler eXcite
#
@ -474,6 +472,20 @@ OBJCOPYFLAGS := --change-addresses=0x57ffffff80000000
endif
endif
#
# SGI IP28 (Indigo2 R10k)
#
# Set the load address to >= 0xa800000020080000 if you want to leave space for
# symmon, 0xa800000020004000 for production kernels ? Note that the value must
# be 16kb aligned or the handling of the current variable will break.
# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
#
#core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o
core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28
#cflags-$(CONFIG_SGI_IP28) += -Iinclude/asm-mips/mach-ip28
load-$(CONFIG_SGI_IP28) += 0xa800000020004000
#
# SGI-IP32 (O2)
#
@ -602,9 +614,11 @@ ifdef CONFIG_64BIT
endif
endif
ifeq ($(KBUILD_SYM32), y)
ifeq ($(call cc-option-yn,-msym32), y)
cflags-y += -msym32 -DKBUILD_64BIT_SYM32
ifeq ($(KBUILD_SYM32)$(call cc-option-yn,-msym32), yy)
cflags-y += -msym32 -DKBUILD_64BIT_SYM32
else
ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y)
$(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32)
endif
endif
endif

21
arch/mips/au1000/common/au1xxx_irqmap.c
View File

@ -25,27 +25,10 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/mach-au1x00/au1000.h>
#include <au1000.h>
/* The IC0 interrupt table. This is processor, rather than
* board dependent, so no reason to keep this info in the board

2
arch/mips/au1000/common/dbdma.c
View File

@ -179,7 +179,7 @@ static dbdev_tab_t dbdev_tab[] = {
{ 0, 0, 0, 0, 0, 0, 0 },
};
#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];

11
arch/mips/au1000/db1x00/init.c
View File

@ -57,17 +57,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
/* Set the platform # */
#if defined(CONFIG_MIPS_DB1550)
mips_machtype = MACH_DB1550;
#elif defined(CONFIG_MIPS_DB1500)
mips_machtype = MACH_DB1500;
#elif defined(CONFIG_MIPS_DB1100)
mips_machtype = MACH_DB1100;
#else
mips_machtype = MACH_DB1000;
#endif
prom_init_cmdline();
memsize_str = prom_getenv("memsize");

2
arch/mips/au1000/mtx-1/init.c
View File

@ -54,8 +54,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machtype = MACH_MTX1; /* set the platform # */
prom_init_cmdline();
memsize_str = prom_getenv("memsize");

27
arch/mips/au1000/mtx-1/platform.c
View File

@ -22,9 +22,32 @@
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <asm/gpio.h>
static struct gpio_keys_button mtx1_gpio_button[] = {
{
.gpio = 207,
.code = BTN_0,
.desc = "System button",
}
};
static struct gpio_keys_platform_data mtx1_buttons_data = {
.buttons = mtx1_gpio_button,
.nbuttons = ARRAY_SIZE(mtx1_gpio_button),
};
static struct platform_device mtx1_button = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &mtx1_buttons_data,
}
};
static struct resource mtx1_wdt_res[] = {
[0] = {
.start = 15,
@ -66,11 +89,13 @@ static struct platform_device mtx1_gpio_leds = {
static struct __initdata platform_device * mtx1_devs[] = {
&mtx1_gpio_leds,
&mtx1_wdt
&mtx1_wdt,
&mtx1_button
};
static int __init mtx1_register_devices(void)
{
gpio_direction_input(207);
return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
}

2
arch/mips/au1000/pb1000/init.c
View File

@ -52,8 +52,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machtype = MACH_PB1000;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {

2
arch/mips/au1000/pb1100/init.c
View File

@ -53,8 +53,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg3;
mips_machtype = MACH_PB1100;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");

2
arch/mips/au1000/pb1200/init.c
View File

@ -53,8 +53,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machtype = MACH_PB1200;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {

2
arch/mips/au1000/pb1500/init.c
View File

@ -53,8 +53,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machtype = MACH_PB1500;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {

2
arch/mips/au1000/pb1550/init.c
View File

@ -53,8 +53,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machtype = MACH_PB1550;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str) {

2
arch/mips/au1000/xxs1500/init.c
View File

@ -52,8 +52,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machtype = MACH_XXS1500; /* set the platform # */
prom_init_cmdline();
memsize_str = prom_getenv("memsize");

9
arch/mips/basler/excite/Kconfig Normal file
View File

@ -0,0 +1,9 @@
config BASLER_EXCITE_PROTOTYPE
bool "Support for pre-release units"
depends on BASLER_EXCITE
default n
help
Pre-series (prototype) units are different from later ones in
some ways. Select this option if you have one of these. Please
note that a kernel built with this option selected will not be
able to run on normal units.

2
arch/mips/basler/excite/excite_iodev.c
View File

@ -48,7 +48,7 @@ static DECLARE_WAIT_QUEUE_HEAD(wq);
static struct file_operations fops =
static const struct file_operations fops =
{
.owner = THIS_MODULE,
.open = iodev_open,

2
arch/mips/basler/excite/excite_prom.c
View File

@ -135,8 +135,6 @@ void __init prom_init(void)
#ifdef CONFIG_64BIT
# error 64 bit support not implemented
#endif /* CONFIG_64BIT */
mips_machtype = MACH_TITAN_EXCITE;
}
/* This is called from free_initmem(), so we need to provide it */

24
arch/mips/cobalt/reset.c
View File

@ -10,9 +10,10 @@
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/leds.h>
#include <asm/processor.h>
#include <cobalt.h>
#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
@ -29,28 +30,15 @@ device_initcall(ledtrig_power_off_init);
void cobalt_machine_halt(void)
{
int state, last, diff;
unsigned long mark;
/*
* turn on power off LED on RaQ
*
* restart if ENTER and SELECT are pressed
*/
last = COBALT_KEY_PORT;
led_trigger_event(power_off_led_trigger, LED_FULL);
for (state = 0;;) {
diff = COBALT_KEY_PORT ^ last;
last ^= diff;
if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
writeb(RESET, RESET_PORT);
for (mark = jiffies; jiffies - mark < HZ;)
;
local_irq_disable();
while (1) {
if (cpu_wait)
cpu_wait();
}
}

2
arch/mips/configs/atlas_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_MIPS_ATLAS=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_MIPS_ATLAS=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/bigsur_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_SIBYTE_BIGSUR=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/capcella_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/cobalt_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MIPS_COBALT=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MIPS_COBALT=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/db1000_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/db1100_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/db1200_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/db1500_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/db1550_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/decstation_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_MACH_DECSTATION=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_MACH_DECSTATION=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/e55_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/emma2rh_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
CONFIG_MARKEINS=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_MARKEINS=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/excite_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_BASLER_EXCITE=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_BASLER_EXCITE=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/fulong_defconfig
View File

@ -23,7 +23,6 @@ CONFIG_LEMOTE_FULONG=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -33,7 +32,6 @@ CONFIG_LEMOTE_FULONG=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/ip22_defconfig
View File

@ -25,7 +25,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
CONFIG_SGI_IP22=y
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -36,7 +35,6 @@ CONFIG_SGI_IP22=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/ip27_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MIPS=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
CONFIG_SGI_IP27=y
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_SGI_IP27=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/ip32_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_SGI_IP32=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/jazz_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_MACH_JAZZ=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_MACH_JAZZ=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

17
arch/mips/configs/jmr3927_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MIPS=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MIPS=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
CONFIG_TOSHIBA_JMR3927=y
@ -464,7 +462,6 @@ CONFIG_SERIAL_TXX9_STDSERIAL=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
# CONFIG_R3964 is not set
@ -482,6 +479,20 @@ CONFIG_DEVPORT=y
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_TXX9_WDT=y
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# Multifunction device drivers

2
arch/mips/configs/lasat_defconfig
View File

@ -25,7 +25,6 @@ CONFIG_LASAT=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -36,7 +35,6 @@ CONFIG_LASAT=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/malta_defconfig
View File

@ -25,7 +25,6 @@ CONFIG_MIPS_MALTA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -36,7 +35,6 @@ CONFIG_MIPS_MALTA=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/mipssim_defconfig
View File

@ -26,7 +26,6 @@ CONFIG_MIPS_SIM=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -37,7 +36,6 @@ CONFIG_MIPS_SIM=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/mpc30x_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/msp71xx_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MACH_VR41XX is not set
CONFIG_PMC_MSP=y
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_PMC_MSP=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

3
arch/mips/configs/mtx1_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_ALCHEMY=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_ALCHEMY=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set
@ -1617,6 +1615,7 @@ CONFIG_INPUT_EVBUG=m
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_XTKBD=m

2
arch/mips/configs/pb1100_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/pb1500_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/pb1550_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -48,7 +47,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/pnx8550-jbs_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_PNX8550_JBS=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_PNX8550_JBS=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/pnx8550-stb810_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
CONFIG_PNX8550_STB810=y
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_PNX8550_STB810=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/qemu_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
CONFIG_QEMU=y
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_QEMU=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

17
arch/mips/configs/rbhma4200_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MIPS=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MIPS=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set
@ -431,7 +429,6 @@ CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
# CONFIG_R3964 is not set
@ -449,6 +446,20 @@ CONFIG_DEVPORT=y
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_TXX9_WDT=m
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# Multifunction device drivers

17
arch/mips/configs/rbhma4500_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MIPS=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MIPS=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set
@ -450,7 +448,6 @@ CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
# CONFIG_R3964 is not set
@ -479,6 +476,20 @@ CONFIG_SPI_AT25=y
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_TXX9_WDT=m
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# Multifunction device drivers

2
arch/mips/configs/rm200_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/sb1250-swarm_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_SIBYTE_SWARM=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/sead_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_MIPS_SEAD=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_MIPS_SEAD=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/tb0219_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/tb0226_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/tb0287_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/workpad_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/configs/wrppmc_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_WR_PPMC=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_WR_PPMC=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

2
arch/mips/configs/yosemite_defconfig
View File

@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_PMC_YOSEMITE=y
# CONFIG_QEMU is not set
# CONFIG_MARKEINS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
@ -47,7 +46,6 @@ CONFIG_PMC_YOSEMITE=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set

1
arch/mips/dec/time.c
View File

@ -161,7 +161,6 @@ static cycle_t dec_ioasic_hpt_read(void)
void __init plat_time_init(void)
{
mips_timer_state = dec_timer_state;
mips_timer_ack = dec_timer_ack;
if (!cpu_has_counter && IOASIC)

2
arch/mips/defconfig
View File

@ -25,7 +25,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
CONFIG_SGI_IP22=y
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
@ -36,7 +35,6 @@ CONFIG_SGI_IP22=y
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set

2
arch/mips/fw/arc/cmdline.c
View File

@ -52,7 +52,7 @@ static char * __init move_firmware_args(char* cp)
strcat(cp, used_arc[i][1]);
cp += strlen(used_arc[i][1]);
/* ... and now the argument */
s = strstr(prom_argv(actr), "=");
s = strchr(prom_argv(actr), '=');
if (s) {
s++;
strcpy(cp, s);

8
arch/mips/fw/arc/init.c
View File

@ -12,6 +12,7 @@
#include <asm/bootinfo.h>
#include <asm/sgialib.h>
#include <asm/smp-ops.h>
#undef DEBUG_PROM_INIT
@ -48,4 +49,11 @@ void __init prom_init(void)
ArcRead(0, &c, 1, &cnt);
ArcEnterInteractiveMode();
#endif
#ifdef CONFIG_SGI_IP27
{
extern struct plat_smp_ops ip27_smp_ops;
register_smp_ops(&ip27_smp_ops);
}
#endif
}

184
arch/mips/fw/cfe/cfe_api.c
View File

@ -16,19 +16,16 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* *********************************************************************
*
* Broadcom Common Firmware Environment (CFE)
*
* Device Function stubs File: cfe_api.c
*
* This module contains device function stubs (small routines to
* call the standard "iocb" interface entry point to CFE).
* There should be one routine here per iocb function call.
*
* Authors: Mitch Lichtenberg, Chris Demetriou
*
********************************************************************* */
/*
*
* Broadcom Common Firmware Environment (CFE)
*
* This module contains device function stubs (small routines to
* call the standard "iocb" interface entry point to CFE).
* There should be one routine here per iocb function call.
*
* Authors: Mitch Lichtenberg, Chris Demetriou
*/
#include <asm/fw/cfe/cfe_api.h>
#include "cfe_api_int.h"
@ -37,12 +34,8 @@
#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n))
#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x))
#ifdef CFE_API_IMPL_NAMESPACE
#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a)
#endif
int cfe_iocb_dispatch(cfe_xiocb_t * xiocb);
int cfe_iocb_dispatch(struct cfe_xiocb *xiocb);
#if defined(CFE_API_common) || defined(CFE_API_ALL)
/*
* Declare the dispatch function with args of "intptr_t".
* This makes sure whatever model we're compiling in
@ -53,27 +46,25 @@ int cfe_iocb_dispatch(cfe_xiocb_t * xiocb);
*/
static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0;
static cfe_xuint_t cfe_handle = 0;
static u64 cfe_handle = 0;
int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept)
int cfe_init(u64 handle, u64 ept)
{
cfe_dispfunc = NATIVE_FROM_XPTR(ept);
cfe_handle = handle;
return 0;
}
int cfe_iocb_dispatch(cfe_xiocb_t * xiocb)
int cfe_iocb_dispatch(struct cfe_xiocb * xiocb)
{
if (!cfe_dispfunc)
return -1;
return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb);
}
#endif /* CFE_API_common || CFE_API_ALL */
#if defined(CFE_API_close) || defined(CFE_API_ALL)
int cfe_close(int handle)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
xiocb.xiocb_status = 0;
@ -86,18 +77,16 @@ int cfe_close(int handle)
return xiocb.xiocb_status;
}
#endif /* CFE_API_close || CFE_API_ALL */
#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL)
int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
xiocb.plist.xiocb_cpuctl.gp_val = gp;
@ -109,18 +98,16 @@ int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
return xiocb.xiocb_status;
}
#endif /* CFE_API_cpu_start || CFE_API_ALL */
#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL)
int cfe_cpu_stop(int cpu)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
@ -128,18 +115,16 @@ int cfe_cpu_stop(int cpu)
return xiocb.xiocb_status;
}
#endif /* CFE_API_cpu_stop || CFE_API_ALL */
#if defined(CFE_API_enumenv) || defined(CFE_API_ALL)
int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
xiocb.plist.xiocb_envbuf.enum_idx = idx;
xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
xiocb.plist.xiocb_envbuf.name_length = namelen;
@ -150,20 +135,17 @@ int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
return xiocb.xiocb_status;
}
#endif /* CFE_API_enumenv || CFE_API_ALL */
#if defined(CFE_API_enummem) || defined(CFE_API_ALL)
int
cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length,
cfe_xuint_t * type)
cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = flags;
xiocb.xiocb_psize = sizeof(xiocb_meminfo_t);
xiocb.xiocb_psize = sizeof(struct xiocb_meminfo);
xiocb.plist.xiocb_meminfo.mi_idx = idx;
cfe_iocb_dispatch(&xiocb);
@ -177,30 +159,26 @@ cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length,
return 0;
}
#endif /* CFE_API_enummem || CFE_API_ALL */
#if defined(CFE_API_exit) || defined(CFE_API_ALL)
int cfe_exit(int warm, int status)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
xiocb.xiocb_psize = sizeof(xiocb_exitstat_t);
xiocb.xiocb_psize = sizeof(struct xiocb_exitstat);
xiocb.plist.xiocb_exitstat.status = status;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
#endif /* CFE_API_exit || CFE_API_ALL */
#if defined(CFE_API_flushcache) || defined(CFE_API_ALL)
int cfe_flushcache(int flg)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
xiocb.xiocb_status = 0;
@ -212,34 +190,30 @@ int cfe_flushcache(int flg)
return xiocb.xiocb_status;
}
#endif /* CFE_API_flushcache || CFE_API_ALL */
#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL)
int cfe_getdevinfo(char *name)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
xiocb.plist.xiocb_buffer.buf_offset = 0;
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
xiocb.plist.xiocb_buffer.buf_length = strlen(name);
cfe_iocb_dispatch(&xiocb);
if (xiocb.xiocb_status < 0)
return xiocb.xiocb_status;
return xiocb.plist.xiocb_buffer.buf_devflags;
return xiocb.plist.xiocb_buffer.buf_ioctlcmd;
}
#endif /* CFE_API_getdevinfo || CFE_API_ALL */
#if defined(CFE_API_getenv) || defined(CFE_API_ALL)
int cfe_getenv(char *name, char *dest, int destlen)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
*dest = 0;
@ -247,10 +221,10 @@ int cfe_getenv(char *name, char *dest, int destlen)
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
xiocb.plist.xiocb_envbuf.enum_idx = 0;
xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
xiocb.plist.xiocb_envbuf.name_length = strlen(name);
xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest);
xiocb.plist.xiocb_envbuf.val_length = destlen;
@ -258,18 +232,16 @@ int cfe_getenv(char *name, char *dest, int destlen)
return xiocb.xiocb_status;
}
#endif /* CFE_API_getenv || CFE_API_ALL */
#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL)
int cfe_getfwinfo(cfe_fwinfo_t * info)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t);
xiocb.xiocb_psize = sizeof(struct xiocb_fwinfo);
cfe_iocb_dispatch(&xiocb);
@ -292,12 +264,10 @@ int cfe_getfwinfo(cfe_fwinfo_t * info)
return 0;
}
#endif /* CFE_API_getfwinfo || CFE_API_ALL */
#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL)
int cfe_getstdhandle(int flg)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
xiocb.xiocb_status = 0;
@ -311,23 +281,17 @@ int cfe_getstdhandle(int flg)
return xiocb.xiocb_status;
return xiocb.xiocb_handle;
}
#endif /* CFE_API_getstdhandle || CFE_API_ALL */
#if defined(CFE_API_getticks) || defined(CFE_API_ALL)
int64_t
#ifdef CFE_API_IMPL_NAMESPACE
__cfe_getticks(void)
#else
cfe_getticks(void)
#endif
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_time_t);
xiocb.xiocb_psize = sizeof(struct xiocb_time);
xiocb.plist.xiocb_time.ticks = 0;
cfe_iocb_dispatch(&xiocb);
@ -335,18 +299,16 @@ cfe_getticks(void)
return xiocb.plist.xiocb_time.ticks;
}
#endif /* CFE_API_getticks || CFE_API_ALL */
#if defined(CFE_API_inpstat) || defined(CFE_API_ALL)
int cfe_inpstat(int handle)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_inpstat_t);
xiocb.xiocb_psize = sizeof(struct xiocb_inpstat);
xiocb.plist.xiocb_inpstat.inp_status = 0;
cfe_iocb_dispatch(&xiocb);
@ -355,20 +317,18 @@ int cfe_inpstat(int handle)
return xiocb.xiocb_status;
return xiocb.plist.xiocb_inpstat.inp_status;
}
#endif /* CFE_API_inpstat || CFE_API_ALL */
#if defined(CFE_API_ioctl) || defined(CFE_API_ALL)
int
cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
int length, int *retlen, cfe_xuint_t offset)
int length, int *retlen, u64 offset)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum;
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
@ -380,21 +340,19 @@ cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
*retlen = xiocb.plist.xiocb_buffer.buf_retlen;
return xiocb.xiocb_status;
}
#endif /* CFE_API_ioctl || CFE_API_ALL */
#if defined(CFE_API_open) || defined(CFE_API_ALL)
int cfe_open(char *name)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
xiocb.plist.xiocb_buffer.buf_offset = 0;
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
xiocb.plist.xiocb_buffer.buf_length = strlen(name);
cfe_iocb_dispatch(&xiocb);
@ -402,27 +360,21 @@ int cfe_open(char *name)
return xiocb.xiocb_status;
return xiocb.xiocb_handle;
}
#endif /* CFE_API_open || CFE_API_ALL */
#if defined(CFE_API_read) || defined(CFE_API_ALL)
int cfe_read(int handle, unsigned char *buffer, int length)
{
return cfe_readblk(handle, 0, buffer, length);
}
#endif /* CFE_API_read || CFE_API_ALL */
#if defined(CFE_API_readblk) || defined(CFE_API_ALL)
int
cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer,
int length)
int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
xiocb.plist.xiocb_buffer.buf_length = length;
@ -433,62 +385,41 @@ cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer,
return xiocb.xiocb_status;
return xiocb.plist.xiocb_buffer.buf_retlen;
}
#endif /* CFE_API_readblk || CFE_API_ALL */
#if defined(CFE_API_setenv) || defined(CFE_API_ALL)
int cfe_setenv(char *name, char *val)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
xiocb.plist.xiocb_envbuf.enum_idx = 0;
xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
xiocb.plist.xiocb_envbuf.name_length = strlen(name);
xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val);
xiocb.plist.xiocb_envbuf.val_length = strlen(val);
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
#endif /* CFE_API_setenv || CFE_API_ALL */
#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \
&& !defined(CFE_API_STRLEN_CUSTOM)
int cfe_strlen(char *name)
{
int count = 0;
while (*name++)
count++;
return count;
}
#endif /* CFE_API_strlen || CFE_API_ALL */
#if defined(CFE_API_write) || defined(CFE_API_ALL)
int cfe_write(int handle, unsigned char *buffer, int length)
{
return cfe_writeblk(handle, 0, buffer, length);
}
#endif /* CFE_API_write || CFE_API_ALL */
#if defined(CFE_API_writeblk) || defined(CFE_API_ALL)
int
cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer,
int length)
int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
{
cfe_xiocb_t xiocb;
struct cfe_xiocb xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
xiocb.plist.xiocb_buffer.buf_length = length;
@ -499,4 +430,3 @@ cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer,
return xiocb.xiocb_status;
return xiocb.plist.xiocb_buffer.buf_retlen;
}
#endif /* CFE_API_writeblk || CFE_API_ALL */

176
arch/mips/fw/cfe/cfe_api_int.h
View File

@ -15,28 +15,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* *********************************************************************
*
* Broadcom Common Firmware Environment (CFE)
*
* Device function prototypes File: cfe_api_int.h
*
* This header defines all internal types and macros for the
* library. This is stuff that's not exported to an app
* using the library.
*
* Authors: Mitch Lichtenberg, Chris Demetriou
*
********************************************************************* */
#ifndef CFE_API_INT_H
#define CFE_API_INT_H
/* *********************************************************************
* Constants
********************************************************************* */
/*
* Constants.
*/
#define CFE_CMD_FW_GETINFO 0
#define CFE_CMD_FW_RESTART 1
#define CFE_CMD_FW_BOOT 2
@ -64,89 +48,101 @@
#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
/* *********************************************************************
* Structures
********************************************************************* */
/*
* Structures.
*/
typedef uint64_t cfe_xuint_t;
typedef int64_t cfe_xint_t;
typedef int64_t cfe_xptr_t;
/* eeek, signed "pointers" */
typedef s64 cfe_xptr_t;
typedef struct xiocb_buffer_s {
cfe_xuint_t buf_offset; /* offset on device (bytes) */
struct xiocb_buffer {
u64 buf_offset; /* offset on device (bytes) */
cfe_xptr_t buf_ptr; /* pointer to a buffer */
cfe_xuint_t buf_length; /* length of this buffer */
cfe_xuint_t buf_retlen; /* returned length (for read ops) */
cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
} xiocb_buffer_t;
u64 buf_length; /* length of this buffer */
u64 buf_retlen; /* returned length (for read ops) */
u64 buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
};
#define buf_devflags buf_ioctlcmd /* returned device info flags */
struct xiocb_inpstat {
u64 inp_status; /* 1 means input available */
};
typedef struct xiocb_inpstat_s {
cfe_xuint_t inp_status; /* 1 means input available */
} xiocb_inpstat_t;
typedef struct xiocb_envbuf_s {
cfe_xint_t enum_idx; /* 0-based enumeration index */
struct xiocb_envbuf {
s64 enum_idx; /* 0-based enumeration index */
cfe_xptr_t name_ptr; /* name string buffer */
cfe_xint_t name_length; /* size of name buffer */
s64 name_length; /* size of name buffer */
cfe_xptr_t val_ptr; /* value string buffer */
cfe_xint_t val_length; /* size of value string buffer */
} xiocb_envbuf_t;
s64 val_length; /* size of value string buffer */
};
typedef struct xiocb_cpuctl_s {
cfe_xuint_t cpu_number; /* cpu number to control */
cfe_xuint_t cpu_command; /* command to issue to CPU */
cfe_xuint_t start_addr; /* CPU start address */
cfe_xuint_t gp_val; /* starting GP value */
cfe_xuint_t sp_val; /* starting SP value */
cfe_xuint_t a1_val; /* starting A1 value */
} xiocb_cpuctl_t;
struct xiocb_cpuctl {
u64 cpu_number; /* cpu number to control */
u64 cpu_command; /* command to issue to CPU */
u64 start_addr; /* CPU start address */
u64 gp_val; /* starting GP value */
u64 sp_val; /* starting SP value */
u64 a1_val; /* starting A1 value */
};
typedef struct xiocb_time_s {
cfe_xint_t ticks; /* current time in ticks */
} xiocb_time_t;
struct xiocb_time {
s64 ticks; /* current time in ticks */
};
typedef struct xiocb_exitstat_s {
cfe_xint_t status;
} xiocb_exitstat_t;
struct xiocb_exitstat{
s64 status;
};
typedef struct xiocb_meminfo_s {
cfe_xint_t mi_idx; /* 0-based enumeration index */
cfe_xint_t mi_type; /* type of memory block */
cfe_xuint_t mi_addr; /* physical start address */
cfe_xuint_t mi_size; /* block size */
} xiocb_meminfo_t;
struct xiocb_meminfo {
s64 mi_idx; /* 0-based enumeration index */
s64 mi_type; /* type of memory block */
u64 mi_addr; /* physical start address */
u64 mi_size; /* block size */
};
typedef struct xiocb_fwinfo_s {
cfe_xint_t fwi_version; /* major, minor, eco version */
cfe_xint_t fwi_totalmem; /* total installed mem */
cfe_xint_t fwi_flags; /* various flags */
cfe_xint_t fwi_boardid; /* board ID */
cfe_xint_t fwi_bootarea_va; /* VA of boot area */
cfe_xint_t fwi_bootarea_pa; /* PA of boot area */
cfe_xint_t fwi_bootarea_size; /* size of boot area */
cfe_xint_t fwi_reserved1;
cfe_xint_t fwi_reserved2;
cfe_xint_t fwi_reserved3;
} xiocb_fwinfo_t;
struct xiocb_fwinfo {
s64 fwi_version; /* major, minor, eco version */
s64 fwi_totalmem; /* total installed mem */
s64 fwi_flags; /* various flags */
s64 fwi_boardid; /* board ID */
s64 fwi_bootarea_va; /* VA of boot area */
s64 fwi_bootarea_pa; /* PA of boot area */
s64 fwi_bootarea_size; /* size of boot area */
s64 fwi_reserved1;
s64 fwi_reserved2;
s64 fwi_reserved3;
};
typedef struct cfe_xiocb_s {
cfe_xuint_t xiocb_fcode; /* IOCB function code */
cfe_xint_t xiocb_status; /* return status */
cfe_xint_t xiocb_handle; /* file/device handle */
cfe_xuint_t xiocb_flags; /* flags for this IOCB */
cfe_xuint_t xiocb_psize; /* size of parameter list */
struct cfe_xiocb {
u64 xiocb_fcode; /* IOCB function code */
s64 xiocb_status; /* return status */
s64 xiocb_handle; /* file/device handle */
u64 xiocb_flags; /* flags for this IOCB */
u64 xiocb_psize; /* size of parameter list */
union {
xiocb_buffer_t xiocb_buffer; /* buffer parameters */
xiocb_inpstat_t xiocb_inpstat; /* input status parameters */
xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */
xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */
xiocb_time_t xiocb_time; /* timer parameters */
xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */
xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */
xiocb_exitstat_t xiocb_exitstat; /* Exit Status */
} plist;
} cfe_xiocb_t;
/* buffer parameters */
struct xiocb_buffer xiocb_buffer;
#endif /* CFE_API_INT_H */
/* input status parameters */
struct xiocb_inpstat xiocb_inpstat;
/* environment function parameters */
struct xiocb_envbuf xiocb_envbuf;
/* CPU control parameters */
struct xiocb_cpuctl xiocb_cpuctl;
/* timer parameters */
struct xiocb_time xiocb_time;
/* memory arena info parameters */
struct xiocb_meminfo xiocb_meminfo;
/* firmware information */
struct xiocb_fwinfo xiocb_fwinfo;
/* Exit Status */
struct xiocb_exitstat xiocb_exitstat;
} plist;
};
#endif /* CFE_API_INT_H */

5
arch/mips/fw/lib/Makefile Normal file
View File

@ -0,0 +1,5 @@
#
# Makefile for generic prom monitor library routines under Linux.
#
lib-$(CONFIG_64BIT) += call_o32.o

97
arch/mips/fw/lib/call_o32.S Normal file
View File

@ -0,0 +1,97 @@
/*
* arch/mips/dec/prom/call_o32.S
*
* O32 interface for the 64 (or N32) ABI.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for static register */
#define O32_FRAMESZ (SZREG * O32_STATC)
/* Frame size on new stack */
#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC)
.text
/*
* O32 function call dispatcher, for interfacing 32-bit ROM routines.
*
* The standard 64 (N32) calling sequence is supported, with a0
* holding a function pointer, a1 a new stack pointer, a2-a7 -- its
* first six arguments and the stack -- remaining ones (up to O32_ARGC,
* including a2-a7). Static registers, gp and fp are preserved, v0 holds
* a result. This code relies on the called o32 function for sp and ra
* restoration and this dispatcher has to be placed in a KSEGx (or KUSEG)
* address space. Any pointers passed have to point to addresses within
* one of these spaces as well.
*/
NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ
REG_S ra,O32_FRAMESZ-1*SZREG(sp)
REG_S fp,O32_FRAMESZ-2*SZREG(sp)
REG_S gp,O32_FRAMESZ-3*SZREG(sp)
REG_S s7,O32_FRAMESZ-4*SZREG(sp)
REG_S s6,O32_FRAMESZ-5*SZREG(sp)
REG_S s5,O32_FRAMESZ-6*SZREG(sp)
REG_S s4,O32_FRAMESZ-7*SZREG(sp)
REG_S s3,O32_FRAMESZ-8*SZREG(sp)
REG_S s2,O32_FRAMESZ-9*SZREG(sp)
REG_S s1,O32_FRAMESZ-10*SZREG(sp)
REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0
REG_SUBU s0,a1,O32_FRAMESZ_NEW
REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0)
sll a0,a2,zero
sll a1,a3,zero
sll a2,a4,zero
sll a3,a5,zero
sw a6,0x10(s0)
sw a7,0x14(s0)
PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x18(s0)
li t2,O32_ARGC-6
1:
lw t3,(t0)
REG_ADDU t0,SZREG
sw t3,(t1)
REG_SUBU t2,1
REG_ADDU t1,4
bnez t2,1b
move sp,s0
jalr jp
REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp)
REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp)
REG_L s2,O32_FRAMESZ-9*SZREG(sp)
REG_L s3,O32_FRAMESZ-8*SZREG(sp)
REG_L s4,O32_FRAMESZ-7*SZREG(sp)
REG_L s5,O32_FRAMESZ-6*SZREG(sp)
REG_L s6,O32_FRAMESZ-5*SZREG(sp)
REG_L s7,O32_FRAMESZ-4*SZREG(sp)
REG_L gp,O32_FRAMESZ-3*SZREG(sp)
REG_L fp,O32_FRAMESZ-2*SZREG(sp)
REG_L ra,O32_FRAMESZ-1*SZREG(sp)
REG_ADDU sp,O32_FRAMESZ
jr ra
END(call_o32)

5
arch/mips/fw/sni/Makefile Normal file
View File

@ -0,0 +1,5 @@
#
# Makefile for the SNI prom monitor routines under Linux.
#
lib-$(CONFIG_SNIPROM) += sniprom.o

151
arch/mips/fw/sni/sniprom.c Normal file
View File

@ -0,0 +1,151 @@
/*
* Big Endian PROM code for SNI RM machines
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
* Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/console.h>
#include <asm/addrspace.h>
#include <asm/sni.h>
#include <asm/mipsprom.h>
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
/* special SNI prom calls */
/*
* This does not exist in all proms - SINIX compares
* the prom env variable "version" against "2.0008"
* or greater. If lesser it tries to probe interesting
* registers
*/
#define PROM_GET_MEMCONF 58
#define PROM_GET_HWCONF 61
#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
#define PROM_ENTRY(x) (PROM_VEC + (x))
#define ___prom_putchar ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR))
#define ___prom_getenv ((char *(*)(char *))PROM_ENTRY(PROM_GETENV))
#define ___prom_get_memconf ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF))
#define ___prom_get_hwconf ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF))
#ifdef CONFIG_64BIT
static u8 o32_stk[16384];
#define O32_STK &o32_stk[sizeof(o32_stk)]
#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
__asm__(#fun " = call_o32")
int __PROM_O32(__prom_putchar, (int *(*)(int), void *, int));
char *__PROM_O32(__prom_getenv, (char *(*)(char *), void *, char *));
void __PROM_O32(__prom_get_memconf, (void (*)(void *), void *, void *));
u32 __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *));
#define _prom_putchar(x) __prom_putchar(___prom_putchar, O32_STK, x)
#define _prom_getenv(x) __prom_getenv(___prom_getenv, O32_STK, x)
#define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x)
#define _prom_get_hwconf() __prom_get_hwconf(___prom_get_hwconf, O32_STK)
#else
#define _prom_putchar(x) ___prom_putchar(x)
#define _prom_getenv(x) ___prom_getenv(x)
#define _prom_get_memconf(x) ___prom_get_memconf(x)
#define _prom_get_hwconf(x) ___prom_get_hwconf(x)
#endif
void prom_putchar(char c)
{
_prom_putchar(c);
}
char *prom_getenv(char *s)
{
return _prom_getenv(s);
}
void *prom_get_hwconf(void)
{
u32 hwconf = _prom_get_hwconf();
if (hwconf == 0xffffffff)
return NULL;
return (void *)CKSEG1ADDR(hwconf);
}
void __init prom_free_prom_memory(void)
{
}
/*
* /proc/cpuinfo system type
*
*/
char *system_type = "Unknown";
const char *get_system_type(void)
{
return system_type;
}
static void __init sni_mem_init(void)
{
int i, memsize;
struct membank {
u32 size;
u32 base;
u32 size2;
u32 pad1;
u32 pad2;
} memconf[8];
int brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
/* MemSIZE from prom in 16MByte chunks */
memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
pr_debug("IDProm memsize: %u MByte\n", memsize);
/* get memory bank layout from prom */
_prom_get_memconf(&memconf);
pr_debug("prom_get_mem_conf memory configuration:\n");
for (i = 0; i < 8 && memconf[i].size; i++) {
if (brd_type == SNI_BRD_PCI_TOWER ||
brd_type == SNI_BRD_PCI_TOWER_CPLUS) {
if (memconf[i].base >= 0x20000000 &&
memconf[i].base < 0x30000000)
memconf[i].base -= 0x20000000;
}
pr_debug("Bank%d: %08x @ %08x\n", i,
memconf[i].size, memconf[i].base);
add_memory_region(memconf[i].base, memconf[i].size,
BOOT_MEM_RAM);
}
}
void __init prom_init(void)
{
int argc = fw_arg0;
u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
int i;
sni_mem_init();
/* copy prom cmdline parameters to kernel cmdline */
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
}

2
arch/mips/gt64120/wrppmc/setup.c
View File

@ -121,8 +121,6 @@ const char *get_system_type(void)
*/
void __init prom_init(void)
{
mips_machtype = MACH_WRPPMC;
add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);

7
arch/mips/jazz/setup.c
View File

@ -200,12 +200,19 @@ static struct platform_device jazz_cmos_pdev = {
.resource = jazz_cmos_rsrc
};
static struct platform_device pcspeaker_pdev = {
.name = "pcspkr",
.id = -1,
};
static int __init jazz_setup_devinit(void)
{
platform_device_register(&jazz_serial8250_device);
platform_device_register(&jazz_esp_pdev);
platform_device_register(&jazz_sonic_pdev);
platform_device_register(&jazz_cmos_pdev);
platform_device_register(&pcspeaker_pdev);
return 0;
}

4
arch/mips/jmr3927/rbhma3100/init.c
View File

@ -52,10 +52,6 @@ void __init prom_init(void)
puts("Warning: TX3927 TLB off\n");
#endif
#ifdef CONFIG_TOSHIBA_JMR3927
mips_machtype = MACH_TOSHIBA_JMR3927;
#endif
prom_init_cmdline();
add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
}

60
arch/mips/jmr3927/rbhma3100/setup.c
View File

@ -29,21 +29,17 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#ifdef CONFIG_SERIAL_TXX9
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#endif
#include <asm/addrspace.h>
#include <asm/txx9tmr.h>
#include <asm/reboot.h>
#include <asm/jmr3927/jmr3927.h>
@ -238,6 +234,8 @@ static void __init tx3927_setup(void)
tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
/* Disable PCI snoop */
tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
/* do reset on watchdog */
tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
#ifdef DO_WRITE_THROUGH
/* Enable PCI SNOOP - with write through only */
@ -388,3 +386,55 @@ static int __init jmr3927_rtc_init(void)
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}
device_initcall(jmr3927_rtc_init);
/* Watchdog support */
static int __init txx9_wdt_init(unsigned long base)
{
struct resource res = {
.start = base,
.end = base + 0x100 - 1,
.flags = IORESOURCE_MEM,
};
struct platform_device *dev =
platform_device_register_simple("txx9wdt", -1, &res, 1);
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}
static int __init jmr3927_wdt_init(void)
{
return txx9_wdt_init(TX3927_TMR_REG(2));
}
device_initcall(jmr3927_wdt_init);
/* Minimum CLK support */
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "imbus_clk"))
return (struct clk *)JMR3927_IMCLK;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return (unsigned long)clk;
}
EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

47
arch/mips/kernel/cpu-bugs64.c
View File

@ -18,6 +18,15 @@
#include <asm/mipsregs.h>
#include <asm/system.h>
static char bug64hit[] __initdata =
"reliable operation impossible!\n%s";
static char nowar[] __initdata =
"Please report to <linux-mips@linux-mips.org>.";
static char r4kwar[] __initdata =
"Enable CPU_R4000_WORKAROUNDS to rectify.";
static char daddiwar[] __initdata =
"Enable CPU_DADDI_WORKAROUNDS to rectify.";
static inline void align_mod(const int align, const int mod)
{
asm volatile(
@ -155,13 +164,7 @@ static inline void check_mult_sh(void)
}
printk("no.\n");
panic("Reliable operation impossible!\n"
#ifndef CONFIG_CPU_R4000
"Configure for R4000 to enable the workaround."
#else
"Please report to <linux-mips@linux-mips.org>."
#endif
);
panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
}
static volatile int daddi_ov __initdata = 0;
@ -233,15 +236,11 @@ static inline void check_daddi(void)
}
printk("no.\n");
panic("Reliable operation impossible!\n"
#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
"Configure for R4000 or R4400 to enable the workaround."
#else
"Please report to <linux-mips@linux-mips.org>."
#endif
);
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
}
int daddiu_bug __initdata = -1;
static inline void check_daddiu(void)
{
long v, w, tmp;
@ -281,7 +280,9 @@ static inline void check_daddiu(void)
: "=&r" (v), "=&r" (w), "=&r" (tmp)
: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
if (v == w) {
daddiu_bug = v != w;
if (!daddiu_bug) {
printk("no.\n");
return;
}
@ -303,18 +304,16 @@ static inline void check_daddiu(void)
}
printk("no.\n");
panic("Reliable operation impossible!\n"
#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
"Configure for R4000 or R4400 to enable the workaround."
#else
"Please report to <linux-mips@linux-mips.org>."
#endif
);
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
}
void __init check_bugs64_early(void)
{
check_mult_sh();
check_daddiu();
}
void __init check_bugs64(void)
{
check_mult_sh();
check_daddi();
check_daddiu();
}

9
arch/mips/kernel/cpu-probe.c
View File

@ -188,6 +188,8 @@ static inline void check_wait(void)
case CPU_AU1500:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
if (allow_au1k_wait)
cpu_wait = au1k_wait;
break;
@ -733,6 +735,11 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
break;
case 4:
c->cputype = CPU_AU1200;
if (2 == (c->processor_id & 0xff))
c->cputype = CPU_AU1250;
break;
case 5:
c->cputype = CPU_AU1210;
break;
default:
panic("Unknown Au Core!");
@ -858,6 +865,8 @@ static __init const char *cpu_to_name(struct cpuinfo_mips *c)
case CPU_AU1100: name = "Au1100"; break;
case CPU_AU1550: name = "Au1550"; break;
case CPU_AU1200: name = "Au1200"; break;
case CPU_AU1210: name = "Au1210"; break;
case CPU_AU1250: name = "Au1250"; break;
case CPU_4KEC: name = "MIPS 4KEc"; break;
case CPU_4KSC: name = "MIPS 4KSc"; break;
case CPU_VR41XX: name = "NEC Vr41xx"; break;

8
arch/mips/kernel/genex.S
View File

@ -6,7 +6,7 @@
* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
* Copyright (C) 2002, 2007 Maciej W. Rozycki
*/
#include <linux/init.h>
@ -471,7 +471,13 @@ NESTED(nmi_handler, PT_SIZE, sp)
jr k0
rfe
#else
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
LONG_ADDIU k0, 4 /* stall on $k0 */
#else
.set at=v1
LONG_ADDIU k0, 4
.set noat
#endif
MTC0 k0, CP0_EPC
/* I hope three instructions between MTC0 and ERET are enough... */
ori k1, _THREAD_MASK

3
arch/mips/kernel/kspd.c
View File

@ -161,8 +161,7 @@ static unsigned int translate_open_flags(int flags)
int i;
unsigned int ret = 0;
for (i = 0; i < (sizeof(open_flags_table) / sizeof(struct apsp_table));
i++) {
for (i = 0; i < ARRAY_SIZE(open_flags_table); i++) {
if( (flags & open_flags_table[i].sp) ) {
ret |= open_flags_table[i].ap;
}

30
arch/mips/kernel/linux32.c
View File

@ -174,36 +174,16 @@ struct rlimit32 {
int rlim_max;
};
#ifdef __MIPSEB__
asmlinkage long sys32_truncate64(const char __user * path, unsigned long __dummy,
int length_hi, int length_lo)
#endif
#ifdef __MIPSEL__
asmlinkage long sys32_truncate64(const char __user * path, unsigned long __dummy,
int length_lo, int length_hi)
#endif
asmlinkage long sys32_truncate64(const char __user * path,
unsigned long __dummy, int a2, int a3)
{
loff_t length;
length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo;
return sys_truncate(path, length);
return sys_truncate(path, merge_64(a2, a3));
}
#ifdef __MIPSEB__
asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy,
int length_hi, int length_lo)
#endif
#ifdef __MIPSEL__
asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy,
int length_lo, int length_hi)
#endif
int a2, int a3)
{
loff_t length;
length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo;
return sys_ftruncate(fd, length);
return sys_ftruncate(fd, merge_64(a2, a3));
}
static inline long

1
arch/mips/kernel/mips-mt.c
View File

@ -17,7 +17,6 @@
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/mipsmtregs.h>
#include <asm/r4kcache.h>
#include <asm/cacheflush.h>

28
arch/mips/kernel/pcspeaker.c
View File

@ -1,28 +0,0 @@
/*
* Copyright (C) 2006 IBM Corporation
*
* Implements device information for i8253 timer chip
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation
*/
#include <linux/platform_device.h>
static __init int add_pcspkr(void)
{
struct platform_device *pd;
int ret;
pd = platform_device_alloc("pcspkr", -1);
if (!pd)
return -ENOMEM;
ret = platform_device_add(pd);
if (ret)
platform_device_put(pd);
return ret;
}
device_initcall(add_pcspkr);

3
arch/mips/kernel/proc.c
View File

@ -62,6 +62,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
);
seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets);
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");
@ -89,7 +90,7 @@ static void c_stop(struct seq_file *m, void *v)
{
}
struct seq_operations cpuinfo_op = {
const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,

1
arch/mips/kernel/rtlx.c
View File

@ -40,7 +40,6 @@
#include <asm/atomic.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/mips_mt.h>
#include <asm/system.h>
#include <asm/vpe.h>
#include <asm/rtlx.h>

7
arch/mips/kernel/setup.c
View File

@ -8,7 +8,7 @@
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle
* Copyright (C) 1996 Stoned Elipot
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2000 2001, 2002 Maciej W. Rozycki
* Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki
*/
#include <linux/init.h>
#include <linux/ioport.h>
@ -24,10 +24,12 @@
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/bugs.h>
#include <asm/cache.h>
#include <asm/cpu.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp-ops.h>
#include <asm/system.h>
struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;
@ -561,6 +563,7 @@ void __init setup_arch(char **cmdline_p)
}
#endif
cpu_report();
check_bugs_early();
#if defined(CONFIG_VT)
#if defined(CONFIG_VGA_CONSOLE)
@ -573,9 +576,7 @@ void __init setup_arch(char **cmdline_p)
arch_mem_init(cmdline_p);
resource_init();
#ifdef CONFIG_SMP
plat_smp_setup();
#endif
}
static int __init fpu_disable(char *s)

207
arch/mips/kernel/smp-mt.c
View File

@ -22,6 +22,7 @@
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/smp.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
@ -30,7 +31,6 @@
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
@ -215,68 +215,67 @@ static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
write_tc_c0_tchalt(TCHALT_H);
}
/*
* Common setup before any secondaries are started
* Make sure all CPU's are in a sensible state before we boot any of the
* secondarys
*/
void __init plat_smp_setup(void)
static void vsmp_send_ipi_single(int cpu, unsigned int action)
{
unsigned int mvpconf0, ntc, tc, ncpu = 0;
int i;
unsigned long flags;
int vpflags;
local_irq_save(flags);
vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
switch (action) {
case SMP_CALL_FUNCTION:
i = C_SW1;
break;
case SMP_RESCHEDULE_YOURSELF:
default:
i = C_SW0;
break;
}
/* 1:1 mapping of vpe and tc... */
settc(cpu);
write_vpe_c0_cause(read_vpe_c0_cause() | i);
evpe(vpflags);
local_irq_restore(flags);
}
static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action)
{
unsigned int i;
for_each_cpu_mask(i, mask)
vsmp_send_ipi_single(i, action);
}
static void __cpuinit vsmp_init_secondary(void)
{
/* Enable per-cpu interrupts */
/* This is Malta specific: IPI,performance and timer inetrrupts */
write_c0_status((read_c0_status() & ~ST0_IM ) |
(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
}
static void __cpuinit vsmp_smp_finish(void)
{
write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
if (cpu_has_fpu)
cpu_set(0, mt_fpu_cpumask);
cpu_set(smp_processor_id(), mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
if (!cpu_has_mipsmt)
return;
/* disable MT so we can configure */
dvpe();
dmt();
/* Put MVPE's into 'configuration state' */
set_c0_mvpcontrol(MVPCONTROL_VPC);
mvpconf0 = read_c0_mvpconf0();
ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
/* we'll always have more TC's than VPE's, so loop setting everything
to a sensible state */
for (tc = 0; tc <= ntc; tc++) {
settc(tc);
smp_tc_init(tc, mvpconf0);
ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
}
/* Release config state */
clear_c0_mvpcontrol(MVPCONTROL_VPC);
/* We'll wait until starting the secondaries before starting MVPE */
printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
local_irq_enable();
}
void __init plat_prepare_cpus(unsigned int max_cpus)
static void vsmp_cpus_done(void)
{
mips_mt_set_cpuoptions();
/* set up ipi interrupts */
if (cpu_has_vint) {
set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
}
cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
setup_irq(cpu_ipi_resched_irq, &irq_resched);
setup_irq(cpu_ipi_call_irq, &irq_call);
set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
}
/*
@ -287,7 +286,7 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
* (unsigned long)idle->thread_info the gp
* assumes a 1:1 mapping of TC => VPE
*/
void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
{
struct thread_info *gp = task_thread_info(idle);
dvpe();
@ -321,57 +320,81 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
evpe(EVPE_ENABLE);
}
void __cpuinit prom_init_secondary(void)
/*
* Common setup before any secondaries are started
* Make sure all CPU's are in a sensible state before we boot any of the
* secondarys
*/
static void __init vsmp_smp_setup(void)
{
/* Enable per-cpu interrupts */
/* This is Malta specific: IPI,performance and timer inetrrupts */
write_c0_status((read_c0_status() & ~ST0_IM ) |
(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
}
void __cpuinit prom_smp_finish(void)
{
write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
unsigned int mvpconf0, ntc, tc, ncpu = 0;
unsigned int nvpe;
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
if (cpu_has_fpu)
cpu_set(smp_processor_id(), mt_fpu_cpumask);
cpu_set(0, mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
if (!cpu_has_mipsmt)
return;
local_irq_enable();
}
/* disable MT so we can configure */
dvpe();
dmt();
void prom_cpus_done(void)
{
}
/* Put MVPE's into 'configuration state' */
set_c0_mvpcontrol(MVPCONTROL_VPC);
void core_send_ipi(int cpu, unsigned int action)
{
int i;
unsigned long flags;
int vpflags;
mvpconf0 = read_c0_mvpconf0();
ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
local_irq_save(flags);
nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
smp_num_siblings = nvpe;
vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
/* we'll always have more TC's than VPE's, so loop setting everything
to a sensible state */
for (tc = 0; tc <= ntc; tc++) {
settc(tc);
switch (action) {
case SMP_CALL_FUNCTION:
i = C_SW1;
break;
case SMP_RESCHEDULE_YOURSELF:
default:
i = C_SW0;
break;
smp_tc_init(tc, mvpconf0);
ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
}
/* 1:1 mapping of vpe and tc... */
settc(cpu);
write_vpe_c0_cause(read_vpe_c0_cause() | i);
evpe(vpflags);
/* Release config state */
clear_c0_mvpcontrol(MVPCONTROL_VPC);
local_irq_restore(flags);
/* We'll wait until starting the secondaries before starting MVPE */
printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
}
static void __init vsmp_prepare_cpus(unsigned int max_cpus)
{
mips_mt_set_cpuoptions();
/* set up ipi interrupts */
if (cpu_has_vint) {
set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
}
cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
setup_irq(cpu_ipi_resched_irq, &irq_resched);
setup_irq(cpu_ipi_call_irq, &irq_call);
set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
}
struct plat_smp_ops vsmp_smp_ops = {
.send_ipi_single = vsmp_send_ipi_single,
.send_ipi_mask = vsmp_send_ipi_mask,
.init_secondary = vsmp_init_secondary,
.smp_finish = vsmp_smp_finish,
.cpus_done = vsmp_cpus_done,
.boot_secondary = vsmp_boot_secondary,
.smp_setup = vsmp_smp_setup,
.prepare_cpus = vsmp_prepare_cpus,
};

53
arch/mips/kernel/smp.c
View File

@ -37,7 +37,6 @@
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/time.h>
#ifdef CONFIG_MIPS_MT_SMTC
@ -56,6 +55,44 @@ EXPORT_SYMBOL(cpu_online_map);
extern void __init calibrate_delay(void);
extern void cpu_idle(void);
/* Number of TCs (or siblings in Intel speak) per CPU core */
int smp_num_siblings = 1;
EXPORT_SYMBOL(smp_num_siblings);
/* representing the TCs (or siblings in Intel speak) of each logical CPU */
cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_sibling_map);
/* representing cpus for which sibling maps can be computed */
static cpumask_t cpu_sibling_setup_map;
static inline void set_cpu_sibling_map(int cpu)
{
int i;
cpu_set(cpu, cpu_sibling_setup_map);
if (smp_num_siblings > 1) {
for_each_cpu_mask(i, cpu_sibling_setup_map) {
if (cpu_data[cpu].core == cpu_data[i].core) {
cpu_set(i, cpu_sibling_map[cpu]);
cpu_set(cpu, cpu_sibling_map[i]);
}
}
} else
cpu_set(cpu, cpu_sibling_map[cpu]);
}
struct plat_smp_ops *mp_ops;
__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
{
if (ops)
printk(KERN_WARNING "Overriding previous set SMP ops\n");
mp_ops = ops;
}
/*
* First C code run on the secondary CPUs after being started up by
* the master.
@ -72,7 +109,7 @@ asmlinkage __cpuinit void start_secondary(void)
cpu_report();
per_cpu_trap_init();
mips_clockevent_init();
prom_init_secondary();
mp_ops->init_secondary();
/*
* XXX parity protection should be folded in here when it's converted
@ -84,7 +121,8 @@ asmlinkage __cpuinit void start_secondary(void)
cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
prom_smp_finish();
mp_ops->smp_finish();
set_cpu_sibling_map(cpu);
cpu_set(cpu, cpu_callin_map);
@ -155,7 +193,7 @@ int smp_call_function_mask(cpumask_t mask, void (*func) (void *info),
smp_mb();
/* Send a message to all other CPUs and wait for them to respond */
core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
/* Wait for response */
/* FIXME: lock-up detection, backtrace on lock-up */
@ -249,7 +287,7 @@ void smp_send_stop(void)
void __init smp_cpus_done(unsigned int max_cpus)
{
prom_cpus_done();
mp_ops->cpus_done();
}
/* called from main before smp_init() */
@ -257,7 +295,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
{
init_new_context(current, &init_mm);
current_thread_info()->cpu = 0;
plat_prepare_cpus(max_cpus);
mp_ops->prepare_cpus(max_cpus);
set_cpu_sibling_map(0);
#ifndef CONFIG_HOTPLUG_CPU
cpu_present_map = cpu_possible_map;
#endif
@ -295,7 +334,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
if (IS_ERR(idle))
panic(KERN_ERR "Fork failed for CPU %d", cpu);
prom_boot_secondary(cpu, idle);
mp_ops->boot_secondary(cpu, idle);
/*
* Trust is futile. We should really have timeouts ...

1
arch/mips/kernel/smtc-proc.c
View File

@ -14,7 +14,6 @@
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/mipsregs.h>
#include <asm/cacheflush.h>
#include <linux/proc_fs.h>

1
arch/mips/kernel/smtc.c
View File

@ -16,7 +16,6 @@
#include <asm/hazards.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/mipsregs.h>
#include <asm/cacheflush.h>
#include <asm/time.h>

2
arch/mips/kernel/time.c
View File

@ -50,8 +50,6 @@ int update_persistent_clock(struct timespec now)
return rtc_mips_set_mmss(now.tv_sec);
}
int (*mips_timer_state)(void);
int null_perf_irq(void)
{
return 0;

1
arch/mips/kernel/vpe.c
View File

@ -53,7 +53,6 @@
#include <asm/system.h>
#include <asm/vpe.h>
#include <asm/kspd.h>
#include <asm/mips_mt.h>
typedef void *vpe_handle;

2
arch/mips/lasat/picvue.c
View File

@ -22,8 +22,6 @@
struct pvc_defs *picvue;
DECLARE_MUTEX(pvc_sem);
static void pvc_reg_write(u32 val)
{
*picvue->reg = val;

3
arch/mips/lasat/picvue.h
View File

@ -4,8 +4,6 @@
* Brian Murphy <brian.murphy@eicon.com>
*
*/
#include <asm/semaphore.h>
struct pvc_defs {
volatile u32 *reg;
u32 data_shift;
@ -45,4 +43,3 @@ void pvc_move(u8 cmd);
void pvc_clear(void);
void pvc_home(void);
extern struct semaphore pvc_sem;

18
arch/mips/lasat/picvue_proc.c
View File

@ -13,9 +13,11 @@
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/mutex.h>
#include "picvue.h"
static DEFINE_MUTEX(pvc_mutex);
static char pvc_lines[PVC_NLINES][PVC_LINELEN+1];
static int pvc_linedata[PVC_NLINES];
static struct proc_dir_entry *pvc_display_dir;
@ -48,9 +50,9 @@ static int pvc_proc_read_line(char *page, char **start,
return 0;
}
down(&pvc_sem);
mutex_lock(&pvc_mutex);
page += sprintf(page, "%s\n", pvc_lines[lineno]);
up(&pvc_sem);
mutex_unlock(&pvc_mutex);
return page - origpage;
}
@ -73,10 +75,10 @@ static int pvc_proc_write_line(struct file *file, const char *buffer,
if (buffer[count-1] == '\n')
count--;
down(&pvc_sem);
mutex_lock(&pvc_mutex);
strncpy(pvc_lines[lineno], buffer, count);
pvc_lines[lineno][count] = '\0';
up(&pvc_sem);
mutex_unlock(&pvc_mutex);
tasklet_schedule(&pvc_display_tasklet);
@ -89,7 +91,7 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
int origcount = count;
int cmd = simple_strtol(buffer, NULL, 10);
down(&pvc_sem);
mutex_lock(&pvc_mutex);
if (scroll_interval != 0)
del_timer(&timer);
@ -106,7 +108,7 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
}
add_timer(&timer);
}
up(&pvc_sem);
mutex_unlock(&pvc_mutex);
return origcount;
}
@ -117,9 +119,9 @@ static int pvc_proc_read_scroll(char *page, char **start,
{
char *origpage = page;
down(&pvc_sem);
mutex_lock(&pvc_mutex);
page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
up(&pvc_sem);
mutex_unlock(&pvc_mutex);
return page - origpage;
}

3
arch/mips/lemote/lm2e/pci.c
View File

@ -81,9 +81,6 @@ static void __init ict_pcimap(void)
static int __init pcibios_init(void)
{
extern int pci_probe_only;
pci_probe_only = 0;
ict_pcimap();
register_pci_controller(&loongson2e_pci_controller);

2
arch/mips/lemote/lm2e/prom.c
View File

@ -57,8 +57,6 @@ void __init prom_init(void)
arg = (int *)fw_arg1;
env = (int *)fw_arg2;
mips_machtype = MACH_LEMOTE_FULONG;
prom_init_cmdline();
if ((strstr(arcs_cmdline, "console=")) == NULL)

275
arch/mips/lib/csum_partial.S
View File

@ -7,6 +7,7 @@
*
* Copyright (C) 1998, 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki
*/
#include <linux/errno.h>
#include <asm/asm.h>
@ -52,9 +53,12 @@
#define UNIT(unit) ((unit)*NBYTES)
#define ADDC(sum,reg) \
.set push; \
.set noat; \
ADD sum, reg; \
sltu v1, sum, reg; \
ADD sum, v1
ADD sum, v1; \
.set pop
#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
LOAD _t0, (offset + UNIT(0))(src); \
@ -92,13 +96,13 @@ LEAF(csum_partial)
move t7, zero
sltiu t8, a1, 0x8
bnez t8, small_csumcpy /* < 8 bytes to copy */
bnez t8, .Lsmall_csumcpy /* < 8 bytes to copy */
move t2, a1
andi t7, src, 0x1 /* odd buffer? */
hword_align:
beqz t7, word_align
.Lhword_align:
beqz t7, .Lword_align
andi t8, src, 0x2
lbu t0, (src)
@ -110,8 +114,8 @@ hword_align:
PTR_ADDU src, src, 0x1
andi t8, src, 0x2
word_align:
beqz t8, dword_align
.Lword_align:
beqz t8, .Ldword_align
sltiu t8, a1, 56
lhu t0, (src)
@ -120,12 +124,12 @@ word_align:
sltiu t8, a1, 56
PTR_ADDU src, src, 0x2
dword_align:
bnez t8, do_end_words
.Ldword_align:
bnez t8, .Ldo_end_words
move t8, a1
andi t8, src, 0x4
beqz t8, qword_align
beqz t8, .Lqword_align
andi t8, src, 0x8
lw t0, 0x00(src)
@ -134,8 +138,8 @@ dword_align:
PTR_ADDU src, src, 0x4
andi t8, src, 0x8
qword_align:
beqz t8, oword_align
.Lqword_align:
beqz t8, .Loword_align
andi t8, src, 0x10
#ifdef USE_DOUBLE
@ -152,8 +156,8 @@ qword_align:
PTR_ADDU src, src, 0x8
andi t8, src, 0x10
oword_align:
beqz t8, begin_movement
.Loword_align:
beqz t8, .Lbegin_movement
LONG_SRL t8, a1, 0x7
#ifdef USE_DOUBLE
@ -168,51 +172,55 @@ oword_align:
PTR_ADDU src, src, 0x10
LONG_SRL t8, a1, 0x7
begin_movement:
.Lbegin_movement:
beqz t8, 1f
andi t2, a1, 0x40
move_128bytes:
.Lmove_128bytes:
CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
LONG_SUBU t8, t8, 0x01
bnez t8, move_128bytes
PTR_ADDU src, src, 0x80
.set reorder /* DADDI_WAR */
PTR_ADDU src, src, 0x80
bnez t8, .Lmove_128bytes
.set noreorder
1:
beqz t2, 1f
andi t2, a1, 0x20
move_64bytes:
.Lmove_64bytes:
CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
PTR_ADDU src, src, 0x40
1:
beqz t2, do_end_words
beqz t2, .Ldo_end_words
andi t8, a1, 0x1c
move_32bytes:
.Lmove_32bytes:
CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
andi t8, a1, 0x1c
PTR_ADDU src, src, 0x20
do_end_words:
beqz t8, small_csumcpy
.Ldo_end_words:
beqz t8, .Lsmall_csumcpy
andi t2, a1, 0x3
LONG_SRL t8, t8, 0x2
end_words:
.Lend_words:
lw t0, (src)
LONG_SUBU t8, t8, 0x1
ADDC(sum, t0)
bnez t8, end_words
PTR_ADDU src, src, 0x4
.set reorder /* DADDI_WAR */
PTR_ADDU src, src, 0x4
bnez t8, .Lend_words
.set noreorder
/* unknown src alignment and < 8 bytes to go */
small_csumcpy:
.Lsmall_csumcpy:
move a1, t2
andi t0, a1, 4
@ -246,6 +254,8 @@ small_csumcpy:
1: ADDC(sum, t1)
/* fold checksum */
.set push
.set noat
#ifdef USE_DOUBLE
dsll32 v1, sum, 0
daddu sum, v1
@ -266,6 +276,7 @@ small_csumcpy:
srl sum, sum, 8
or sum, v1
andi sum, 0xffff
.set pop
1:
.set reorder
/* Add the passed partial csum. */
@ -373,7 +384,11 @@ small_csumcpy:
#define ADDRMASK (NBYTES-1)
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
.set noat
#else
.set at=v1
#endif
LEAF(__csum_partial_copy_user)
PTR_ADDU AT, src, len /* See (1) above. */
@ -398,95 +413,101 @@ FEXPORT(csum_partial_copy_nocheck)
*/
sltu t2, len, NBYTES
and t1, dst, ADDRMASK
bnez t2, copy_bytes_checklen
bnez t2, .Lcopy_bytes_checklen
and t0, src, ADDRMASK
andi odd, dst, 0x1 /* odd buffer? */
bnez t1, dst_unaligned
bnez t1, .Ldst_unaligned
nop
bnez t0, src_unaligned_dst_aligned
bnez t0, .Lsrc_unaligned_dst_aligned
/*
* use delay slot for fall-through
* src and dst are aligned; need to compute rem
*/
both_aligned:
.Lboth_aligned:
SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
beqz t0, cleanup_both_aligned # len < 8*NBYTES
beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
nop
SUB len, 8*NBYTES # subtract here for bgez loop
.align 4
1:
EXC( LOAD t0, UNIT(0)(src), l_exc)
EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
EXC( LOAD t4, UNIT(4)(src), l_exc_copy)
EXC( LOAD t5, UNIT(5)(src), l_exc_copy)
EXC( LOAD t6, UNIT(6)(src), l_exc_copy)
EXC( LOAD t7, UNIT(7)(src), l_exc_copy)
EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
EXC( LOAD t5, UNIT(5)(src), .Ll_exc_copy)
EXC( LOAD t6, UNIT(6)(src), .Ll_exc_copy)
EXC( LOAD t7, UNIT(7)(src), .Ll_exc_copy)
SUB len, len, 8*NBYTES
ADD src, src, 8*NBYTES
EXC( STORE t0, UNIT(0)(dst), s_exc)
EXC( STORE t0, UNIT(0)(dst), .Ls_exc)
ADDC(sum, t0)
EXC( STORE t1, UNIT(1)(dst), s_exc)
EXC( STORE t1, UNIT(1)(dst), .Ls_exc)
ADDC(sum, t1)
EXC( STORE t2, UNIT(2)(dst), s_exc)
EXC( STORE t2, UNIT(2)(dst), .Ls_exc)
ADDC(sum, t2)
EXC( STORE t3, UNIT(3)(dst), s_exc)
EXC( STORE t3, UNIT(3)(dst), .Ls_exc)
ADDC(sum, t3)
EXC( STORE t4, UNIT(4)(dst), s_exc)
EXC( STORE t4, UNIT(4)(dst), .Ls_exc)
ADDC(sum, t4)
EXC( STORE t5, UNIT(5)(dst), s_exc)
EXC( STORE t5, UNIT(5)(dst), .Ls_exc)
ADDC(sum, t5)
EXC( STORE t6, UNIT(6)(dst), s_exc)
EXC( STORE t6, UNIT(6)(dst), .Ls_exc)
ADDC(sum, t6)
EXC( STORE t7, UNIT(7)(dst), s_exc)
EXC( STORE t7, UNIT(7)(dst), .Ls_exc)
ADDC(sum, t7)
.set reorder /* DADDI_WAR */
ADD dst, dst, 8*NBYTES
bgez len, 1b
ADD dst, dst, 8*NBYTES
.set noreorder
ADD len, 8*NBYTES # revert len (see above)
/*
* len == the number of bytes left to copy < 8*NBYTES
*/
cleanup_both_aligned:
.Lcleanup_both_aligned:
#define rem t7
beqz len, done
beqz len, .Ldone
sltu t0, len, 4*NBYTES
bnez t0, less_than_4units
bnez t0, .Lless_than_4units
and rem, len, (NBYTES-1) # rem = len % NBYTES
/*
* len >= 4*NBYTES
*/
EXC( LOAD t0, UNIT(0)(src), l_exc)
EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
SUB len, len, 4*NBYTES
ADD src, src, 4*NBYTES
EXC( STORE t0, UNIT(0)(dst), s_exc)
EXC( STORE t0, UNIT(0)(dst), .Ls_exc)
ADDC(sum, t0)
EXC( STORE t1, UNIT(1)(dst), s_exc)
EXC( STORE t1, UNIT(1)(dst), .Ls_exc)
ADDC(sum, t1)
EXC( STORE t2, UNIT(2)(dst), s_exc)
EXC( STORE t2, UNIT(2)(dst), .Ls_exc)
ADDC(sum, t2)
EXC( STORE t3, UNIT(3)(dst), s_exc)
EXC( STORE t3, UNIT(3)(dst), .Ls_exc)
ADDC(sum, t3)
beqz len, done
ADD dst, dst, 4*NBYTES
less_than_4units:
.set reorder /* DADDI_WAR */
ADD dst, dst, 4*NBYTES
beqz len, .Ldone
.set noreorder
.Lless_than_4units:
/*
* rem = len % NBYTES
*/
beq rem, len, copy_bytes
beq rem, len, .Lcopy_bytes
nop
1:
EXC( LOAD t0, 0(src), l_exc)
EXC( LOAD t0, 0(src), .Ll_exc)
ADD src, src, NBYTES
SUB len, len, NBYTES
EXC( STORE t0, 0(dst), s_exc)
EXC( STORE t0, 0(dst), .Ls_exc)
ADDC(sum, t0)
.set reorder /* DADDI_WAR */
ADD dst, dst, NBYTES
bne rem, len, 1b
ADD dst, dst, NBYTES
.set noreorder
/*
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
@ -500,20 +521,20 @@ EXC( STORE t0, 0(dst), s_exc)
* more instruction-level parallelism.
*/
#define bits t2
beqz len, done
beqz len, .Ldone
ADD t1, dst, len # t1 is just past last byte of dst
li bits, 8*NBYTES
SLL rem, len, 3 # rem = number of bits to keep
EXC( LOAD t0, 0(src), l_exc)
EXC( LOAD t0, 0(src), .Ll_exc)
SUB bits, bits, rem # bits = number of bits to discard
SHIFT_DISCARD t0, t0, bits
EXC( STREST t0, -1(t1), s_exc)
EXC( STREST t0, -1(t1), .Ls_exc)
SHIFT_DISCARD_REVERT t0, t0, bits
.set reorder
ADDC(sum, t0)
b done
b .Ldone
.set noreorder
dst_unaligned:
.Ldst_unaligned:
/*
* dst is unaligned
* t0 = src & ADDRMASK
@ -524,25 +545,25 @@ dst_unaligned:
* Set match = (src and dst have same alignment)
*/
#define match rem
EXC( LDFIRST t3, FIRST(0)(src), l_exc)
EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
ADD t2, zero, NBYTES
EXC( LDREST t3, REST(0)(src), l_exc_copy)
EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
SUB t2, t2, t1 # t2 = number of bytes copied
xor match, t0, t1
EXC( STFIRST t3, FIRST(0)(dst), s_exc)
EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc)
SLL t4, t1, 3 # t4 = number of bits to discard
SHIFT_DISCARD t3, t3, t4
/* no SHIFT_DISCARD_REVERT to handle odd buffer properly */
ADDC(sum, t3)
beq len, t2, done
beq len, t2, .Ldone
SUB len, len, t2
ADD dst, dst, t2
beqz match, both_aligned
beqz match, .Lboth_aligned
ADD src, src, t2
src_unaligned_dst_aligned:
.Lsrc_unaligned_dst_aligned:
SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
beqz t0, cleanup_src_unaligned
beqz t0, .Lcleanup_src_unaligned
and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
1:
/*
@ -551,49 +572,53 @@ src_unaligned_dst_aligned:
* It's OK to load FIRST(N+1) before REST(N) because the two addresses
* are to the same unit (unless src is aligned, but it's not).
*/
EXC( LDFIRST t0, FIRST(0)(src), l_exc)
EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
SUB len, len, 4*NBYTES
EXC( LDREST t0, REST(0)(src), l_exc_copy)
EXC( LDREST t1, REST(1)(src), l_exc_copy)
EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
EXC( LDREST t2, REST(2)(src), l_exc_copy)
EXC( LDREST t3, REST(3)(src), l_exc_copy)
EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
ADD src, src, 4*NBYTES
#ifdef CONFIG_CPU_SB1
nop # improves slotting
#endif
EXC( STORE t0, UNIT(0)(dst), s_exc)
EXC( STORE t0, UNIT(0)(dst), .Ls_exc)
ADDC(sum, t0)
EXC( STORE t1, UNIT(1)(dst), s_exc)
EXC( STORE t1, UNIT(1)(dst), .Ls_exc)
ADDC(sum, t1)
EXC( STORE t2, UNIT(2)(dst), s_exc)
EXC( STORE t2, UNIT(2)(dst), .Ls_exc)
ADDC(sum, t2)
EXC( STORE t3, UNIT(3)(dst), s_exc)
EXC( STORE t3, UNIT(3)(dst), .Ls_exc)
ADDC(sum, t3)
.set reorder /* DADDI_WAR */
ADD dst, dst, 4*NBYTES
bne len, rem, 1b
ADD dst, dst, 4*NBYTES
.set noreorder
cleanup_src_unaligned:
beqz len, done
.Lcleanup_src_unaligned:
beqz len, .Ldone
and rem, len, NBYTES-1 # rem = len % NBYTES
beq rem, len, copy_bytes
beq rem, len, .Lcopy_bytes
nop
1:
EXC( LDFIRST t0, FIRST(0)(src), l_exc)
EXC( LDREST t0, REST(0)(src), l_exc_copy)
EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
ADD src, src, NBYTES
SUB len, len, NBYTES
EXC( STORE t0, 0(dst), s_exc)
EXC( STORE t0, 0(dst), .Ls_exc)
ADDC(sum, t0)
.set reorder /* DADDI_WAR */
ADD dst, dst, NBYTES
bne len, rem, 1b
ADD dst, dst, NBYTES
.set noreorder
copy_bytes_checklen:
beqz len, done
.Lcopy_bytes_checklen:
beqz len, .Ldone
nop
copy_bytes:
.Lcopy_bytes:
/* 0 < len < NBYTES */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define SHIFT_START 0
@ -604,14 +629,14 @@ copy_bytes:
#endif
move t2, zero # partial word
li t3, SHIFT_START # shift
/* use l_exc_copy here to return correct sum on fault */
/* use .Ll_exc_copy here to return correct sum on fault */
#define COPY_BYTE(N) \
EXC( lbu t0, N(src), l_exc_copy); \
EXC( lbu t0, N(src), .Ll_exc_copy); \
SUB len, len, 1; \
EXC( sb t0, N(dst), s_exc); \
EXC( sb t0, N(dst), .Ls_exc); \
SLLV t0, t0, t3; \
addu t3, SHIFT_INC; \
beqz len, copy_bytes_done; \
beqz len, .Lcopy_bytes_done; \
or t2, t0
COPY_BYTE(0)
@ -622,15 +647,17 @@ EXC( sb t0, N(dst), s_exc); \
COPY_BYTE(4)
COPY_BYTE(5)
#endif
EXC( lbu t0, NBYTES-2(src), l_exc_copy)
EXC( lbu t0, NBYTES-2(src), .Ll_exc_copy)
SUB len, len, 1
EXC( sb t0, NBYTES-2(dst), s_exc)
EXC( sb t0, NBYTES-2(dst), .Ls_exc)
SLLV t0, t0, t3
or t2, t0
copy_bytes_done:
.Lcopy_bytes_done:
ADDC(sum, t2)
done:
.Ldone:
/* fold checksum */
.set push
.set noat
#ifdef USE_DOUBLE
dsll32 v1, sum, 0
daddu sum, v1
@ -651,13 +678,14 @@ done:
srl sum, sum, 8
or sum, v1
andi sum, 0xffff
.set pop
1:
.set reorder
ADDC(sum, psum)
jr ra
.set noreorder
l_exc_copy:
.Ll_exc_copy:
/*
* Copy bytes from src until faulting load address (or until a
* lb faults)
@ -672,15 +700,17 @@ l_exc_copy:
li t2, SHIFT_START
LOAD t0, THREAD_BUADDR(t0)
1:
EXC( lbu t1, 0(src), l_exc)
EXC( lbu t1, 0(src), .Ll_exc)
ADD src, src, 1
sb t1, 0(dst) # can't fault -- we're copy_from_user
SLLV t1, t1, t2
addu t2, SHIFT_INC
ADDC(sum, t1)
.set reorder /* DADDI_WAR */
ADD dst, dst, 1
bne src, t0, 1b
ADD dst, dst, 1
l_exc:
.set noreorder
.Ll_exc:
LOAD t0, TI_TASK($28)
nop
LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
@ -697,19 +727,30 @@ l_exc:
* Clear len bytes starting at dst. Can't call __bzero because it
* might modify len. An inefficient loop for these rare times...
*/
beqz len, done
SUB src, len, 1
.set reorder /* DADDI_WAR */
SUB src, len, 1
beqz len, .Ldone
.set noreorder
1: sb zero, 0(dst)
ADD dst, dst, 1
.set push
.set noat
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
bnez src, 1b
SUB src, src, 1
#else
li v1, 1
bnez src, 1b
SUB src, src, v1
#endif
li v1, -EFAULT
b done
b .Ldone
sw v1, (errptr)
s_exc:
.Ls_exc:
li v0, -1 /* invalid checksum */
li v1, -EFAULT
jr ra
sw v1, (errptr)
.set pop
END(__csum_partial_copy_user)

141
arch/mips/lib/memcpy-inatomic.S
View File

@ -9,6 +9,7 @@
* Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
* Copyright (C) 2002 Broadcom, Inc.
* memcpy/copy_user author: Mark Vandevoorde
* Copyright (C) 2007 Maciej W. Rozycki
*
* Mnemonic names for arguments to memcpy/__copy_user
*/
@ -175,7 +176,11 @@
.text
.set noreorder
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
.set noat
#else
.set at=v1
#endif
/*
* A combined memcpy/__copy_user
@ -204,36 +209,36 @@ LEAF(__copy_user_inatomic)
and t1, dst, ADDRMASK
PREF( 0, 1*32(src) )
PREF( 1, 1*32(dst) )
bnez t2, copy_bytes_checklen
bnez t2, .Lcopy_bytes_checklen
and t0, src, ADDRMASK
PREF( 0, 2*32(src) )
PREF( 1, 2*32(dst) )
bnez t1, dst_unaligned
bnez t1, .Ldst_unaligned
nop
bnez t0, src_unaligned_dst_aligned
bnez t0, .Lsrc_unaligned_dst_aligned
/*
* use delay slot for fall-through
* src and dst are aligned; need to compute rem
*/
both_aligned:
SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
beqz t0, cleanup_both_aligned # len < 8*NBYTES
and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
.Lboth_aligned:
SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
PREF( 0, 3*32(src) )
PREF( 1, 3*32(dst) )
.align 4
1:
EXC( LOAD t0, UNIT(0)(src), l_exc)
EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
SUB len, len, 8*NBYTES
EXC( LOAD t4, UNIT(4)(src), l_exc_copy)
EXC( LOAD t7, UNIT(5)(src), l_exc_copy)
EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy)
STORE t0, UNIT(0)(dst)
STORE t1, UNIT(1)(dst)
EXC( LOAD t0, UNIT(6)(src), l_exc_copy)
EXC( LOAD t1, UNIT(7)(src), l_exc_copy)
EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy)
EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy)
ADD src, src, 8*NBYTES
ADD dst, dst, 8*NBYTES
STORE t2, UNIT(-6)(dst)
@ -250,39 +255,43 @@ EXC( LOAD t1, UNIT(7)(src), l_exc_copy)
/*
* len == rem == the number of bytes left to copy < 8*NBYTES
*/
cleanup_both_aligned:
beqz len, done
.Lcleanup_both_aligned:
beqz len, .Ldone
sltu t0, len, 4*NBYTES
bnez t0, less_than_4units
bnez t0, .Lless_than_4units
and rem, len, (NBYTES-1) # rem = len % NBYTES
/*
* len >= 4*NBYTES
*/
EXC( LOAD t0, UNIT(0)(src), l_exc)
EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
SUB len, len, 4*NBYTES
ADD src, src, 4*NBYTES
STORE t0, UNIT(0)(dst)
STORE t1, UNIT(1)(dst)
STORE t2, UNIT(2)(dst)
STORE t3, UNIT(3)(dst)
beqz len, done
ADD dst, dst, 4*NBYTES
less_than_4units:
.set reorder /* DADDI_WAR */
ADD dst, dst, 4*NBYTES
beqz len, .Ldone
.set noreorder
.Lless_than_4units:
/*
* rem = len % NBYTES
*/
beq rem, len, copy_bytes
beq rem, len, .Lcopy_bytes
nop
1:
EXC( LOAD t0, 0(src), l_exc)
EXC( LOAD t0, 0(src), .Ll_exc)
ADD src, src, NBYTES
SUB len, len, NBYTES
STORE t0, 0(dst)
.set reorder /* DADDI_WAR */
ADD dst, dst, NBYTES
bne rem, len, 1b
ADD dst, dst, NBYTES
.set noreorder
/*
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
@ -296,17 +305,17 @@ EXC( LOAD t0, 0(src), l_exc)
* more instruction-level parallelism.
*/
#define bits t2
beqz len, done
beqz len, .Ldone
ADD t1, dst, len # t1 is just past last byte of dst
li bits, 8*NBYTES
SLL rem, len, 3 # rem = number of bits to keep
EXC( LOAD t0, 0(src), l_exc)
EXC( LOAD t0, 0(src), .Ll_exc)
SUB bits, bits, rem # bits = number of bits to discard
SHIFT_DISCARD t0, t0, bits
STREST t0, -1(t1)
jr ra
move len, zero
dst_unaligned:
.Ldst_unaligned:
/*
* dst is unaligned
* t0 = src & ADDRMASK
@ -317,22 +326,22 @@ dst_unaligned:
* Set match = (src and dst have same alignment)
*/
#define match rem
EXC( LDFIRST t3, FIRST(0)(src), l_exc)
EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
ADD t2, zero, NBYTES
EXC( LDREST t3, REST(0)(src), l_exc_copy)
EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
SUB t2, t2, t1 # t2 = number of bytes copied
xor match, t0, t1
STFIRST t3, FIRST(0)(dst)
beq len, t2, done
beq len, t2, .Ldone
SUB len, len, t2
ADD dst, dst, t2
beqz match, both_aligned
beqz match, .Lboth_aligned
ADD src, src, t2
src_unaligned_dst_aligned:
.Lsrc_unaligned_dst_aligned:
SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
PREF( 0, 3*32(src) )
beqz t0, cleanup_src_unaligned
beqz t0, .Lcleanup_src_unaligned
and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
PREF( 1, 3*32(dst) )
1:
@ -342,15 +351,15 @@ src_unaligned_dst_aligned:
* It's OK to load FIRST(N+1) before REST(N) because the two addresses
* are to the same unit (unless src is aligned, but it's not).
*/
EXC( LDFIRST t0, FIRST(0)(src), l_exc)
EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
SUB len, len, 4*NBYTES
EXC( LDREST t0, REST(0)(src), l_exc_copy)
EXC( LDREST t1, REST(1)(src), l_exc_copy)
EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
EXC( LDREST t2, REST(2)(src), l_exc_copy)
EXC( LDREST t3, REST(3)(src), l_exc_copy)
EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
ADD src, src, 4*NBYTES
#ifdef CONFIG_CPU_SB1
@ -361,32 +370,36 @@ EXC( LDREST t3, REST(3)(src), l_exc_copy)
STORE t2, UNIT(2)(dst)
STORE t3, UNIT(3)(dst)
PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
.set reorder /* DADDI_WAR */
ADD dst, dst, 4*NBYTES
bne len, rem, 1b
ADD dst, dst, 4*NBYTES
.set noreorder
cleanup_src_unaligned:
beqz len, done
.Lcleanup_src_unaligned:
beqz len, .Ldone
and rem, len, NBYTES-1 # rem = len % NBYTES
beq rem, len, copy_bytes
beq rem, len, .Lcopy_bytes
nop
1:
EXC( LDFIRST t0, FIRST(0)(src), l_exc)
EXC( LDREST t0, REST(0)(src), l_exc_copy)
EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
ADD src, src, NBYTES
SUB len, len, NBYTES
STORE t0, 0(dst)
.set reorder /* DADDI_WAR */
ADD dst, dst, NBYTES
bne len, rem, 1b
ADD dst, dst, NBYTES
.set noreorder
copy_bytes_checklen:
beqz len, done
.Lcopy_bytes_checklen:
beqz len, .Ldone
nop
copy_bytes:
.Lcopy_bytes:
/* 0 < len < NBYTES */
#define COPY_BYTE(N) \
EXC( lb t0, N(src), l_exc); \
EXC( lb t0, N(src), .Ll_exc); \
SUB len, len, 1; \
beqz len, done; \
beqz len, .Ldone; \
sb t0, N(dst)
COPY_BYTE(0)
@ -397,16 +410,16 @@ EXC( lb t0, N(src), l_exc); \
COPY_BYTE(4)
COPY_BYTE(5)
#endif
EXC( lb t0, NBYTES-2(src), l_exc)
EXC( lb t0, NBYTES-2(src), .Ll_exc)
SUB len, len, 1
jr ra
sb t0, NBYTES-2(dst)
done:
.Ldone:
jr ra
nop
END(__copy_user_inatomic)
l_exc_copy:
.Ll_exc_copy:
/*
* Copy bytes from src until faulting load address (or until a
* lb faults)
@ -421,12 +434,14 @@ l_exc_copy:
nop
LOAD t0, THREAD_BUADDR(t0)
1:
EXC( lb t1, 0(src), l_exc)
EXC( lb t1, 0(src), .Ll_exc)
ADD src, src, 1
sb t1, 0(dst) # can't fault -- we're copy_from_user
.set reorder /* DADDI_WAR */
ADD dst, dst, 1
bne src, t0, 1b
ADD dst, dst, 1
l_exc:
.set noreorder
.Ll_exc:
LOAD t0, TI_TASK($28)
nop
LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address

250
arch/mips/lib/memcpy.S
View File

@ -9,6 +9,7 @@
* Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
* Copyright (C) 2002 Broadcom, Inc.
* memcpy/copy_user author: Mark Vandevoorde
* Copyright (C) 2007 Maciej W. Rozycki
*
* Mnemonic names for arguments to memcpy/__copy_user
*/
@ -175,7 +176,11 @@
.text
.set noreorder
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
.set noat
#else
.set at=v1
#endif
/*
* A combined memcpy/__copy_user
@ -186,7 +191,7 @@
.align 5
LEAF(memcpy) /* a0=dst a1=src a2=len */
move v0, dst /* return value */
__memcpy:
.L__memcpy:
FEXPORT(__copy_user)
/*
* Note: dst & src may be unaligned, len may be 0
@ -194,6 +199,7 @@ FEXPORT(__copy_user)
*/
#define rem t8
R10KCBARRIER(0(ra))
/*
* The "issue break"s below are very approximate.
* Issue delays for dcache fills will perturb the schedule, as will
@ -207,44 +213,45 @@ FEXPORT(__copy_user)
and t1, dst, ADDRMASK
PREF( 0, 1*32(src) )
PREF( 1, 1*32(dst) )
bnez t2, copy_bytes_checklen
bnez t2, .Lcopy_bytes_checklen
and t0, src, ADDRMASK
PREF( 0, 2*32(src) )
PREF( 1, 2*32(dst) )
bnez t1, dst_unaligned
bnez t1, .Ldst_unaligned
nop
bnez t0, src_unaligned_dst_aligned
bnez t0, .Lsrc_unaligned_dst_aligned
/*
* use delay slot for fall-through
* src and dst are aligned; need to compute rem
*/
both_aligned:
.Lboth_aligned:
SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
beqz t0, cleanup_both_aligned # len < 8*NBYTES
beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
PREF( 0, 3*32(src) )
PREF( 1, 3*32(dst) )
.align 4
1:
EXC( LOAD t0, UNIT(0)(src), l_exc)
EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
R10KCBARRIER(0(ra))
EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
SUB len, len, 8*NBYTES
EXC( LOAD t4, UNIT(4)(src), l_exc_copy)
EXC( LOAD t7, UNIT(5)(src), l_exc_copy)
EXC( STORE t0, UNIT(0)(dst), s_exc_p8u)
EXC( STORE t1, UNIT(1)(dst), s_exc_p7u)
EXC( LOAD t0, UNIT(6)(src), l_exc_copy)
EXC( LOAD t1, UNIT(7)(src), l_exc_copy)
EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy)
EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p8u)
EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p7u)
EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy)
EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy)
ADD src, src, 8*NBYTES
ADD dst, dst, 8*NBYTES
EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u)
EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u)
EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u)
EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u)
EXC( STORE t2, UNIT(-6)(dst), .Ls_exc_p6u)
EXC( STORE t3, UNIT(-5)(dst), .Ls_exc_p5u)
EXC( STORE t4, UNIT(-4)(dst), .Ls_exc_p4u)
EXC( STORE t7, UNIT(-3)(dst), .Ls_exc_p3u)
EXC( STORE t0, UNIT(-2)(dst), .Ls_exc_p2u)
EXC( STORE t1, UNIT(-1)(dst), .Ls_exc_p1u)
PREF( 0, 8*32(src) )
PREF( 1, 8*32(dst) )
bne len, rem, 1b
@ -253,39 +260,45 @@ EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u)
/*
* len == rem == the number of bytes left to copy < 8*NBYTES
*/
cleanup_both_aligned:
beqz len, done
.Lcleanup_both_aligned:
beqz len, .Ldone
sltu t0, len, 4*NBYTES
bnez t0, less_than_4units
bnez t0, .Lless_than_4units
and rem, len, (NBYTES-1) # rem = len % NBYTES
/*
* len >= 4*NBYTES
*/
EXC( LOAD t0, UNIT(0)(src), l_exc)
EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
SUB len, len, 4*NBYTES
ADD src, src, 4*NBYTES
EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
beqz len, done
ADD dst, dst, 4*NBYTES
less_than_4units:
R10KCBARRIER(0(ra))
EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u)
EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u)
EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u)
EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u)
.set reorder /* DADDI_WAR */
ADD dst, dst, 4*NBYTES
beqz len, .Ldone
.set noreorder
.Lless_than_4units:
/*
* rem = len % NBYTES
*/
beq rem, len, copy_bytes
beq rem, len, .Lcopy_bytes
nop
1:
EXC( LOAD t0, 0(src), l_exc)
R10KCBARRIER(0(ra))
EXC( LOAD t0, 0(src), .Ll_exc)
ADD src, src, NBYTES
SUB len, len, NBYTES
EXC( STORE t0, 0(dst), s_exc_p1u)
EXC( STORE t0, 0(dst), .Ls_exc_p1u)
.set reorder /* DADDI_WAR */
ADD dst, dst, NBYTES
bne rem, len, 1b
ADD dst, dst, NBYTES
.set noreorder
/*
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
@ -299,17 +312,17 @@ EXC( STORE t0, 0(dst), s_exc_p1u)
* more instruction-level parallelism.
*/
#define bits t2
beqz len, done
beqz len, .Ldone
ADD t1, dst, len # t1 is just past last byte of dst
li bits, 8*NBYTES
SLL rem, len, 3 # rem = number of bits to keep
EXC( LOAD t0, 0(src), l_exc)
EXC( LOAD t0, 0(src), .Ll_exc)
SUB bits, bits, rem # bits = number of bits to discard
SHIFT_DISCARD t0, t0, bits
EXC( STREST t0, -1(t1), s_exc)
EXC( STREST t0, -1(t1), .Ls_exc)
jr ra
move len, zero
dst_unaligned:
.Ldst_unaligned:
/*
* dst is unaligned
* t0 = src & ADDRMASK
@ -320,22 +333,23 @@ dst_unaligned:
* Set match = (src and dst have same alignment)
*/
#define match rem
EXC( LDFIRST t3, FIRST(0)(src), l_exc)
EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
ADD t2, zero, NBYTES
EXC( LDREST t3, REST(0)(src), l_exc_copy)
EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
SUB t2, t2, t1 # t2 = number of bytes copied
xor match, t0, t1
EXC( STFIRST t3, FIRST(0)(dst), s_exc)
beq len, t2, done
R10KCBARRIER(0(ra))
EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc)
beq len, t2, .Ldone
SUB len, len, t2
ADD dst, dst, t2
beqz match, both_aligned
beqz match, .Lboth_aligned
ADD src, src, t2
src_unaligned_dst_aligned:
.Lsrc_unaligned_dst_aligned:
SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
PREF( 0, 3*32(src) )
beqz t0, cleanup_src_unaligned
beqz t0, .Lcleanup_src_unaligned
and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
PREF( 1, 3*32(dst) )
1:
@ -345,52 +359,59 @@ src_unaligned_dst_aligned:
* It's OK to load FIRST(N+1) before REST(N) because the two addresses
* are to the same unit (unless src is aligned, but it's not).
*/
EXC( LDFIRST t0, FIRST(0)(src), l_exc)
EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
R10KCBARRIER(0(ra))
EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
SUB len, len, 4*NBYTES
EXC( LDREST t0, REST(0)(src), l_exc_copy)
EXC( LDREST t1, REST(1)(src), l_exc_copy)
EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
EXC( LDREST t2, REST(2)(src), l_exc_copy)
EXC( LDREST t3, REST(3)(src), l_exc_copy)
EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
ADD src, src, 4*NBYTES
#ifdef CONFIG_CPU_SB1
nop # improves slotting
#endif
EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u)
EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u)
EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u)
EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u)
PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
.set reorder /* DADDI_WAR */
ADD dst, dst, 4*NBYTES
bne len, rem, 1b
ADD dst, dst, 4*NBYTES
.set noreorder
cleanup_src_unaligned:
beqz len, done
.Lcleanup_src_unaligned:
beqz len, .Ldone
and rem, len, NBYTES-1 # rem = len % NBYTES
beq rem, len, copy_bytes
beq rem, len, .Lcopy_bytes
nop
1:
EXC( LDFIRST t0, FIRST(0)(src), l_exc)
EXC( LDREST t0, REST(0)(src), l_exc_copy)
R10KCBARRIER(0(ra))
EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
ADD src, src, NBYTES
SUB len, len, NBYTES
EXC( STORE t0, 0(dst), s_exc_p1u)
EXC( STORE t0, 0(dst), .Ls_exc_p1u)
.set reorder /* DADDI_WAR */
ADD dst, dst, NBYTES
bne len, rem, 1b
ADD dst, dst, NBYTES
.set noreorder
copy_bytes_checklen:
beqz len, done
.Lcopy_bytes_checklen:
beqz len, .Ldone
nop
copy_bytes:
.Lcopy_bytes:
/* 0 < len < NBYTES */
R10KCBARRIER(0(ra))
#define COPY_BYTE(N) \
EXC( lb t0, N(src), l_exc); \
EXC( lb t0, N(src), .Ll_exc); \
SUB len, len, 1; \
beqz len, done; \
EXC( sb t0, N(dst), s_exc_p1)
beqz len, .Ldone; \
EXC( sb t0, N(dst), .Ls_exc_p1)
COPY_BYTE(0)
COPY_BYTE(1)
@ -400,16 +421,16 @@ EXC( sb t0, N(dst), s_exc_p1)
COPY_BYTE(4)
COPY_BYTE(5)
#endif
EXC( lb t0, NBYTES-2(src), l_exc)
EXC( lb t0, NBYTES-2(src), .Ll_exc)
SUB len, len, 1
jr ra
EXC( sb t0, NBYTES-2(dst), s_exc_p1)
done:
EXC( sb t0, NBYTES-2(dst), .Ls_exc_p1)
.Ldone:
jr ra
nop
END(memcpy)
l_exc_copy:
.Ll_exc_copy:
/*
* Copy bytes from src until faulting load address (or until a
* lb faults)
@ -424,12 +445,14 @@ l_exc_copy:
nop
LOAD t0, THREAD_BUADDR(t0)
1:
EXC( lb t1, 0(src), l_exc)
EXC( lb t1, 0(src), .Ll_exc)
ADD src, src, 1
sb t1, 0(dst) # can't fault -- we're copy_from_user
.set reorder /* DADDI_WAR */
ADD dst, dst, 1
bne src, t0, 1b
ADD dst, dst, 1
l_exc:
.set noreorder
.Ll_exc:
LOAD t0, TI_TASK($28)
nop
LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
@ -446,20 +469,33 @@ l_exc:
* Clear len bytes starting at dst. Can't call __bzero because it
* might modify len. An inefficient loop for these rare times...
*/
beqz len, done
SUB src, len, 1
.set reorder /* DADDI_WAR */
SUB src, len, 1
beqz len, .Ldone
.set noreorder
1: sb zero, 0(dst)
ADD dst, dst, 1
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
bnez src, 1b
SUB src, src, 1
#else
.set push
.set noat
li v1, 1
bnez src, 1b
SUB src, src, v1
.set pop
#endif
jr ra
nop
#define SEXC(n) \
s_exc_p ## n ## u: \
jr ra; \
ADD len, len, n*NBYTES
#define SEXC(n) \
.set reorder; /* DADDI_WAR */ \
.Ls_exc_p ## n ## u: \
ADD len, len, n*NBYTES; \
jr ra; \
.set noreorder
SEXC(8)
SEXC(7)
@ -470,10 +506,12 @@ SEXC(3)
SEXC(2)
SEXC(1)
s_exc_p1:
.Ls_exc_p1:
.set reorder /* DADDI_WAR */
ADD len, len, 1
jr ra
ADD len, len, 1
s_exc:
.set noreorder
.Ls_exc:
jr ra
nop
@ -484,38 +522,44 @@ LEAF(memmove)
sltu t0, a1, t0 # dst + len <= src -> memcpy
sltu t1, a0, t1 # dst >= src + len -> memcpy
and t0, t1
beqz t0, __memcpy
beqz t0, .L__memcpy
move v0, a0 /* return value */
beqz a2, r_out
beqz a2, .Lr_out
END(memmove)
/* fall through to __rmemcpy */
LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
sltu t0, a1, a0
beqz t0, r_end_bytes_up # src >= dst
beqz t0, .Lr_end_bytes_up # src >= dst
nop
ADD a0, a2 # dst = dst + len
ADD a1, a2 # src = src + len
r_end_bytes:
.Lr_end_bytes:
R10KCBARRIER(0(ra))
lb t0, -1(a1)
SUB a2, a2, 0x1
sb t0, -1(a0)
SUB a1, a1, 0x1
bnez a2, r_end_bytes
SUB a0, a0, 0x1
.set reorder /* DADDI_WAR */
SUB a0, a0, 0x1
bnez a2, .Lr_end_bytes
.set noreorder
r_out:
.Lr_out:
jr ra
move a2, zero
r_end_bytes_up:
.Lr_end_bytes_up:
R10KCBARRIER(0(ra))
lb t0, (a1)
SUB a2, a2, 0x1
sb t0, (a0)
ADD a1, a1, 0x1
bnez a2, r_end_bytes_up
ADD a0, a0, 0x1
.set reorder /* DADDI_WAR */
ADD a0, a0, 0x1
bnez a2, .Lr_end_bytes_up
.set noreorder
jr ra
move a2, zero

44
arch/mips/lib/memset.S
View File

@ -5,6 +5,7 @@
*
* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki
*/
#include <asm/asm.h>
#include <asm/asm-offsets.h>
@ -71,34 +72,45 @@ LEAF(memset)
FEXPORT(__bzero)
sltiu t0, a2, LONGSIZE /* very small region? */
bnez t0, small_memset
bnez t0, .Lsmall_memset
andi t0, a0, LONGMASK /* aligned? */
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
beqz t0, 1f
PTR_SUBU t0, LONGSIZE /* alignment in bytes */
#else
.set noat
li AT, LONGSIZE
beqz t0, 1f
PTR_SUBU t0, AT /* alignment in bytes */
.set at
#endif
R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
EX(LONG_S_L, a1, (a0), first_fixup) /* make word/dword aligned */
EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
#endif
#ifdef __MIPSEL__
EX(LONG_S_R, a1, (a0), first_fixup) /* make word/dword aligned */
EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
#endif
PTR_SUBU a0, t0 /* long align ptr */
PTR_ADDU a2, t0 /* correct size */
1: ori t1, a2, 0x3f /* # of full blocks */
xori t1, 0x3f
beqz t1, memset_partial /* no block to fill */
beqz t1, .Lmemset_partial /* no block to fill */
andi t0, a2, 0x40-LONGSIZE
PTR_ADDU t1, a0 /* end address */
.set reorder
1: PTR_ADDIU a0, 64
f_fill64 a0, -64, a1, fwd_fixup
R10KCBARRIER(0(ra))
f_fill64 a0, -64, a1, .Lfwd_fixup
bne t1, a0, 1b
.set noreorder
memset_partial:
.Lmemset_partial:
R10KCBARRIER(0(ra))
PTR_LA t1, 2f /* where to start */
#if LONGSIZE == 4
PTR_SUBU t1, t0
@ -106,7 +118,7 @@ memset_partial:
.set noat
LONG_SRL AT, t0, 1
PTR_SUBU t1, AT
.set noat
.set at
#endif
jr t1
PTR_ADDU a0, t0 /* dest ptr */
@ -114,26 +126,28 @@ memset_partial:
.set push
.set noreorder
.set nomacro
f_fill64 a0, -64, a1, partial_fixup /* ... but first do longs ... */
f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */
2: .set pop
andi a2, LONGMASK /* At most one long to go */
beqz a2, 1f
PTR_ADDU a0, a2 /* What's left */
R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
EX(LONG_S_R, a1, -1(a0), last_fixup)
EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
#endif
#ifdef __MIPSEL__
EX(LONG_S_L, a1, -1(a0), last_fixup)
EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
#endif
1: jr ra
move a2, zero
small_memset:
.Lsmall_memset:
beqz a2, 2f
PTR_ADDU t1, a0, a2
1: PTR_ADDIU a0, 1 /* fill bytewise */
R10KCBARRIER(0(ra))
bne t1, a0, 1b
sb a1, -1(a0)
@ -141,11 +155,11 @@ small_memset:
move a2, zero
END(memset)
first_fixup:
.Lfirst_fixup:
jr ra
nop
fwd_fixup:
.Lfwd_fixup:
PTR_L t0, TI_TASK($28)
LONG_L t0, THREAD_BUADDR(t0)
andi a2, 0x3f
@ -153,7 +167,7 @@ fwd_fixup:
jr ra
LONG_SUBU a2, t0
partial_fixup:
.Lpartial_fixup:
PTR_L t0, TI_TASK($28)
LONG_L t0, THREAD_BUADDR(t0)
andi a2, LONGMASK
@ -161,6 +175,6 @@ partial_fixup:
jr ra
LONG_SUBU a2, t0
last_fixup:
.Llast_fixup:
jr ra
andi v1, a2, LONGMASK

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