mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'icc-rpmh-qos' into icc-next
This series adds QoS support for QNOC type device which can be found on SC7280 platform. It adds support for programming priority, priority forward disable and urgency forwarding. This helps in priortizing the traffic originating from different interconnect masters at NOC (Network On Chip). * icc-rpmh-qos dt-bindings: interconnect: add clock property to enable QOS on SC7280 interconnect: qcom: icc-rpmh: Add QoS configuration support interconnect: qcom: sc7280: enable QoS configuration interconnect: qcom: Fix DT backwards compatibility for QoS Link: https://lore.kernel.org/r/20240607173927.26321-1-quic_okukatla@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
226e58b209
@ -35,6 +35,10 @@ properties:
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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@ -53,10 +57,50 @@ allOf:
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required:
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- reg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7280-aggre1-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre UFS PHY AXI clock
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- description: aggre USB3 PRIM AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7280-aggre2-noc
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then:
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properties:
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clocks:
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items:
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- description: RPMH CC IPA clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7280-aggre1-noc
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- qcom,sc7280-aggre2-noc
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then:
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required:
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- clocks
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else:
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properties:
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clocks: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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interconnect {
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compatible = "qcom,sc7280-clk-virt";
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#interconnect-cells = <2>;
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@ -69,3 +113,12 @@ examples:
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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interconnect@16e0000 {
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reg = <0x016e0000 0x1c080>;
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compatible = "qcom,sc7280-aggre1-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
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};
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@ -1,8 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interconnect.h>
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#include <linux/interconnect-provider.h>
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#include <linux/module.h>
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@ -14,6 +17,38 @@
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#include "icc-common.h"
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#include "icc-rpmh.h"
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/* QNOC QoS */
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#define QOSGEN_MAINCTL_LO(p, qp) (0x8 + (p->port_offsets[qp]))
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#define QOS_SLV_URG_MSG_EN_MASK GENMASK(3, 3)
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#define QOS_DFLT_PRIO_MASK GENMASK(6, 4)
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#define QOS_DISABLE_MASK GENMASK(24, 24)
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/**
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* qcom_icc_set_qos - initialize static QoS configurations
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* @qp: qcom icc provider to which @node belongs
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* @node: qcom icc node to operate on
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*/
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static void qcom_icc_set_qos(struct qcom_icc_provider *qp,
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struct qcom_icc_node *node)
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{
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const struct qcom_icc_qosbox *qos = node->qosbox;
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int port;
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for (port = 0; port < qos->num_ports; port++) {
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regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
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QOS_DISABLE_MASK,
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FIELD_PREP(QOS_DISABLE_MASK, qos->prio_fwd_disable));
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regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
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QOS_DFLT_PRIO_MASK,
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FIELD_PREP(QOS_DFLT_PRIO_MASK, qos->prio));
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regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
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QOS_SLV_URG_MSG_EN_MASK,
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FIELD_PREP(QOS_SLV_URG_MSG_EN_MASK, qos->urg_fwd));
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}
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}
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/**
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* qcom_icc_pre_aggregate - cleans up stale values from prior icc_set
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* @node: icc node to operate on
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@ -159,6 +194,36 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
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}
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EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
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/**
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* qcom_icc_rpmh_configure_qos - configure QoS parameters
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* @qp: qcom icc provider associated with QoS endpoint nodes
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*
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* Return: 0 on success, or an error code otherwise
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*/
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static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp)
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{
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struct qcom_icc_node *qnode;
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size_t i;
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int ret;
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ret = clk_bulk_prepare_enable(qp->num_clks, qp->clks);
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if (ret)
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return ret;
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for (i = 0; i < qp->num_nodes; i++) {
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qnode = qp->nodes[i];
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if (!qnode)
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continue;
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if (qnode->qosbox)
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qcom_icc_set_qos(qp, qnode);
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}
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clk_bulk_disable_unprepare(qp->num_clks, qp->clks);
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return ret;
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}
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int qcom_icc_rpmh_probe(struct platform_device *pdev)
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{
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const struct qcom_icc_desc *desc;
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@ -199,7 +264,9 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
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qp->dev = dev;
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qp->bcms = desc->bcms;
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qp->nodes = desc->nodes;
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qp->num_bcms = desc->num_bcms;
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qp->num_nodes = desc->num_nodes;
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qp->voter = of_bcm_voter_get(qp->dev, NULL);
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if (IS_ERR(qp->voter))
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@ -229,6 +296,32 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
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data->nodes[i] = node;
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}
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if (desc->config) {
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struct resource *res;
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void __iomem *base;
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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goto skip_qos_config;
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qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
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if (IS_ERR(qp->regmap)) {
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dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap));
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goto skip_qos_config;
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}
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qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
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if (qp->num_clks < 0 || (!qp->num_clks && desc->qos_clks_required)) {
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dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
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goto skip_qos_config;
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}
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ret = qcom_icc_rpmh_configure_qos(qp);
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if (ret)
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dev_info(dev, "Failed to program QoS: %d\n", ret);
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}
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skip_qos_config:
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ret = icc_provider_register(provider);
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if (ret)
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goto err_remove_nodes;
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@ -1,12 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
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#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <linux/regmap.h>
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#define to_qcom_provider(_provider) \
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container_of(_provider, struct qcom_icc_provider, provider)
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@ -18,6 +20,11 @@
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* @bcms: list of bcms that maps to the provider
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* @num_bcms: number of @bcms
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* @voter: bcm voter targeted by this provider
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* @nodes: list of icc nodes that maps to the provider
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* @num_nodes: number of @nodes
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* @regmap: used for QoS, register access
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* @clks : clks required for register access
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* @num_clks: number of @clks
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*/
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struct qcom_icc_provider {
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struct icc_provider provider;
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@ -25,6 +32,11 @@ struct qcom_icc_provider {
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struct qcom_icc_bcm * const *bcms;
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size_t num_bcms;
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struct bcm_voter *voter;
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struct qcom_icc_node * const *nodes;
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size_t num_nodes;
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struct regmap *regmap;
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struct clk_bulk_data *clks;
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int num_clks;
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};
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/**
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@ -41,6 +53,26 @@ struct bcm_db {
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u8 reserved;
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};
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#define MAX_PORTS 2
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/**
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* struct qcom_icc_qosbox - Qualcomm specific QoS config
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* @prio: priority value assigned to requests on the node
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* @urg_fwd: whether to forward the urgency promotion issued by master
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* (endpoint), or discard
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* @prio_fwd_disable: whether to forward the priority driven by master, or
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* override by @prio
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* @num_ports: number of @ports
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* @port_offsets: qos register offsets
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*/
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struct qcom_icc_qosbox {
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const u32 prio;
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const bool urg_fwd;
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const bool prio_fwd_disable;
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const u32 num_ports;
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const u32 port_offsets[MAX_PORTS];
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};
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#define MAX_LINKS 128
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#define MAX_BCMS 64
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#define MAX_BCM_PER_NODE 3
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@ -58,6 +90,7 @@ struct bcm_db {
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* @max_peak: current max aggregate value of all peak bw requests
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* @bcms: list of bcms associated with this logical node
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* @num_bcms: num of @bcms
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* @qosbox: QoS config data associated with node
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*/
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struct qcom_icc_node {
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const char *name;
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@ -70,6 +103,7 @@ struct qcom_icc_node {
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u64 max_peak[QCOM_ICC_NUM_BUCKETS];
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struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
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size_t num_bcms;
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const struct qcom_icc_qosbox *qosbox;
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};
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/**
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@ -114,10 +148,12 @@ struct qcom_icc_fabric {
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};
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struct qcom_icc_desc {
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const struct regmap_config *config;
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struct qcom_icc_node * const *nodes;
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size_t num_nodes;
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struct qcom_icc_bcm * const *bcms;
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size_t num_bcms;
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bool qos_clks_required;
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};
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|
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int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
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@ -1,6 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
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*
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||||
*/
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@ -21,6 +22,12 @@ static struct qcom_icc_node qhm_qspi = {
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.id = SC7280_MASTER_QSPI_0,
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.channels = 1,
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.buswidth = 4,
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.qosbox = &(const struct qcom_icc_qosbox) {
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.num_ports = 1,
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.port_offsets = { 0x7000 },
|
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.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -30,6 +37,12 @@ static struct qcom_icc_node qhm_qup0 = {
|
||||
.id = SC7280_MASTER_QUP_0,
|
||||
.channels = 1,
|
||||
.buswidth = 4,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x11000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -39,6 +52,12 @@ static struct qcom_icc_node qhm_qup1 = {
|
||||
.id = SC7280_MASTER_QUP_1,
|
||||
.channels = 1,
|
||||
.buswidth = 4,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x8000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -57,6 +76,12 @@ static struct qcom_icc_node xm_sdc1 = {
|
||||
.id = SC7280_MASTER_SDCC_1,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xc000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -66,6 +91,12 @@ static struct qcom_icc_node xm_sdc2 = {
|
||||
.id = SC7280_MASTER_SDCC_2,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xe000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -75,6 +106,12 @@ static struct qcom_icc_node xm_sdc4 = {
|
||||
.id = SC7280_MASTER_SDCC_4,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x9000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -84,6 +121,12 @@ static struct qcom_icc_node xm_ufs_mem = {
|
||||
.id = SC7280_MASTER_UFS_MEM,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xa000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -102,6 +145,12 @@ static struct qcom_icc_node xm_usb3_0 = {
|
||||
.id = SC7280_MASTER_USB3_0,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xb000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A1NOC_SNOC },
|
||||
};
|
||||
@ -111,6 +160,12 @@ static struct qcom_icc_node qhm_qdss_bam = {
|
||||
.id = SC7280_MASTER_QDSS_BAM,
|
||||
.channels = 1,
|
||||
.buswidth = 4,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x18000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A2NOC_SNOC },
|
||||
};
|
||||
@ -129,6 +184,12 @@ static struct qcom_icc_node qnm_cnoc_datapath = {
|
||||
.id = SC7280_MASTER_CNOC_A2NOC,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x1c000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A2NOC_SNOC },
|
||||
};
|
||||
@ -138,6 +199,12 @@ static struct qcom_icc_node qxm_crypto = {
|
||||
.id = SC7280_MASTER_CRYPTO,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x1d000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A2NOC_SNOC },
|
||||
};
|
||||
@ -147,6 +214,12 @@ static struct qcom_icc_node qxm_ipa = {
|
||||
.id = SC7280_MASTER_IPA,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x10000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A2NOC_SNOC },
|
||||
};
|
||||
@ -173,6 +246,12 @@ static struct qcom_icc_node xm_qdss_etr = {
|
||||
.id = SC7280_MASTER_QDSS_ETR,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x15000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_A2NOC_SNOC },
|
||||
};
|
||||
@ -305,6 +384,12 @@ static struct qcom_icc_node alm_gpu_tcu = {
|
||||
.id = SC7280_MASTER_GPU_TCU,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xd7000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 2,
|
||||
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -314,6 +399,12 @@ static struct qcom_icc_node alm_sys_tcu = {
|
||||
.id = SC7280_MASTER_SYS_TCU,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xd6000 },
|
||||
.prio = 6,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 2,
|
||||
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -333,6 +424,12 @@ static struct qcom_icc_node qnm_cmpnoc = {
|
||||
.id = SC7280_MASTER_COMPUTE_NOC,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0x21000, 0x61000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 2,
|
||||
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -353,6 +450,12 @@ static struct qcom_icc_node qnm_gpu = {
|
||||
.id = SC7280_MASTER_GFX3D,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0x22000, 0x62000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 2,
|
||||
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -362,6 +465,12 @@ static struct qcom_icc_node qnm_mnoc_hf = {
|
||||
.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0x23000, 0x63000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -371,6 +480,12 @@ static struct qcom_icc_node qnm_mnoc_sf = {
|
||||
.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xcf000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 2,
|
||||
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -389,6 +504,12 @@ static struct qcom_icc_node qnm_snoc_gc = {
|
||||
.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xd3000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_LLCC },
|
||||
};
|
||||
@ -398,6 +519,12 @@ static struct qcom_icc_node qnm_snoc_sf = {
|
||||
.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xd4000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 3,
|
||||
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
|
||||
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
|
||||
@ -437,6 +564,12 @@ static struct qcom_icc_node qnm_video0 = {
|
||||
.id = SC7280_MASTER_VIDEO_P0,
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x14000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
|
||||
};
|
||||
@ -446,6 +579,12 @@ static struct qcom_icc_node qnm_video_cpu = {
|
||||
.id = SC7280_MASTER_VIDEO_PROC,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x15000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
|
||||
};
|
||||
@ -455,6 +594,12 @@ static struct qcom_icc_node qxm_camnoc_hf = {
|
||||
.id = SC7280_MASTER_CAMNOC_HF,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0x10000, 0x10180 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
|
||||
};
|
||||
@ -464,6 +609,12 @@ static struct qcom_icc_node qxm_camnoc_icp = {
|
||||
.id = SC7280_MASTER_CAMNOC_ICP,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x11000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
|
||||
};
|
||||
@ -473,6 +624,12 @@ static struct qcom_icc_node qxm_camnoc_sf = {
|
||||
.id = SC7280_MASTER_CAMNOC_SF,
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x12000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
|
||||
};
|
||||
@ -482,6 +639,12 @@ static struct qcom_icc_node qxm_mdp0 = {
|
||||
.id = SC7280_MASTER_MDP0,
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x16000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
|
||||
};
|
||||
@ -536,6 +699,12 @@ static struct qcom_icc_node qxm_pimem = {
|
||||
.id = SC7280_MASTER_PIMEM,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x8000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
|
||||
};
|
||||
@ -545,6 +714,12 @@ static struct qcom_icc_node xm_gic = {
|
||||
.id = SC7280_MASTER_GIC,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &(const struct qcom_icc_qosbox) {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xa000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
},
|
||||
.num_links = 1,
|
||||
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
|
||||
};
|
||||
@ -1502,17 +1677,35 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
|
||||
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1c080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_aggre1_noc = {
|
||||
.config = &sc7280_aggre1_noc_regmap_config,
|
||||
.nodes = aggre1_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
|
||||
.bcms = aggre1_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
|
||||
.qos_clks_required = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
|
||||
&bcm_ce0,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x2b080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
|
||||
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
|
||||
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
|
||||
@ -1525,10 +1718,12 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_aggre2_noc = {
|
||||
.config = &sc7280_aggre2_noc_regmap_config,
|
||||
.nodes = aggre2_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
|
||||
.bcms = aggre2_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
|
||||
.qos_clks_required = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
|
||||
@ -1605,7 +1800,16 @@ static struct qcom_icc_node * const cnoc2_nodes[] = {
|
||||
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_cnoc2_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_cnoc2 = {
|
||||
.config = &sc7280_cnoc2_regmap_config,
|
||||
.nodes = cnoc2_nodes,
|
||||
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
|
||||
.bcms = cnoc2_bcms,
|
||||
@ -1637,7 +1841,16 @@ static struct qcom_icc_node * const cnoc3_nodes[] = {
|
||||
[SLAVE_TCU] = &xs_sys_tcu_cfg,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_cnoc3_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_cnoc3 = {
|
||||
.config = &sc7280_cnoc3_regmap_config,
|
||||
.nodes = cnoc3_nodes,
|
||||
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
|
||||
.bcms = cnoc3_bcms,
|
||||
@ -1653,7 +1866,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
|
||||
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_dc_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x5080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_dc_noc = {
|
||||
.config = &sc7280_dc_noc_regmap_config,
|
||||
.nodes = dc_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
|
||||
.bcms = dc_noc_bcms,
|
||||
@ -1689,7 +1911,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
|
||||
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_gem_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xe2200,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_gem_noc = {
|
||||
.config = &sc7280_gem_noc_regmap_config,
|
||||
.nodes = gem_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
||||
.bcms = gem_noc_bcms,
|
||||
@ -1709,7 +1940,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
|
||||
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xf080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
|
||||
.config = &sc7280_lpass_ag_noc_regmap_config,
|
||||
.nodes = lpass_ag_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
|
||||
.bcms = lpass_ag_noc_bcms,
|
||||
@ -1726,7 +1966,16 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
|
||||
[SLAVE_EBI1] = &ebi,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_mc_virt_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x4,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_mc_virt = {
|
||||
.config = &sc7280_mc_virt_regmap_config,
|
||||
.nodes = mc_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
|
||||
.bcms = mc_virt_bcms,
|
||||
@ -1753,7 +2002,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
|
||||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_mmss_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1e080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_mmss_noc = {
|
||||
.config = &sc7280_mmss_noc_regmap_config,
|
||||
.nodes = mmss_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
|
||||
.bcms = mmss_noc_bcms,
|
||||
@ -1772,7 +2030,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
|
||||
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_nsp_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_nsp_noc = {
|
||||
.config = &sc7280_nsp_noc_regmap_config,
|
||||
.nodes = nsp_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
|
||||
.bcms = nsp_noc_bcms,
|
||||
@ -1797,7 +2064,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
|
||||
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sc7280_system_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x15480,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sc7280_system_noc = {
|
||||
.config = &sc7280_system_noc_regmap_config,
|
||||
.nodes = system_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
||||
.bcms = system_noc_bcms,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user