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firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
Implement support for DRAM MRQ GSCs. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> [treding@nvidia.com: drop unnecessary discrimination enum] Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver
Thierry Reding
parent
ac9a78681b
commit
2abd484ca4
@ -4,7 +4,9 @@
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*/
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#include <linux/genalloc.h>
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#include <linux/io.h>
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#include <linux/mailbox_client.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/bpmp.h>
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@ -18,7 +20,10 @@ struct tegra186_bpmp {
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struct {
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struct gen_pool *pool;
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void __iomem *virt;
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union {
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void __iomem *sram;
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void *dram;
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};
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dma_addr_t phys;
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} tx, rx;
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@ -118,8 +123,13 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp_channel *channel,
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queue_size = tegra_ivc_total_queue_size(message_size);
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offset = queue_size * index;
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iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset);
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iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset);
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if (priv->rx.pool) {
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iosys_map_set_vaddr_iomem(&rx, priv->rx.sram + offset);
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iosys_map_set_vaddr_iomem(&tx, priv->tx.sram + offset);
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} else {
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iosys_map_set_vaddr(&rx, priv->rx.dram + offset);
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iosys_map_set_vaddr(&tx, priv->tx.dram + offset);
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}
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err = tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &tx,
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priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify,
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@ -158,18 +168,72 @@ static void mbox_handle_rx(struct mbox_client *client, void *data)
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tegra_bpmp_handle_rx(bpmp);
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}
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static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
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static void tegra186_bpmp_teardown_channels(struct tegra_bpmp *bpmp)
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{
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struct tegra186_bpmp *priv;
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struct tegra186_bpmp *priv = bpmp->priv;
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unsigned int i;
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for (i = 0; i < bpmp->threaded.count; i++) {
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if (!bpmp->threaded_channels[i].bpmp)
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continue;
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tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]);
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}
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tegra186_bpmp_channel_cleanup(bpmp->rx_channel);
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tegra186_bpmp_channel_cleanup(bpmp->tx_channel);
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if (priv->tx.pool) {
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gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.sram, 4096);
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gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.sram, 4096);
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}
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}
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static int tegra186_bpmp_dram_init(struct tegra_bpmp *bpmp)
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{
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struct tegra186_bpmp *priv = bpmp->priv;
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struct device_node *np;
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struct resource res;
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size_t size;
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int err;
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priv = devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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np = of_parse_phandle(bpmp->dev->of_node, "memory-region", 0);
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if (!np)
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return -ENODEV;
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bpmp->priv = priv;
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priv->parent = bpmp;
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err = of_address_to_resource(np, 0, &res);
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if (err < 0) {
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dev_warn(bpmp->dev, "failed to parse memory region: %d\n", err);
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return err;
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}
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size = resource_size(&res);
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if (size < SZ_8K) {
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dev_warn(bpmp->dev, "DRAM region must be larger than 8 KiB\n");
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return -EINVAL;
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}
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priv->tx.phys = res.start;
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priv->rx.phys = res.start + SZ_4K;
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priv->tx.dram = devm_memremap(bpmp->dev, priv->tx.phys, size,
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MEMREMAP_WC);
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if (IS_ERR(priv->tx.dram)) {
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err = PTR_ERR(priv->tx.dram);
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dev_warn(bpmp->dev, "failed to map DRAM region: %d\n", err);
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return err;
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}
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priv->rx.dram = priv->tx.dram + SZ_4K;
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return 0;
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}
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static int tegra186_bpmp_sram_init(struct tegra_bpmp *bpmp)
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{
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struct tegra186_bpmp *priv = bpmp->priv;
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int err;
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priv->tx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 0);
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if (!priv->tx.pool) {
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@ -177,8 +241,9 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
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return -EPROBE_DEFER;
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}
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priv->tx.virt = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys);
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if (!priv->tx.virt) {
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priv->tx.sram = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096,
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&priv->tx.phys);
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if (!priv->tx.sram) {
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dev_err(bpmp->dev, "failed to allocate from TX pool\n");
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return -ENOMEM;
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}
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@ -190,22 +255,45 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
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goto free_tx;
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}
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priv->rx.virt = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096, &priv->rx.phys);
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if (!priv->rx.virt) {
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priv->rx.sram = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096,
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&priv->rx.phys);
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if (!priv->rx.sram) {
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dev_err(bpmp->dev, "failed to allocate from RX pool\n");
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err = -ENOMEM;
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goto free_tx;
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}
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return 0;
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free_tx:
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gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.sram, 4096);
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return err;
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}
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static int tegra186_bpmp_setup_channels(struct tegra_bpmp *bpmp)
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{
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unsigned int i;
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int err;
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err = tegra186_bpmp_dram_init(bpmp);
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if (err == -ENODEV) {
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err = tegra186_bpmp_sram_init(bpmp);
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if (err < 0)
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return err;
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}
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err = tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp,
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bpmp->soc->channels.cpu_tx.offset);
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if (err < 0)
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goto free_rx;
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return err;
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err = tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp,
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bpmp->soc->channels.cpu_rx.offset);
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if (err < 0)
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goto cleanup_tx_channel;
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if (err < 0) {
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tegra186_bpmp_channel_cleanup(bpmp->tx_channel);
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return err;
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}
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for (i = 0; i < bpmp->threaded.count; i++) {
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unsigned int index = bpmp->soc->channels.thread.offset + i;
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@ -213,9 +301,43 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
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err = tegra186_bpmp_channel_init(&bpmp->threaded_channels[i],
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bpmp, index);
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if (err < 0)
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goto cleanup_channels;
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break;
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}
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if (err < 0)
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tegra186_bpmp_teardown_channels(bpmp);
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return err;
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}
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static void tegra186_bpmp_reset_channels(struct tegra_bpmp *bpmp)
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{
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unsigned int i;
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/* reset message channels */
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tegra186_bpmp_channel_reset(bpmp->tx_channel);
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tegra186_bpmp_channel_reset(bpmp->rx_channel);
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for (i = 0; i < bpmp->threaded.count; i++)
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tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]);
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}
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static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
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{
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struct tegra186_bpmp *priv;
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int err;
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priv = devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->parent = bpmp;
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bpmp->priv = priv;
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err = tegra186_bpmp_setup_channels(bpmp);
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if (err < 0)
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return err;
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/* mbox registration */
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priv->mbox.client.dev = bpmp->dev;
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priv->mbox.client.rx_callback = mbox_handle_rx;
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@ -226,63 +348,27 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
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if (IS_ERR(priv->mbox.channel)) {
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err = PTR_ERR(priv->mbox.channel);
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dev_err(bpmp->dev, "failed to get HSP mailbox: %d\n", err);
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goto cleanup_channels;
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tegra186_bpmp_teardown_channels(bpmp);
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return err;
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}
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tegra186_bpmp_channel_reset(bpmp->tx_channel);
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tegra186_bpmp_channel_reset(bpmp->rx_channel);
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for (i = 0; i < bpmp->threaded.count; i++)
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tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]);
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tegra186_bpmp_reset_channels(bpmp);
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return 0;
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cleanup_channels:
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for (i = 0; i < bpmp->threaded.count; i++) {
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if (!bpmp->threaded_channels[i].bpmp)
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continue;
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tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]);
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}
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tegra186_bpmp_channel_cleanup(bpmp->rx_channel);
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cleanup_tx_channel:
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tegra186_bpmp_channel_cleanup(bpmp->tx_channel);
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free_rx:
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gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096);
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free_tx:
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gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096);
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return err;
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}
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static void tegra186_bpmp_deinit(struct tegra_bpmp *bpmp)
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{
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struct tegra186_bpmp *priv = bpmp->priv;
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unsigned int i;
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mbox_free_channel(priv->mbox.channel);
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for (i = 0; i < bpmp->threaded.count; i++)
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tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]);
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tegra186_bpmp_channel_cleanup(bpmp->rx_channel);
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tegra186_bpmp_channel_cleanup(bpmp->tx_channel);
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gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096);
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gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096);
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tegra186_bpmp_teardown_channels(bpmp);
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}
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static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp)
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{
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unsigned int i;
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/* reset message channels */
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tegra186_bpmp_channel_reset(bpmp->tx_channel);
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tegra186_bpmp_channel_reset(bpmp->rx_channel);
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for (i = 0; i < bpmp->threaded.count; i++)
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tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]);
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tegra186_bpmp_reset_channels(bpmp);
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return 0;
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}
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@ -735,6 +735,8 @@ static int tegra_bpmp_probe(struct platform_device *pdev)
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if (!bpmp->threaded_channels)
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return -ENOMEM;
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platform_set_drvdata(pdev, bpmp);
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err = bpmp->soc->ops->init(bpmp);
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if (err < 0)
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return err;
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@ -758,8 +760,6 @@ static int tegra_bpmp_probe(struct platform_device *pdev)
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dev_info(&pdev->dev, "firmware: %.*s\n", (int)sizeof(tag), tag);
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platform_set_drvdata(pdev, bpmp);
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err = of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev);
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if (err < 0)
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goto free_mrq;
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