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MIPS: Fix typos
Fix typos, most reported by "codespell arch/mips". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-mips@vger.kernel.org Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Bjorn Helgaas
Thomas Bogendoerfer
parent
8e1803900e
commit
2f9060b1db
@ -147,21 +147,21 @@ static const struct gpio_keys_button
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bcm47xx_buttons_buffalo_whr_g125[] __initconst = {
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BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
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BCM47XX_GPIO_KEY(4, KEY_RESTART),
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BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
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BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
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};
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static const struct gpio_keys_button
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bcm47xx_buttons_buffalo_whr_g54s[] __initconst = {
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BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
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BCM47XX_GPIO_KEY_H(4, KEY_RESTART),
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BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
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BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
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};
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static const struct gpio_keys_button
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bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = {
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BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
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BCM47XX_GPIO_KEY(4, KEY_RESTART),
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BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
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BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
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};
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static const struct gpio_keys_button
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@ -174,7 +174,7 @@ static void enetsw_set(struct clk *clk, int enable)
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}
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if (enable) {
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/* reset switch core afer clock change */
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/* reset switch core after clock change */
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bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
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msleep(10);
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bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
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@ -304,7 +304,7 @@ static void xtm_set(struct clk *clk, int enable)
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bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
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if (enable) {
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/* reset sar core afer clock change */
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/* reset sar core after clock change */
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bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
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mdelay(1);
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bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
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@ -3,7 +3,7 @@
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* MIPS-specific debug support for pre-boot environment
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*
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* NOTE: putc() is board specific, if your board have a 16550 compatible uart,
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* please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
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* please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. otherwise, you
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* need to implement your own putc().
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*/
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#include <linux/compiler.h>
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@ -443,7 +443,7 @@ int main(int argc, char *argv[])
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efh.f_symptr = 0;
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efh.f_nsyms = 0;
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efh.f_opthdr = sizeof eah;
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efh.f_flags = 0x100f; /* Stripped, not sharable. */
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efh.f_flags = 0x100f; /* Stripped, not shareable. */
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memset(esecs, 0, sizeof esecs);
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strcpy(esecs[0].s_name, ".text");
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@ -113,7 +113,7 @@ static struct clocksource clocksource_mips = {
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unsigned long long notrace sched_clock(void)
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{
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/* 64-bit arithmatic can overflow, so use 128-bit. */
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/* 64-bit arithmetic can overflow, so use 128-bit. */
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u64 t1, t2, t3;
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unsigned long long rv;
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u64 mult = clocksource_mips.mult;
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@ -143,7 +143,7 @@ static void cvmx_boot_vector_init(void *mem)
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uint64_t v = _cvmx_bootvector_data[i];
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if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
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v &= 0xffffffff00000000ull; /* KScratch not availble. */
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v &= 0xffffffff00000000ull; /* KScratch not available */
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
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}
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@ -264,7 +264,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
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* Convert !0 address_min and 0 address_max to special case of
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* range that specifies an exact memory block to allocate. Do
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* this before other checks and adjustments so that this
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* tranformation will be validated.
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* transformation will be validated.
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*/
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if (address_min && !address_max)
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address_max = address_min + req_size;
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@ -192,7 +192,7 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
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}
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/*
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* Shutdown a queue a free it's command buffers to the FPA. The
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* Shutdown a queue and free its command buffers to the FPA. The
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* hardware connected to the queue must be stopped before this
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* function is called.
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*
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@ -285,7 +285,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
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/*
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* Return the command buffer to be written to. The purpose of this
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* function is to allow CVMX routine access t othe low level buffer
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* function is to allow CVMX routine access to the low level buffer
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* for initial hardware setup. User applications should not call this
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* function directly.
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*
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@ -103,7 +103,7 @@ uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
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/**
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* Shift long sequences of zeros into the QLM JTAG chain. It is
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* common to need to shift more than 32 bits of zeros into the
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* chain. This function is a convience wrapper around
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* chain. This function is a convenience wrapper around
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* cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
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* zeros at a time.
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*
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@ -615,7 +615,7 @@ int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
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/*
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* Each packet has a 12 bytes of interframe gap, an 8 byte
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* preamble, and a 4 byte CRC. These are not included in the
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* per word count. Multiply by 8 to covert to bits and divide
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* per word count. Multiply by 8 to convert to bits and divide
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* by 256 for limit granularity.
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*/
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pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
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@ -973,7 +973,7 @@ int __init octeon_prune_device_tree(void)
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* zero.
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*/
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/* Asume that CS1 immediately follows. */
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/* Assume that CS1 immediately follows. */
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mio_boot_reg_cfg.u64 =
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cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
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region1_base = mio_boot_reg_cfg.s.base << 16;
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@ -15,11 +15,11 @@
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/*
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* For 64bit kernels working with a 32bit ARC PROM pointer arguments
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* for ARC calls need to reside in CKEG0/1. But as soon as the kernel
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* switches to it's first kernel thread stack is set to an address in
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* switches to its first kernel thread stack is set to an address in
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* XKPHYS, so anything on stack can't be used anymore. This is solved
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* by using a * static declartion variables are put into BSS, which is
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* by using a * static declaration variables are put into BSS, which is
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* linked to a CKSEG0 address. Since this is only used on UP platforms
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* there is not spinlock needed
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* there is no spinlock needed
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*/
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#define O32_STATIC static
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#else
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@ -10,7 +10,7 @@
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/*
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* mips_debugfs_dir corresponds to the "mips" directory at the top level
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* of the DebugFS hierarchy. MIPS-specific DebugFS entires should be
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* of the DebugFS hierarchy. MIPS-specific DebugFS entries should be
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* placed beneath this directory.
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*/
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extern struct dentry *mips_debugfs_dir;
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@ -179,7 +179,7 @@ void iounmap(const volatile void __iomem *addr);
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked cachable by
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* This version of ioremap ensures that the memory is marked cacheable by
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* the CPU. Also enables full write-combining. Useful for some
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* memory-like regions on I/O busses.
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*/
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@ -197,7 +197,7 @@ void iounmap(const volatile void __iomem *addr);
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* This version of ioremap ensures that the memory is marked uncacheable
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* but accelerated by means of write-combining feature. It is specifically
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* useful for PCIe prefetchable windows, which may vastly improve a
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* communications performance. If it was determined on boot stage, what
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@ -259,7 +259,7 @@ static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
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if (!chan)
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return;
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/*
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* set_dma_mode is only allowed to change endianess, direction,
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* set_dma_mode is only allowed to change endianness, direction,
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* transfer size, device FIFO width, and coherency settings.
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* Make sure anything else is masked off.
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*/
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@ -435,7 +435,7 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
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/**
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* alchemy_gpio2_enable - Activate GPIO2 block.
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*
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* The GPIO2 block must be enabled excplicitly to work. On systems
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* The GPIO2 block must be enabled explicitly to work. On systems
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* where this isn't done by the bootloader, this macro can be used.
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*/
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static inline void alchemy_gpio2_enable(void)
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@ -55,7 +55,7 @@ extern __iomem void *ltq_sys1_membase;
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#define ltq_sys1_w32_mask(clear, set, reg) \
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ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
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/* allow the gpio and pinctrl drivers to talk to eachother */
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/* allow the gpio and pinctrl drivers to talk to each other */
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extern int pinctrl_falcon_get_range_size(int id);
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extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
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@ -42,7 +42,7 @@ struct loongson_fan_policy {
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/* period between two check. (Unit: S) */
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u8 adjust_period;
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/* fan adjust usually depend on a temprature input */
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/* fan adjust usually depend on a temperature input */
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get_temp_fun depend_temp;
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/* up_step/down_step used when type is STEP_SPEED_POLICY */
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@ -227,7 +227,7 @@ static inline void csr_writeq(u64 val, u32 reg)
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#define LOONGSON_CSR_NODECNT 0x408
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#define LOONGSON_CSR_CPUTEMP 0x428
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/* PerCore CSR, only accessable by local cores */
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/* PerCore CSR, only accessible by local cores */
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#define LOONGSON_CSR_IPI_STATUS 0x1000
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#define LOONGSON_CSR_IPI_EN 0x1004
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#define LOONGSON_CSR_IPI_SET 0x1008
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@ -23,13 +23,13 @@
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* The kernel is still located in 0x80000000(kseg0). However,
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* the physical mask has been shifted to 0x80000000 which exploits the alias
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* on the Malta board. As a result of which, we override the __pa_symbol
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* to peform direct mapping from virtual to physical addresses. In other
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* to perform direct mapping from virtual to physical addresses. In other
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* words, the 0x80000000 virtual address maps to 0x80000000 physical address
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* which in turn aliases to 0x0. We do this in order to be able to use a flat
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* 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
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* 0x10000000 - 0x1fffffff.
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* The last 64KB of physical memory are reserved for correct HIGHMEM
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* macros arithmetics.
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* macros arithmetic.
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*
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*/
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@ -16,7 +16,7 @@
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*/
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/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
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/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
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/* This bonito64 version edited from bonito.h Revision 1.48 on 11/09/00 */
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#ifndef _ASM_MIPS_BOARDS_BONITO64_H
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#define _ASM_MIPS_BOARDS_BONITO64_H
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@ -22,7 +22,7 @@ extern void __iomem *mips_cpc_base;
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* the CPC
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*
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* Returns the default physical base address of the Cluster Power Controller
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* memory mapped registers. This is platform dependant & must therefore be
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* memory mapped registers. This is platform dependent & must therefore be
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* implemented per-platform.
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*/
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extern phys_addr_t mips_cpc_default_phys_base(void);
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@ -98,7 +98,7 @@
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/*
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* R4640/R4650 cp0 register names. These registers are listed
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* here only for completeness; without MMU these CPUs are not useable
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* here only for completeness; without MMU these CPUs are not usable
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* by Linux. A future ELKS port might take make Linux run on them
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* though ...
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*/
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@ -461,7 +461,7 @@
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#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
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#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
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#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
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#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
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#define EXCCODE_CACHEERR 30 /* Parity/ECC occurred on a core */
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/* Implementation specific trap codes used by MIPS cores */
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#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
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@ -114,7 +114,7 @@ struct cvmx_bootinfo {
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/*
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* flags indicating various configuration options. These
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* flags supercede the 'flags' variable and should be used
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* flags supersede the 'flags' variable and should be used
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* instead if available.
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*/
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uint32_t config_flags;
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@ -145,7 +145,7 @@ typedef struct {
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/**
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* This structure contains the global state of all command queues.
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* It is stored in a bootmem named block and shared by all
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* applications running on Octeon. Tickets are stored in a differnet
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* applications running on Octeon. Tickets are stored in a different
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* cache line that queue information to reduce the contention on the
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* ll/sc used to get a ticket. If this is not the case, the update
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* of queue state causes the ll/sc to fail quite often.
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@ -172,7 +172,7 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
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int pool_size);
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/**
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* Shutdown a queue a free it's command buffers to the FPA. The
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* Shutdown a queue and free its command buffers to the FPA. The
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* hardware connected to the queue must be stopped before this
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* function is called.
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*
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@ -194,7 +194,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
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/**
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* Return the command buffer to be written to. The purpose of this
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* function is to allow CVMX routine access t othe low level buffer
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* function is to allow CVMX routine access to the low level buffer
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* for initial hardware setup. User applications should not call this
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* function directly.
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*
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@ -91,7 +91,7 @@ typedef enum {
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} cvmx_pko_status_t;
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/**
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* This enumeration represents the differnet locking modes supported by PKO.
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* This enumeration represents the different locking modes supported by PKO.
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*/
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typedef enum {
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/*
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@ -1342,7 +1342,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
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* This function does NOT wait for previous tag switches to complete,
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* so the caller must ensure that there is not a pending tag switch.
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*
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* @wait: When set, call stalls until work becomes avaiable, or times out.
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* @wait: When set, call stalls until work becomes available, or times out.
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* If not set, returns immediately.
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*
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* Returns: the WQE pointer from POW. Returns NULL if no work
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@ -1376,7 +1376,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_
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* This function waits for any previous tag switch to complete before
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* requesting the new work.
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*
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* @wait: When set, call stalls until work becomes avaiable, or times out.
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* @wait: When set, call stalls until work becomes available, or times out.
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* If not set, returns immediately.
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*
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* Returns: the WQE pointer from POW. Returns NULL if no work
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@ -54,7 +54,7 @@
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#define OM_CHECK_SUBMODEL 0x02000000
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/* Match all models previous than the one specified */
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#define OM_MATCH_PREVIOUS_MODELS 0x04000000
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/* Ignores the minor revison on newer parts */
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/* Ignores the minor revision on newer parts */
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#define OM_IGNORE_MINOR_REVISION 0x08000000
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#define OM_FLAG_MASK 0xff000000
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@ -226,7 +226,7 @@
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#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
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/*
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* CN3XXX models with old revision enconding
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* CN3XXX models with old revision encoding
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*/
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#define OCTEON_CN38XX_PASS1 0x000d0000
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#define OCTEON_CN38XX_PASS2 0x000d0001
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@ -173,7 +173,7 @@ static inline unsigned long ___pa(unsigned long x)
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if (IS_ENABLED(CONFIG_64BIT)) {
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/*
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* For MIPS64 the virtual address may either be in one of
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* the compatibility segements ckseg0 or ckseg1, or it may
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* the compatibility segments ckseg0 or ckseg1, or it may
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* be in xkphys.
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*/
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return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
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@ -23,7 +23,7 @@
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#ifdef CONFIG_PCI_DRIVERS_LEGACY
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/*
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* Each pci channel is a top-level PCI bus seem by CPU. A machine with
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* Each PCI channel is a top-level PCI bus seem by CPU. A machine with
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* multiple PCI channels may have multiple PCI host controllers or a
|
||||
* single controller supporting multiple channels.
|
||||
*/
|
||||
|
||||
@ -201,7 +201,7 @@ enum pgtable_bits {
|
||||
* The final layouts of the PTE bits are:
|
||||
*
|
||||
* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
|
||||
* 32-bit, R1 or earler: CCC D V G M A W R P
|
||||
* 32-bit, R1 or earlier: CCC D V G M A W R P
|
||||
* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
|
||||
* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
|
||||
*/
|
||||
|
||||
@ -96,7 +96,7 @@ struct sgimc_regs {
|
||||
volatile u32 lbursttp; /* Time period for long bursts */
|
||||
|
||||
/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
|
||||
* be the same size. The size encoding for supported SIMMs is bellow */
|
||||
* be the same size. The size encoding for supported SIMMs is below */
|
||||
u32 _unused11[9];
|
||||
volatile u32 mconfig0; /* Memory config register zero */
|
||||
u32 _unused12;
|
||||
|
||||
@ -851,7 +851,7 @@ typedef union kldev_s { /* for device structure allocation */
|
||||
/*
|
||||
* TBD - Allocation issues.
|
||||
*
|
||||
* Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
|
||||
* Do we need to Mark off separate heaps for lboard_t, rboard_t, component,
|
||||
* errinfo and allocate from them, or have a single heap and allocate all
|
||||
* structures from it. Debug is easier in the former method since we can
|
||||
* dump all similar structs in one command, but there will be lots of holes,
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
*
|
||||
* Ordering barriers can be more efficient than completion barriers, since:
|
||||
*
|
||||
* a) Ordering barriers only require memory access instructions which preceed
|
||||
* a) Ordering barriers only require memory access instructions which precede
|
||||
* them in program order (older instructions) to reach a point in the
|
||||
* load/store datapath beyond which reordering is not possible before
|
||||
* allowing memory access instructions which follow them (younger
|
||||
|
||||
@ -27,7 +27,7 @@ struct thread_info {
|
||||
unsigned long flags; /* low level flags */
|
||||
unsigned long tp_value; /* thread pointer */
|
||||
__u32 cpu; /* current CPU */
|
||||
int preempt_count; /* 0 => preemptable, <0 => BUG */
|
||||
int preempt_count; /* 0 => preemptible, <0 => BUG */
|
||||
struct pt_regs *regs;
|
||||
long syscall; /* syscall number */
|
||||
};
|
||||
|
||||
@ -46,7 +46,7 @@ typedef unsigned int cycles_t;
|
||||
*
|
||||
* There is a suggested workaround and also the erratum can't strike if
|
||||
* the compare interrupt isn't being used as the clock source device.
|
||||
* However for now the implementaton of this function doesn't get these
|
||||
* However for now the implementation of this function doesn't get these
|
||||
* fine details right.
|
||||
*/
|
||||
static inline int can_use_mips_counter(unsigned int prid)
|
||||
|
||||
@ -32,7 +32,7 @@ static inline unsigned long get_vdso_base(void)
|
||||
#else
|
||||
/*
|
||||
* Get the base load address of the VDSO. We have to avoid generating
|
||||
* relocations and references to the GOT because ld.so does not peform
|
||||
* relocations and references to the GOT because ld.so does not perform
|
||||
* relocations on the VDSO. We use the current offset from the VDSO base
|
||||
* and perform a PC-relative branch which gives the absolute address in
|
||||
* ra, and take the difference. The assembler chokes on
|
||||
|
||||
@ -88,7 +88,7 @@
|
||||
#define MADV_HUGEPAGE 14 /* Worth backing with hugepages */
|
||||
#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */
|
||||
|
||||
#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump,
|
||||
#define MADV_DONTDUMP 16 /* Explicitly exclude from core dump,
|
||||
overrides the coredump filter bits */
|
||||
#define MADV_DODUMP 17 /* Clear the MADV_NODUMP flag */
|
||||
|
||||
|
||||
@ -62,7 +62,7 @@ struct msqid64_ds {
|
||||
unsigned long __unused5;
|
||||
};
|
||||
#else
|
||||
#warning no endianess set
|
||||
#warning no endianness set
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_MSGBUF_H */
|
||||
|
||||
@ -1139,7 +1139,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
* This processor doesn't have an MMU, so it's not
|
||||
* "real easy" to run Linux on it. It is left purely
|
||||
* for documentation. Commented out because it shares
|
||||
* it's c0_prid id number with the TX3900.
|
||||
* its c0_prid id number with the TX3900.
|
||||
*/
|
||||
c->cputype = CPU_R4650;
|
||||
__cpu_name[cpu] = "R4650";
|
||||
|
||||
@ -55,7 +55,7 @@ NOKPROBE_SYMBOL(insn_has_delayslot);
|
||||
* one; putting breakpoint on top of atomic ll/sc pair is bad idea;
|
||||
* so we need to prevent it and refuse kprobes insertion for such
|
||||
* instructions; cannot do much about breakpoint in the middle of
|
||||
* ll/sc pair; it is upto user to avoid those places
|
||||
* ll/sc pair; it is up to user to avoid those places
|
||||
*/
|
||||
static int insn_has_ll_or_sc(union mips_instruction insn)
|
||||
{
|
||||
|
||||
@ -380,7 +380,7 @@ void *__init relocate_kernel(void)
|
||||
}
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
||||
/* Copy the kernel to it's new location */
|
||||
/* Copy the kernel to its new location */
|
||||
memcpy(loc_new, &_text, kernel_length);
|
||||
|
||||
/* Perform relocations on the new kernel */
|
||||
|
||||
@ -70,7 +70,7 @@ copy_word:
|
||||
done:
|
||||
#ifdef CONFIG_SMP
|
||||
/* kexec_flag reset is signal to other CPUs what kernel
|
||||
was moved to it's location. Note - we need relocated address
|
||||
was moved to its location. Note - we need relocated address
|
||||
of kexec_flag. */
|
||||
|
||||
bal 1f
|
||||
|
||||
@ -146,7 +146,7 @@ static unsigned long __init init_initrd(void)
|
||||
/*
|
||||
* Board specific code or command line parser should have
|
||||
* already set up initrd_start and initrd_end. In these cases
|
||||
* perfom sanity checks and use them if all looks good.
|
||||
* perform sanity checks and use them if all looks good.
|
||||
*/
|
||||
if (!initrd_start || initrd_end <= initrd_start)
|
||||
goto disable;
|
||||
|
||||
@ -569,7 +569,7 @@ void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
|
||||
return (void __user __force *)(-1UL);
|
||||
|
||||
/*
|
||||
* FPU emulator may have it's own trampoline active just
|
||||
* FPU emulator may have its own trampoline active just
|
||||
* above the user stack, 16-bytes before the next lowest
|
||||
* 16 byte boundary. Try to avoid trashing it.
|
||||
*/
|
||||
|
||||
@ -2381,7 +2381,7 @@ void __init trap_init(void)
|
||||
set_except_vector(i, handle_reserved);
|
||||
|
||||
/*
|
||||
* Copy the EJTAG debug exception vector handler code to it's final
|
||||
* Copy the EJTAG debug exception vector handler code to its final
|
||||
* destination.
|
||||
*/
|
||||
if (cpu_has_ejtag && board_ejtag_handler_setup)
|
||||
|
||||
@ -6,9 +6,9 @@
|
||||
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 Imagination Technologies Ltd.
|
||||
*
|
||||
* VPE spport module for loading a MIPS SP program into VPE1. The SP
|
||||
* VPE support module for loading a MIPS SP program into VPE1. The SP
|
||||
* environment is rather simple since there are no TLBs. It needs
|
||||
* to be relocatable (or partiall linked). Initialize your stack in
|
||||
* to be relocatable (or partially linked). Initialize your stack in
|
||||
* the startup-code. The loader looks for the symbol __start and sets
|
||||
* up the execution to resume from there. To load and run, simply do
|
||||
* a cat SP 'binary' to the /dev/vpe1 device.
|
||||
|
||||
@ -531,7 +531,7 @@ static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
|
||||
* to be used for a period of time, but the exact ktime corresponding to the
|
||||
* final Count that must be restored is not known.
|
||||
*
|
||||
* It is gauranteed that a timer interrupt immediately after restore will be
|
||||
* It is guaranteed that a timer interrupt immediately after restore will be
|
||||
* handled, but not if CP0_Compare is exactly at @count. That case should
|
||||
* already be handled when the hardware timer state is saved.
|
||||
*
|
||||
|
||||
@ -17,7 +17,7 @@ static int __init loongson2_cpufreq_init(void)
|
||||
{
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
|
||||
/* Only 2F revision and it's successors support CPUFreq */
|
||||
/* Only 2F revision and its successors support CPUFreq */
|
||||
if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
|
||||
return platform_device_register(&loongson2_cpufreq_device);
|
||||
|
||||
|
||||
@ -516,7 +516,7 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus)
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the PC, SP, and GP of a secondary processor and start it runing!
|
||||
* Setup the PC, SP, and GP of a secondary processor and start it running!
|
||||
*/
|
||||
static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
|
||||
{
|
||||
|
||||
@ -1654,7 +1654,7 @@ static void coherency_setup(void)
|
||||
|
||||
/*
|
||||
* c0_status.cu=0 specifies that updates by the sc instruction use
|
||||
* the coherency mode specified by the TLB; 1 means cachable
|
||||
* the coherency mode specified by the TLB; 1 means cacheable
|
||||
* coherent update on write will be used. Not all processors have
|
||||
* this bit and; some wire it to zero, others like Toshiba had the
|
||||
* silly idea of putting something else there ...
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
* This is a very bad place to be. Our cache error
|
||||
* detection has triggered. If we have write-back data
|
||||
* in the cache, we may not be able to recover. As a
|
||||
* first-order desperate measure, turn off KSEG0 cacheing.
|
||||
* first-order desperate measure, turn off KSEG0 caching.
|
||||
*/
|
||||
mfc0 k0,CP0_CONFIG
|
||||
li k1,~CONF_CM_CMASK
|
||||
|
||||
@ -183,7 +183,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
|
||||
int idx, pid;
|
||||
|
||||
/*
|
||||
* Handle debugger faulting in for debugee.
|
||||
* Handle debugger faulting in for debuggee.
|
||||
*/
|
||||
if (current->active_mm != vma->vm_mm)
|
||||
return;
|
||||
|
||||
@ -301,7 +301,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
||||
int idx, pid;
|
||||
|
||||
/*
|
||||
* Handle debugger faulting in for debugee.
|
||||
* Handle debugger faulting in for debuggee.
|
||||
*/
|
||||
if (current->active_mm != vma->vm_mm)
|
||||
return;
|
||||
|
||||
@ -789,7 +789,7 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
|
||||
|
||||
if (check_for_high_segbits) {
|
||||
/*
|
||||
* The kernel currently implicitely assumes that the
|
||||
* The kernel currently implicitly assumes that the
|
||||
* MIPS SEGBITS parameter for the processor is
|
||||
* (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
|
||||
* allocate virtual addresses outside the maximum
|
||||
@ -1715,7 +1715,7 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
|
||||
/*
|
||||
* Check if PTE is present, if not then jump to LABEL. PTR points to
|
||||
* the page table where this PTE is located, PTE will be re-loaded
|
||||
* with it's original value.
|
||||
* with its original value.
|
||||
*/
|
||||
static void
|
||||
build_pte_present(u32 **p, struct uasm_reloc **r,
|
||||
|
||||
@ -95,7 +95,7 @@
|
||||
/*
|
||||
* Mapping of 64-bit eBPF registers to 32-bit native MIPS registers.
|
||||
*
|
||||
* 1) Native register pairs are ordered according to CPU endiannes, following
|
||||
* 1) Native register pairs are ordered according to CPU endianness, following
|
||||
* the MIPS convention for passing 64-bit arguments and return values.
|
||||
* 2) The eBPF return value, arguments and callee-saved registers are mapped
|
||||
* to their native MIPS equivalents.
|
||||
|
||||
@ -49,7 +49,7 @@ static int loongson_pcibios_config_access(unsigned char access_type,
|
||||
*/
|
||||
#ifdef CONFIG_CS5536
|
||||
/* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
|
||||
* access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
|
||||
* access the registers PCI_MSR_ADDR, PCI_MSR_DATA_LO,
|
||||
* PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
|
||||
* will not go this branch, but the others. so, no calling dead
|
||||
* loop here.
|
||||
|
||||
@ -453,7 +453,7 @@ static int alchemy_pci_probe(struct platform_device *pdev)
|
||||
|
||||
/* we can't ioremap the entire pci config space because it's too large,
|
||||
* nor can we dynamically ioremap it because some drivers use the
|
||||
* PCI config routines from within atomic contex and that becomes a
|
||||
* PCI config routines from within atomic context and that becomes a
|
||||
* problem in get_vm_area(). Instead we use one wired TLB entry to
|
||||
* handle all config accesses for all busses.
|
||||
*/
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
* the CFG_SEL bit in the PCI_MISC_CONFIG register.
|
||||
*
|
||||
* Devices on the bus can perform DMA requests via chip BAR1. PCI host
|
||||
* controller BARs are programmend as if an external device is programmed.
|
||||
* controller BARs are programmed as if an external device is programmed.
|
||||
* Which means that during configuration, IDSEL pin of the chip should be
|
||||
* asserted.
|
||||
*
|
||||
|
||||
@ -152,7 +152,7 @@ static int ltq_pci_startup(struct platform_device *pdev)
|
||||
temp_buffer &= ~0xf0000;
|
||||
/* enable internal arbiter */
|
||||
temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
|
||||
/* enable internal PCI master reqest */
|
||||
/* enable internal PCI master request */
|
||||
temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
|
||||
|
||||
/* enable EBU request */
|
||||
|
||||
@ -376,7 +376,7 @@ static void octeon_pci_initialize(void)
|
||||
ctl_status.s.timer = 1;
|
||||
cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
|
||||
|
||||
/* Deassert PCI reset and advertize PCX Host Mode Device Capability
|
||||
/* Deassert PCI reset and advertise PCX Host Mode Device Capability
|
||||
(64b) */
|
||||
cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
|
||||
cvmx_read_csr(CVMX_CIU_SOFT_PRST);
|
||||
|
||||
@ -114,7 +114,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
|
||||
*
|
||||
* The function is complicated by the ultimate brokenness of the IOC3 chip
|
||||
* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
|
||||
* accesses and does only decode parts of it's address space.
|
||||
* accesses and does only decode parts of its address space.
|
||||
*/
|
||||
static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *value)
|
||||
|
||||
@ -1037,7 +1037,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
|
||||
in_fif_p_count = dbg_data.s.data & 0xff;
|
||||
} while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
|
||||
|
||||
/* Update in_fif_p_count for it's offset with respect to out_p_count */
|
||||
/* Update in_fif_p_count for its offset with respect to out_p_count */
|
||||
in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
|
||||
|
||||
/* Read the OUT_P_COUNT from the debug select */
|
||||
|
||||
@ -175,7 +175,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
|
||||
* mips_cm_probe() wipes out bootloader
|
||||
* config for CM regions and we have to configure them
|
||||
* again. This SoC cannot talk to pamlbus devices
|
||||
* witout proper iocu region set up.
|
||||
* without proper iocu region set up.
|
||||
*
|
||||
* FIXME: it would be better to do this with values
|
||||
* from DT, but we need this very early because
|
||||
|
||||
@ -348,7 +348,7 @@ static void final_fixup(struct pci_dev *dev)
|
||||
unsigned char bist;
|
||||
int ret;
|
||||
|
||||
/* Do build-in self test */
|
||||
/* Do built-in self test */
|
||||
ret = pci_read_config_byte(dev, PCI_BIST, &bist);
|
||||
if ((ret != PCIBIOS_SUCCESSFUL) || !(bist & PCI_BIST_CAPABLE))
|
||||
return;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user