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drm/amd/pm: enable MP0 DPM for sienna_cichlid
Enable MP0 clock DPM for sienna_cichlid. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -68,7 +68,8 @@
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FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
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FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
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FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
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FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
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FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
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FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
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#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
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@ -229,6 +230,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
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| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
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| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
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| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
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| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
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| FEATURE_MASK(FEATURE_DS_FCLK_BIT)
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