mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2024-12-28 16:53:49 +00:00
Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next
- Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
This commit is contained in:
Stephen Boyd
commit
3462100cf3
282
Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml
Normal file
282
Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml
Normal file
@ -0,0 +1,282 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8 Audio Clock Mux
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
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description: |
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NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
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used to control Audio related clock on the SoC.
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properties:
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compatible:
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enum:
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- fsl,imx8dxl-acm
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- fsl,imx8qm-acm
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- fsl,imx8qxp-acm
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reg:
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maxItems: 1
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||||
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power-domains:
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minItems: 13
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maxItems: 21
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||||
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
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for the full list of i.MX8 ACM clock IDs.
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clocks:
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minItems: 13
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maxItems: 27
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clock-names:
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minItems: 13
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maxItems: 27
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required:
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- compatible
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- reg
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- power-domains
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- '#clock-cells'
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 18
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maxItems: 18
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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|
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_ESAI_1
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SAI_6
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- description: power domain of IMX_SC_R_SAI_7
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_SPDIF_1
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- description: power domain of IMX_SC_R_MQS_0
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|
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clocks:
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minItems: 27
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maxItems: 27
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: mlb_clk
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- const: hdmi_rx_mclk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: esai1_rx_clk
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- const: esai1_rx_hf_clk
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- const: esai1_tx_clk
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- const: esai1_tx_hf_clk
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- const: spdif0_rx
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- const: spdif1_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- const: sai5_tx_bclk
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- const: sai6_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8dxl-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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additionalProperties: false
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examples:
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# Clock Control Module node:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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clock-controller@59e00000 {
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compatible = "fsl,imx8qxp-acm";
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reg = <0x59e00000 0x1d0000>;
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#clock-cells = <1>;
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power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
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<&pd IMX_SC_R_AUDIO_CLK_1>,
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<&pd IMX_SC_R_MCLK_OUT_0>,
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<&pd IMX_SC_R_MCLK_OUT_1>,
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<&pd IMX_SC_R_AUDIO_PLL_0>,
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<&pd IMX_SC_R_AUDIO_PLL_1>,
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<&pd IMX_SC_R_ASRC_0>,
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<&pd IMX_SC_R_ASRC_1>,
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<&pd IMX_SC_R_ESAI_0>,
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<&pd IMX_SC_R_SAI_0>,
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<&pd IMX_SC_R_SAI_1>,
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<&pd IMX_SC_R_SAI_2>,
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<&pd IMX_SC_R_SAI_3>,
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<&pd IMX_SC_R_SAI_4>,
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<&pd IMX_SC_R_SAI_5>,
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<&pd IMX_SC_R_SPDIF_0>,
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<&pd IMX_SC_R_MQS_0>;
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clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
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<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
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<&clk_ext_aud_mclk0>,
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<&clk_ext_aud_mclk1>,
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<&clk_esai0_rx_clk>,
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<&clk_esai0_rx_hf_clk>,
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<&clk_esai0_tx_clk>,
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<&clk_esai0_tx_hf_clk>,
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<&clk_spdif0_rx>,
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<&clk_sai0_rx_bclk>,
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<&clk_sai0_tx_bclk>,
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<&clk_sai1_rx_bclk>,
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<&clk_sai1_tx_bclk>,
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<&clk_sai2_rx_bclk>,
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<&clk_sai3_rx_bclk>,
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<&clk_sai4_rx_bclk>;
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clock-names = "aud_rec_clk0_lpcg_clk",
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"aud_rec_clk1_lpcg_clk",
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"ext_aud_mclk0",
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"ext_aud_mclk1",
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"esai0_rx_clk",
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"esai0_rx_hf_clk",
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"esai0_tx_clk",
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"esai0_tx_hf_clk",
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"spdif0_rx",
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"sai0_rx_bclk",
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"sai0_tx_bclk",
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"sai1_rx_bclk",
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"sai1_tx_bclk",
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"sai2_rx_bclk",
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"sai3_rx_bclk",
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"sai4_rx_bclk";
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};
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@ -701,6 +701,7 @@ static void __init aspeed_cc_init(struct device_node *np)
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GFP_KERNEL);
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if (!aspeed_clk_data)
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return;
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aspeed_clk_data->num = ASPEED_NUM_CLKS;
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||||
/*
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* This way all clocks fetched before the platform device probes,
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@ -732,8 +733,6 @@ static void __init aspeed_cc_init(struct device_node *np)
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aspeed_ast2500_cc(map);
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else
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pr_err("unknown platform, failed to add clocks\n");
|
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aspeed_clk_data->num = ASPEED_NUM_CLKS;
|
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
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if (ret)
|
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pr_err("failed to add DT provider: %d\n", ret);
|
||||
|
||||
@ -839,6 +839,7 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
|
||||
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
|
||||
if (!aspeed_g6_clk_data)
|
||||
return;
|
||||
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
|
||||
|
||||
/*
|
||||
* This way all clocks fetched before the platform device probes,
|
||||
@ -860,7 +861,6 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
|
||||
}
|
||||
|
||||
aspeed_g6_cc(map);
|
||||
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
|
||||
if (ret)
|
||||
pr_err("failed to add DT provider: %d\n", ret);
|
||||
|
||||
@ -402,6 +402,7 @@ static void __init gemini_cc_init(struct device_node *np)
|
||||
GFP_KERNEL);
|
||||
if (!gemini_clk_data)
|
||||
return;
|
||||
gemini_clk_data->num = GEMINI_NUM_CLKS;
|
||||
|
||||
/*
|
||||
* This way all clock fetched before the platform device probes,
|
||||
@ -455,7 +456,6 @@ static void __init gemini_cc_init(struct device_node *np)
|
||||
gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
|
||||
|
||||
/* Register the clocks to be accessed by the device tree */
|
||||
gemini_clk_data->num = GEMINI_NUM_CLKS;
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
|
||||
|
||||
@ -134,6 +134,11 @@
|
||||
/* 0x14b - 0x152 Holdover */
|
||||
|
||||
/* 0x153 - 0x15f PLL1 Configuration */
|
||||
#define LMK04832_REG_PLL1_LD 0x15f
|
||||
#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)
|
||||
#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07
|
||||
#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)
|
||||
#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03
|
||||
|
||||
/* 0x160 - 0x16e PLL2 Configuration */
|
||||
#define LMK04832_REG_PLL2_R_MSB 0x160
|
||||
@ -206,6 +211,7 @@ enum lmk04832_rdbk_type {
|
||||
RDBK_CLKIN_SEL0,
|
||||
RDBK_CLKIN_SEL1,
|
||||
RDBK_RESET,
|
||||
RDBK_PLL1_LD,
|
||||
};
|
||||
|
||||
struct lmk_dclk {
|
||||
@ -1297,6 +1303,7 @@ static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
|
||||
sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
|
||||
init.name = dclk_name;
|
||||
parent_names[0] = clk_hw_get_name(&lmk->vco);
|
||||
init.parent_names = parent_names;
|
||||
init.ops = &lmk04832_dclk_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.num_parents = 1;
|
||||
@ -1345,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
|
||||
{
|
||||
int reg;
|
||||
int ret;
|
||||
int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
|
||||
LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
|
||||
FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
|
||||
LMK04832_VAL_CLKIN_SEL_TYPE_OUT);
|
||||
|
||||
dev_info(lmk->dev, "setting up 4-wire mode\n");
|
||||
ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
|
||||
@ -1362,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
|
||||
case RDBK_RESET:
|
||||
reg = LMK04832_REG_CLKIN_RST;
|
||||
break;
|
||||
case RDBK_PLL1_LD:
|
||||
reg = LMK04832_REG_PLL1_LD;
|
||||
val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,
|
||||
LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |
|
||||
FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,
|
||||
LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return regmap_write(lmk->regmap, reg,
|
||||
FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
|
||||
LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
|
||||
FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
|
||||
LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
|
||||
return regmap_write(lmk->regmap, reg, val);
|
||||
}
|
||||
|
||||
static int lmk04832_probe(struct spi_device *spi)
|
||||
@ -1504,21 +1518,21 @@ static int lmk04832_probe(struct spi_device *spi)
|
||||
ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to set VCO rate\n");
|
||||
goto err_disable_vco;
|
||||
goto err_disable_oscin;
|
||||
}
|
||||
}
|
||||
|
||||
ret = lmk04832_register_sclk(lmk);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
|
||||
goto err_disable_vco;
|
||||
goto err_disable_oscin;
|
||||
}
|
||||
|
||||
for (i = 0; i < info->num_channels; i++) {
|
||||
ret = lmk04832_register_clkout(lmk, i);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to register clk %d\n", i);
|
||||
goto err_disable_vco;
|
||||
goto err_disable_oscin;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1527,16 +1541,13 @@ static int lmk04832_probe(struct spi_device *spi)
|
||||
lmk->clk_data);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
|
||||
goto err_disable_vco;
|
||||
goto err_disable_oscin;
|
||||
}
|
||||
|
||||
spi_set_drvdata(spi, lmk);
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_vco:
|
||||
clk_disable_unprepare(lmk->vco.clk);
|
||||
|
||||
err_disable_oscin:
|
||||
clk_disable_unprepare(lmk->oscin);
|
||||
|
||||
|
||||
@ -618,6 +618,7 @@ static void __init m10v_cc_init(struct device_node *np)
|
||||
|
||||
if (!m10v_clk_data)
|
||||
return;
|
||||
m10v_clk_data->num = M10V_NUM_CLKS;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
@ -654,8 +655,6 @@ static void __init m10v_cc_init(struct device_node *np)
|
||||
base + CLKSEL(1), 0, 3, 0, rclk_table,
|
||||
&m10v_crglock, NULL);
|
||||
m10v_clk_data->hws[M10V_RCLK_ID] = hw;
|
||||
|
||||
m10v_clk_data->num = M10V_NUM_CLKS;
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);
|
||||
|
||||
@ -621,6 +621,7 @@ static int sp7021_clk_probe(struct platform_device *pdev)
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
clk_data->num = CLK_MAX;
|
||||
|
||||
hws = clk_data->hws;
|
||||
pd_ext.index = 0;
|
||||
@ -688,8 +689,6 @@ static int sp7021_clk_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(hws[i]);
|
||||
}
|
||||
|
||||
clk_data->num = CLK_MAX;
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
|
||||
@ -32,11 +32,12 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
|
||||
|
||||
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
|
||||
|
||||
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
|
||||
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
|
||||
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
|
||||
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \
|
||||
clk-imx8dxl-rsrc.o
|
||||
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
|
||||
clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o
|
||||
|
||||
obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o
|
||||
|
||||
|
||||
@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
|
||||
int prediv_value;
|
||||
int div_value;
|
||||
int ret;
|
||||
u32 val;
|
||||
u32 orig, val;
|
||||
|
||||
ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
|
||||
&prediv_value, &div_value);
|
||||
@ -106,13 +106,15 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
|
||||
|
||||
spin_lock_irqsave(divider->lock, flags);
|
||||
|
||||
val = readl(divider->reg);
|
||||
val &= ~((clk_div_mask(divider->width) << divider->shift) |
|
||||
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
|
||||
orig = readl(divider->reg);
|
||||
val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
|
||||
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
|
||||
|
||||
val |= (u32)(prediv_value - 1) << divider->shift;
|
||||
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
|
||||
writel(val, divider->reg);
|
||||
|
||||
if (val != orig)
|
||||
writel(val, divider->reg);
|
||||
|
||||
spin_unlock_irqrestore(divider->lock, flags);
|
||||
|
||||
|
||||
@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
|
||||
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
|
||||
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
|
||||
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
|
||||
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
|
||||
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
|
||||
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
|
||||
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
|
||||
|
||||
@ -65,16 +65,10 @@ static int imx_clk_gpr_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val);
|
||||
}
|
||||
|
||||
static int imx_clk_gpr_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return clk_mux_determine_rate_flags(hw, req, 0);
|
||||
}
|
||||
|
||||
static const struct clk_ops imx_clk_gpr_mux_ops = {
|
||||
.get_parent = imx_clk_gpr_mux_get_parent,
|
||||
.set_parent = imx_clk_gpr_mux_set_parent,
|
||||
.determine_rate = imx_clk_gpr_mux_determine_rate,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
};
|
||||
|
||||
struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <soc/imx/revision.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
@ -73,7 +74,7 @@ enum mx25_clks {
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
static int __init __mx25_clocks_init(void __iomem *ccm_base)
|
||||
static void __init __mx25_clocks_init(void __iomem *ccm_base)
|
||||
{
|
||||
BUG_ON(!ccm_base);
|
||||
|
||||
@ -220,7 +221,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
|
||||
|
||||
imx_register_uart_clocks();
|
||||
|
||||
return 0;
|
||||
imx_print_silicon_rev("i.MX25", mx25_revision());
|
||||
}
|
||||
|
||||
static void __init mx25_clocks_init_dt(struct device_node *np)
|
||||
|
||||
476
drivers/clk/imx/clk-imx8-acm.c
Normal file
476
drivers/clk/imx/clk-imx8-acm.c
Normal file
@ -0,0 +1,476 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Copyright 2023 NXP
|
||||
//
|
||||
|
||||
#include <dt-bindings/clock/imx8-clock.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
/**
|
||||
* struct clk_imx_acm_pm_domains - structure for multi power domain
|
||||
* @pd_dev: power domain device
|
||||
* @pd_dev_link: power domain device link
|
||||
* @num_domains: power domain nummber
|
||||
*/
|
||||
struct clk_imx_acm_pm_domains {
|
||||
struct device **pd_dev;
|
||||
struct device_link **pd_dev_link;
|
||||
int num_domains;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_imx8_acm_sel - for clock mux
|
||||
* @name: clock name
|
||||
* @clkid: clock id
|
||||
* @parents: clock parents
|
||||
* @num_parents: clock parents number
|
||||
* @reg: register offset
|
||||
* @shift: bit shift in register
|
||||
* @width: bits width
|
||||
*/
|
||||
struct clk_imx8_acm_sel {
|
||||
const char *name;
|
||||
int clkid;
|
||||
const struct clk_parent_data *parents; /* For mux */
|
||||
int num_parents;
|
||||
u32 reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct imx8_acm_soc_data - soc specific data
|
||||
* @sels: pointer to struct clk_imx8_acm_sel
|
||||
* @num_sels: numbers of items
|
||||
*/
|
||||
struct imx8_acm_soc_data {
|
||||
struct clk_imx8_acm_sel *sels;
|
||||
unsigned int num_sels;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct imx8_acm_priv - private structure
|
||||
* @dev_pm: multi power domain
|
||||
* @soc_data: pointer to soc data
|
||||
* @reg: base address of registers
|
||||
* @regs: save registers for suspend
|
||||
*/
|
||||
struct imx8_acm_priv {
|
||||
struct clk_imx_acm_pm_domains dev_pm;
|
||||
const struct imx8_acm_soc_data *soc_data;
|
||||
void __iomem *reg;
|
||||
u32 regs[IMX_ADMA_ACM_CLK_END];
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
|
||||
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
|
||||
{ .fw_name = "mlb_clk" },
|
||||
{ .fw_name = "hdmi_rx_mclk" },
|
||||
{ .fw_name = "ext_aud_mclk0" },
|
||||
{ .fw_name = "ext_aud_mclk1" },
|
||||
{ .fw_name = "esai0_rx_clk" },
|
||||
{ .fw_name = "esai0_rx_hf_clk" },
|
||||
{ .fw_name = "esai0_tx_clk" },
|
||||
{ .fw_name = "esai0_tx_hf_clk" },
|
||||
{ .fw_name = "esai1_rx_clk" },
|
||||
{ .fw_name = "esai1_rx_hf_clk" },
|
||||
{ .fw_name = "esai1_tx_clk" },
|
||||
{ .fw_name = "esai1_tx_hf_clk" },
|
||||
{ .fw_name = "spdif0_rx" },
|
||||
{ .fw_name = "spdif1_rx" },
|
||||
{ .fw_name = "sai0_rx_bclk" },
|
||||
{ .fw_name = "sai0_tx_bclk" },
|
||||
{ .fw_name = "sai1_rx_bclk" },
|
||||
{ .fw_name = "sai1_tx_bclk" },
|
||||
{ .fw_name = "sai2_rx_bclk" },
|
||||
{ .fw_name = "sai3_rx_bclk" },
|
||||
{ .fw_name = "sai4_rx_bclk" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
|
||||
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
|
||||
{ .fw_name = "mlb_clk" },
|
||||
{ .fw_name = "hdmi_rx_mclk" },
|
||||
{ .fw_name = "spdif0_rx" },
|
||||
{ .fw_name = "spdif1_rx" },
|
||||
{ .fw_name = "sai4_rx_bclk" },
|
||||
{ .fw_name = "sai6_rx_bclk" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qm_mclk_sels[] = {
|
||||
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
|
||||
{ .fw_name = "acm_aud_clk0_sel" },
|
||||
{ .fw_name = "acm_aud_clk1_sel" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
|
||||
{ .fw_name = "sai4_rx_bclk" },
|
||||
{ .fw_name = "sai5_tx_bclk" },
|
||||
{ .index = -1 },
|
||||
{ .fw_name = "mlb_clk" },
|
||||
|
||||
};
|
||||
|
||||
static struct clk_imx8_acm_sel imx8qm_sels[] = {
|
||||
{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 },
|
||||
{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 },
|
||||
{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 },
|
||||
{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 },
|
||||
{ "acm_asrc0_mclk_sel", IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 },
|
||||
{ "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 },
|
||||
{ "acm_esai1_mclk_sel", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 },
|
||||
{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 },
|
||||
{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 },
|
||||
{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 },
|
||||
{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x110000, 0, 2 },
|
||||
{ "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x120000, 0, 2 },
|
||||
{ "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x130000, 0, 2 },
|
||||
{ "acm_sai6_mclk_sel", IMX_ADMA_ACM_SAI6_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x140000, 0, 2 },
|
||||
{ "acm_sai7_mclk_sel", IMX_ADMA_ACM_SAI7_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x150000, 0, 2 },
|
||||
{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1A0000, 0, 2 },
|
||||
{ "acm_spdif1_mclk_sel", IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1B0000, 0, 2 },
|
||||
{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1C0000, 0, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qxp_aud_clk_sels[] = {
|
||||
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
|
||||
{ .fw_name = "ext_aud_mclk0" },
|
||||
{ .fw_name = "ext_aud_mclk1" },
|
||||
{ .fw_name = "esai0_rx_clk" },
|
||||
{ .fw_name = "esai0_rx_hf_clk" },
|
||||
{ .fw_name = "esai0_tx_clk" },
|
||||
{ .fw_name = "esai0_tx_hf_clk" },
|
||||
{ .fw_name = "spdif0_rx" },
|
||||
{ .fw_name = "sai0_rx_bclk" },
|
||||
{ .fw_name = "sai0_tx_bclk" },
|
||||
{ .fw_name = "sai1_rx_bclk" },
|
||||
{ .fw_name = "sai1_tx_bclk" },
|
||||
{ .fw_name = "sai2_rx_bclk" },
|
||||
{ .fw_name = "sai3_rx_bclk" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
|
||||
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .fw_name = "spdif0_rx" },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .fw_name = "sai4_rx_bclk" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8qxp_mclk_sels[] = {
|
||||
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
|
||||
{ .fw_name = "acm_aud_clk0_sel" },
|
||||
{ .fw_name = "acm_aud_clk1_sel" },
|
||||
};
|
||||
|
||||
static struct clk_imx8_acm_sel imx8qxp_sels[] = {
|
||||
{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x000000, 0, 5 },
|
||||
{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x010000, 0, 5 },
|
||||
{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x020000, 0, 3 },
|
||||
{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x030000, 0, 3 },
|
||||
{ "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x060000, 0, 2 },
|
||||
{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0E0000, 0, 2 },
|
||||
{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0F0000, 0, 2 },
|
||||
{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x100000, 0, 2 },
|
||||
{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x110000, 0, 2 },
|
||||
{ "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x140000, 0, 2 },
|
||||
{ "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x150000, 0, 2 },
|
||||
{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1A0000, 0, 2 },
|
||||
{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1C0000, 0, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8dxl_aud_clk_sels[] = {
|
||||
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
|
||||
{ .fw_name = "ext_aud_mclk0" },
|
||||
{ .fw_name = "ext_aud_mclk1" },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .fw_name = "spdif0_rx" },
|
||||
{ .fw_name = "sai0_rx_bclk" },
|
||||
{ .fw_name = "sai0_tx_bclk" },
|
||||
{ .fw_name = "sai1_rx_bclk" },
|
||||
{ .fw_name = "sai1_tx_bclk" },
|
||||
{ .fw_name = "sai2_rx_bclk" },
|
||||
{ .fw_name = "sai3_rx_bclk" },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
|
||||
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .fw_name = "spdif0_rx" },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
{ .index = -1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data imx8dxl_mclk_sels[] = {
|
||||
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
|
||||
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
|
||||
{ .fw_name = "acm_aud_clk0_sel" },
|
||||
{ .fw_name = "acm_aud_clk1_sel" },
|
||||
};
|
||||
|
||||
static struct clk_imx8_acm_sel imx8dxl_sels[] = {
|
||||
{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x000000, 0, 5 },
|
||||
{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x010000, 0, 5 },
|
||||
{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x020000, 0, 3 },
|
||||
{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x030000, 0, 3 },
|
||||
{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0E0000, 0, 2 },
|
||||
{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0F0000, 0, 2 },
|
||||
{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x100000, 0, 2 },
|
||||
{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x110000, 0, 2 },
|
||||
{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1A0000, 0, 2 },
|
||||
{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1C0000, 0, 2 },
|
||||
};
|
||||
|
||||
/**
|
||||
* clk_imx_acm_attach_pm_domains: attach multi power domains
|
||||
* @dev: device pointer
|
||||
* @dev_pm: power domains for device
|
||||
*/
|
||||
static int clk_imx_acm_attach_pm_domains(struct device *dev,
|
||||
struct clk_imx_acm_pm_domains *dev_pm)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
|
||||
"#power-domain-cells");
|
||||
if (dev_pm->num_domains <= 1)
|
||||
return 0;
|
||||
|
||||
dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains,
|
||||
sizeof(*dev_pm->pd_dev),
|
||||
GFP_KERNEL);
|
||||
if (!dev_pm->pd_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_pm->pd_dev_link = devm_kmalloc_array(dev,
|
||||
dev_pm->num_domains,
|
||||
sizeof(*dev_pm->pd_dev_link),
|
||||
GFP_KERNEL);
|
||||
if (!dev_pm->pd_dev_link)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < dev_pm->num_domains; i++) {
|
||||
dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
|
||||
if (IS_ERR(dev_pm->pd_dev[i]))
|
||||
return PTR_ERR(dev_pm->pd_dev[i]);
|
||||
|
||||
dev_pm->pd_dev_link[i] = device_link_add(dev,
|
||||
dev_pm->pd_dev[i],
|
||||
DL_FLAG_STATELESS |
|
||||
DL_FLAG_PM_RUNTIME |
|
||||
DL_FLAG_RPM_ACTIVE);
|
||||
if (IS_ERR(dev_pm->pd_dev_link[i])) {
|
||||
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
|
||||
ret = PTR_ERR(dev_pm->pd_dev_link[i]);
|
||||
goto detach_pm;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
detach_pm:
|
||||
while (--i >= 0) {
|
||||
device_link_del(dev_pm->pd_dev_link[i]);
|
||||
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* clk_imx_acm_detach_pm_domains: detach multi power domains
|
||||
* @dev: deivice pointer
|
||||
* @dev_pm: multi power domain for device
|
||||
*/
|
||||
static int clk_imx_acm_detach_pm_domains(struct device *dev,
|
||||
struct clk_imx_acm_pm_domains *dev_pm)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (dev_pm->num_domains <= 1)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < dev_pm->num_domains; i++) {
|
||||
device_link_del(dev_pm->pd_dev_link[i]);
|
||||
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx8_acm_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_hw_data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct clk_imx8_acm_sel *sels;
|
||||
struct imx8_acm_priv *priv;
|
||||
struct clk_hw **hws;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
base = devm_of_iomap(dev, dev->of_node, 0, NULL);
|
||||
if (WARN_ON(IS_ERR(base)))
|
||||
return PTR_ERR(base);
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->reg = base;
|
||||
priv->soc_data = of_device_get_match_data(dev);
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
clk_hw_data = devm_kzalloc(&pdev->dev, struct_size(clk_hw_data, hws, IMX_ADMA_ACM_CLK_END),
|
||||
GFP_KERNEL);
|
||||
if (!clk_hw_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_hw_data->num = IMX_ADMA_ACM_CLK_END;
|
||||
hws = clk_hw_data->hws;
|
||||
|
||||
ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
sels = priv->soc_data->sels;
|
||||
for (i = 0; i < priv->soc_data->num_sels; i++) {
|
||||
hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
|
||||
sels[i].name, sels[i].parents,
|
||||
sels[i].num_parents, 0,
|
||||
base + sels[i].reg,
|
||||
sels[i].shift, sels[i].width,
|
||||
0, NULL, NULL);
|
||||
if (IS_ERR(hws[sels[i].clkid])) {
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
goto err_clk_register;
|
||||
}
|
||||
}
|
||||
|
||||
imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to register hws for ACM\n");
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
||||
err_clk_register:
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int imx8_acm_clk_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct imx8_acm_soc_data imx8qm_acm_data = {
|
||||
.sels = imx8qm_sels,
|
||||
.num_sels = ARRAY_SIZE(imx8qm_sels),
|
||||
};
|
||||
|
||||
static const struct imx8_acm_soc_data imx8qxp_acm_data = {
|
||||
.sels = imx8qxp_sels,
|
||||
.num_sels = ARRAY_SIZE(imx8qxp_sels),
|
||||
};
|
||||
|
||||
static const struct imx8_acm_soc_data imx8dxl_acm_data = {
|
||||
.sels = imx8dxl_sels,
|
||||
.num_sels = ARRAY_SIZE(imx8dxl_sels),
|
||||
};
|
||||
|
||||
static const struct of_device_id imx8_acm_match[] = {
|
||||
{ .compatible = "fsl,imx8qm-acm", .data = &imx8qm_acm_data },
|
||||
{ .compatible = "fsl,imx8qxp-acm", .data = &imx8qxp_acm_data },
|
||||
{ .compatible = "fsl,imx8dxl-acm", .data = &imx8dxl_acm_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx8_acm_match);
|
||||
|
||||
static int __maybe_unused imx8_acm_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct imx8_acm_priv *priv = dev_get_drvdata(dev);
|
||||
struct clk_imx8_acm_sel *sels;
|
||||
int i;
|
||||
|
||||
sels = priv->soc_data->sels;
|
||||
|
||||
for (i = 0; i < priv->soc_data->num_sels; i++)
|
||||
priv->regs[i] = readl_relaxed(priv->reg + sels[i].reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused imx8_acm_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct imx8_acm_priv *priv = dev_get_drvdata(dev);
|
||||
struct clk_imx8_acm_sel *sels;
|
||||
int i;
|
||||
|
||||
sels = priv->soc_data->sels;
|
||||
|
||||
for (i = 0; i < priv->soc_data->num_sels; i++)
|
||||
writel_relaxed(priv->regs[i], priv->reg + sels[i].reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops imx8_acm_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(imx8_acm_runtime_suspend,
|
||||
imx8_acm_runtime_resume, NULL)
|
||||
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver imx8_acm_clk_driver = {
|
||||
.driver = {
|
||||
.name = "imx8-acm",
|
||||
.of_match_table = imx8_acm_match,
|
||||
.pm = &imx8_acm_pm_ops,
|
||||
},
|
||||
.probe = imx8_acm_clk_probe,
|
||||
.remove = imx8_acm_clk_remove,
|
||||
};
|
||||
module_platform_driver(imx8_acm_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
|
||||
MODULE_DESCRIPTION("Freescale i.MX8 Audio Clock Mux driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -178,10 +178,6 @@ static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "au
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext1", "clk_ext2", };
|
||||
|
||||
static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
@ -567,7 +563,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580);
|
||||
hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600);
|
||||
hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680);
|
||||
hws[IMX8MP_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700);
|
||||
hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780);
|
||||
hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800);
|
||||
hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880);
|
||||
|
||||
@ -181,7 +181,6 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
|
||||
unsigned int bit_offset[IMX_LPCG_MAX_CLKS];
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **clk_hws;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int count;
|
||||
int idx;
|
||||
@ -191,8 +190,7 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
|
||||
if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
|
||||
@ -167,7 +167,7 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
|
||||
clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
|
||||
clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
|
||||
|
||||
clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x500);
|
||||
clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500);
|
||||
clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600);
|
||||
clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6);
|
||||
|
||||
|
||||
@ -32,6 +32,7 @@ static u32 share_count_sai1;
|
||||
static u32 share_count_sai2;
|
||||
static u32 share_count_sai3;
|
||||
static u32 share_count_mub;
|
||||
static u32 share_count_pdm;
|
||||
|
||||
static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
|
||||
static const char *parent_names[MAX_SEL][4] = {
|
||||
@ -236,7 +237,8 @@ static const struct imx93_clk_ccgr {
|
||||
{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
|
||||
{ IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
|
||||
{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, },
|
||||
{ IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, },
|
||||
{ IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, 0, &share_count_pdm},
|
||||
{ IMX93_CLK_PDM_IPG, "pdm_ipg_clk", "bus_aon_root", 0x9ac0, 0, &share_count_pdm},
|
||||
{ IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
|
||||
{ IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
|
||||
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
|
||||
|
||||
@ -64,8 +64,6 @@ static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
struct imx_pll14xx_clk imx_1443x_pll = {
|
||||
@ -139,11 +137,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
|
||||
/*
|
||||
* Fractional PLL constrains:
|
||||
*
|
||||
* a) 6MHz <= prate <= 25MHz
|
||||
* b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz)
|
||||
* c) 64 <= m <= 1023
|
||||
* d) 0 <= s <= 6
|
||||
* e) -32768 <= k <= 32767
|
||||
* a) 1 <= p <= 63
|
||||
* b) 64 <= m <= 1023
|
||||
* c) 0 <= s <= 6
|
||||
* d) -32768 <= k <= 32767
|
||||
*
|
||||
* fvco = (m * 65536 + k) * prate / (p * 65536)
|
||||
*/
|
||||
@ -186,7 +183,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
|
||||
}
|
||||
|
||||
/* Finally calculate best values */
|
||||
for (pdiv = 1; pdiv <= 7; pdiv++) {
|
||||
for (pdiv = 1; pdiv <= 63; pdiv++) {
|
||||
for (sdiv = 0; sdiv <= 6; sdiv++) {
|
||||
/* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */
|
||||
mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
|
||||
|
||||
@ -44,11 +44,15 @@ struct clk_pllv4 {
|
||||
u32 cfg_offset;
|
||||
u32 num_offset;
|
||||
u32 denom_offset;
|
||||
bool use_mult_range;
|
||||
};
|
||||
|
||||
/* Valid PLL MULT Table */
|
||||
static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
|
||||
|
||||
/* Valid PLL MULT range, (max, min) */
|
||||
static const int pllv4_mult_range[] = {54, 27};
|
||||
|
||||
#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
|
||||
|
||||
#define LOCK_TIMEOUT_US USEC_PER_MSEC
|
||||
@ -94,17 +98,30 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
|
||||
static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
unsigned long parent_rate = *prate;
|
||||
unsigned long round_rate, i;
|
||||
u32 mfn, mfd = DEFAULT_MFD;
|
||||
bool found = false;
|
||||
u64 temp64;
|
||||
u32 mult;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
|
||||
round_rate = parent_rate * pllv4_mult_table[i];
|
||||
if (rate >= round_rate) {
|
||||
if (pll->use_mult_range) {
|
||||
temp64 = (u64)rate;
|
||||
do_div(temp64, parent_rate);
|
||||
mult = temp64;
|
||||
if (mult >= pllv4_mult_range[1] &&
|
||||
mult <= pllv4_mult_range[0]) {
|
||||
round_rate = parent_rate * mult;
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
|
||||
round_rate = parent_rate * pllv4_mult_table[i];
|
||||
if (rate >= round_rate) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -138,14 +155,20 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return round_rate + (u32)temp64;
|
||||
}
|
||||
|
||||
static bool clk_pllv4_is_valid_mult(unsigned int mult)
|
||||
static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* check if mult is in valid MULT table */
|
||||
for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
|
||||
if (pllv4_mult_table[i] == mult)
|
||||
if (pll->use_mult_range) {
|
||||
if (mult >= pllv4_mult_range[1] &&
|
||||
mult <= pllv4_mult_range[0])
|
||||
return true;
|
||||
} else {
|
||||
for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
|
||||
if (pllv4_mult_table[i] == mult)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
@ -160,7 +183,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
mult = rate / parent_rate;
|
||||
|
||||
if (!clk_pllv4_is_valid_mult(mult))
|
||||
if (!clk_pllv4_is_valid_mult(pll, mult))
|
||||
return -EINVAL;
|
||||
|
||||
if (parent_rate <= MAX_MFD)
|
||||
@ -227,10 +250,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
|
||||
|
||||
pll->base = base;
|
||||
|
||||
if (type == IMX_PLLV4_IMX8ULP) {
|
||||
if (type == IMX_PLLV4_IMX8ULP ||
|
||||
type == IMX_PLLV4_IMX8ULP_1GHZ) {
|
||||
pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
|
||||
pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
|
||||
pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
|
||||
if (type == IMX_PLLV4_IMX8ULP_1GHZ)
|
||||
pll->use_mult_range = true;
|
||||
} else {
|
||||
pll->cfg_offset = PLL_CFG_OFFSET;
|
||||
pll->num_offset = PLL_NUM_OFFSET;
|
||||
|
||||
@ -45,6 +45,7 @@ enum imx_pll14xx_type {
|
||||
enum imx_pllv4_type {
|
||||
IMX_PLLV4_IMX7ULP,
|
||||
IMX_PLLV4_IMX8ULP,
|
||||
IMX_PLLV4_IMX8ULP_1GHZ,
|
||||
};
|
||||
|
||||
enum imx_pfdv2_type {
|
||||
|
||||
@ -11,8 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
|
||||
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
|
||||
obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
|
||||
|
||||
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
|
||||
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
|
||||
obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
|
||||
|
||||
obj-y += clk-of-pxa1928.o
|
||||
|
||||
@ -55,6 +55,8 @@
|
||||
#define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0)
|
||||
#define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0)
|
||||
|
||||
#define CLK_AUDIO_NR_CLKS 3
|
||||
|
||||
struct mmp2_audio_clk {
|
||||
void __iomem *mmio_base;
|
||||
|
||||
@ -336,7 +338,7 @@ static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
|
||||
priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
|
||||
priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
|
||||
priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
|
||||
priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS;
|
||||
priv->clk_data.num = CLK_AUDIO_NR_CLKS;
|
||||
|
||||
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
&priv->clk_data);
|
||||
@ -349,7 +351,7 @@ static int mmp2_audio_clk_probe(struct platform_device *pdev)
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev,
|
||||
struct_size(priv, clk_data.hws,
|
||||
MMP2_CLK_AUDIO_NR_CLKS),
|
||||
CLK_AUDIO_NR_CLKS),
|
||||
GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -1,454 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* mmp2 clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
* Chao Xie <xiechao.mail@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk/mmp.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define APBC_RTC 0x0
|
||||
#define APBC_TWSI0 0x4
|
||||
#define APBC_TWSI1 0x8
|
||||
#define APBC_TWSI2 0xc
|
||||
#define APBC_TWSI3 0x10
|
||||
#define APBC_TWSI4 0x7c
|
||||
#define APBC_TWSI5 0x80
|
||||
#define APBC_KPC 0x18
|
||||
#define APBC_UART0 0x2c
|
||||
#define APBC_UART1 0x30
|
||||
#define APBC_UART2 0x34
|
||||
#define APBC_UART3 0x88
|
||||
#define APBC_GPIO 0x38
|
||||
#define APBC_PWM0 0x3c
|
||||
#define APBC_PWM1 0x40
|
||||
#define APBC_PWM2 0x44
|
||||
#define APBC_PWM3 0x48
|
||||
#define APBC_SSP0 0x50
|
||||
#define APBC_SSP1 0x54
|
||||
#define APBC_SSP2 0x58
|
||||
#define APBC_SSP3 0x5c
|
||||
#define APMU_SDH0 0x54
|
||||
#define APMU_SDH1 0x58
|
||||
#define APMU_SDH2 0xe8
|
||||
#define APMU_SDH3 0xec
|
||||
#define APMU_USB 0x5c
|
||||
#define APMU_DISP0 0x4c
|
||||
#define APMU_DISP1 0x110
|
||||
#define APMU_CCIC0 0x50
|
||||
#define APMU_CCIC1 0xf4
|
||||
#define MPMU_UART_PLL 0x14
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||
.factor = 2,
|
||||
.num_mask = 0x1fff,
|
||||
.den_mask = 0x1fff,
|
||||
.num_shift = 16,
|
||||
.den_shift = 0,
|
||||
};
|
||||
|
||||
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||
{.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||
{.num = 3521, .den = 689}, /*19.23MHZ */
|
||||
};
|
||||
|
||||
static const char *uart_parent[] = {"uart_pll", "vctcxo"};
|
||||
static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
|
||||
static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
|
||||
static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
|
||||
static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
|
||||
|
||||
void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
|
||||
phys_addr_t apbc_phys)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk *vctcxo;
|
||||
void __iomem *mpmu_base;
|
||||
void __iomem *apmu_base;
|
||||
void __iomem *apbc_base;
|
||||
|
||||
mpmu_base = ioremap(mpmu_phys, SZ_4K);
|
||||
if (!mpmu_base) {
|
||||
pr_err("error to ioremap MPMU base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apmu_base = ioremap(apmu_phys, SZ_4K);
|
||||
if (!apmu_base) {
|
||||
pr_err("error to ioremap APMU base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apbc_base = ioremap(apbc_phys, SZ_4K);
|
||||
if (!apbc_base) {
|
||||
pr_err("error to ioremap APBC base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
|
||||
clk_register_clkdev(clk, "clk32", NULL);
|
||||
|
||||
vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
|
||||
clk_register_clkdev(vctcxo, "vctcxo", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
|
||||
clk_register_clkdev(clk, "pll1", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
|
||||
clk_register_clkdev(clk, "usb_pll", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
|
||||
clk_register_clkdev(clk, "pll2", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_2", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_4", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_8", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_16", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
|
||||
CLK_SET_RATE_PARENT, 1, 5);
|
||||
clk_register_clkdev(clk, "pll1_20", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
|
||||
CLK_SET_RATE_PARENT, 1, 3);
|
||||
clk_register_clkdev(clk, "pll1_3", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_6", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_12", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll2_2", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll2_4", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll2_8", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll2_16", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
|
||||
CLK_SET_RATE_PARENT, 1, 3);
|
||||
clk_register_clkdev(clk, "pll2_3", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll2_6", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll2_12", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "vctcxo_2", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "vctcxo_4", NULL);
|
||||
|
||||
clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
|
||||
mpmu_base + MPMU_UART_PLL,
|
||||
&uart_factor_masks, uart_factor_tbl,
|
||||
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
|
||||
clk_set_rate(clk, 14745600);
|
||||
clk_register_clkdev(clk, "uart_pll", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi0", "vctcxo",
|
||||
apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi1", "vctcxo",
|
||||
apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi2", "vctcxo",
|
||||
apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi3", "vctcxo",
|
||||
apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi4", "vctcxo",
|
||||
apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi5", "vctcxo",
|
||||
apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
|
||||
|
||||
clk = mmp_clk_register_apbc("gpio", "vctcxo",
|
||||
apbc_base + APBC_GPIO, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp2-gpio");
|
||||
|
||||
clk = mmp_clk_register_apbc("kpc", "clk32",
|
||||
apbc_base + APBC_KPC, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa27x-keypad");
|
||||
|
||||
clk = mmp_clk_register_apbc("rtc", "clk32",
|
||||
apbc_base + APBC_RTC, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-rtc");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm0", "vctcxo",
|
||||
apbc_base + APBC_PWM0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm1", "vctcxo",
|
||||
apbc_base + APBC_PWM1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm2", "vctcxo",
|
||||
apbc_base + APBC_PWM2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm3", "vctcxo",
|
||||
apbc_base + APBC_PWM3, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, vctcxo);
|
||||
clk_register_clkdev(clk, "uart_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart0", "uart0_mux",
|
||||
apbc_base + APBC_UART0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, vctcxo);
|
||||
clk_register_clkdev(clk, "uart_mux.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart1", "uart1_mux",
|
||||
apbc_base + APBC_UART1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, vctcxo);
|
||||
clk_register_clkdev(clk, "uart_mux.2", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart2", "uart2_mux",
|
||||
apbc_base + APBC_UART2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, vctcxo);
|
||||
clk_register_clkdev(clk, "uart_mux.3", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart3", "uart3_mux",
|
||||
apbc_base + APBC_UART3, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "uart_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
|
||||
apbc_base + APBC_SSP0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
|
||||
apbc_base + APBC_SSP1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.1");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.2", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
|
||||
apbc_base + APBC_SSP2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.2");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.3", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
|
||||
apbc_base + APBC_SSP3, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.3");
|
||||
|
||||
clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
|
||||
ARRAY_SIZE(sdh_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sdh_mux", NULL);
|
||||
|
||||
clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
|
||||
10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
||||
clk_register_clkdev(clk, "sdh_div", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
|
||||
0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
|
||||
0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
|
||||
0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
|
||||
0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
|
||||
|
||||
clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
|
||||
0x9, &clk_lock);
|
||||
clk_register_clkdev(clk, "usb_clk", NULL);
|
||||
|
||||
clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
|
||||
ARRAY_SIZE(disp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_mux.0", NULL);
|
||||
|
||||
clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
|
||||
8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_div.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("disp0", "disp0_div",
|
||||
apmu_base + APMU_DISP0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-disp.0");
|
||||
|
||||
clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
|
||||
apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
|
||||
apmu_base + APMU_DISP0, 0x1024, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_sphy.0", NULL);
|
||||
|
||||
clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
|
||||
ARRAY_SIZE(disp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_mux.1", NULL);
|
||||
|
||||
clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
|
||||
8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_div.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("disp1", "disp1_div",
|
||||
apmu_base + APMU_DISP1, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-disp.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
|
||||
apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_arbiter", NULL);
|
||||
|
||||
clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
|
||||
ARRAY_SIZE(ccic_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_mux.0", NULL);
|
||||
|
||||
clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
|
||||
17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_div.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
|
||||
apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
|
||||
apmu_base + APMU_CCIC0, 0x24, &clk_lock);
|
||||
clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
|
||||
|
||||
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
|
||||
10, 5, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
|
||||
apmu_base + APMU_CCIC0, 0x300, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
|
||||
ARRAY_SIZE(ccic_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_mux.1", NULL);
|
||||
|
||||
clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
|
||||
16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_div.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
|
||||
apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
|
||||
apmu_base + APMU_CCIC1, 0x24, &clk_lock);
|
||||
clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
|
||||
|
||||
clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
|
||||
10, 5, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
|
||||
apmu_base + APMU_CCIC1, 0x300, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
|
||||
}
|
||||
@ -78,6 +78,8 @@
|
||||
#define MPMU_PLL_DIFF_CTRL 0x68
|
||||
#define MPMU_PLL2_CTRL1 0x414
|
||||
|
||||
#define NR_CLKS 200
|
||||
|
||||
enum mmp2_clk_model {
|
||||
CLK_MODEL_MMP2,
|
||||
CLK_MODEL_MMP3,
|
||||
@ -543,7 +545,7 @@ static void __init mmp2_clk_init(struct device_node *np)
|
||||
|
||||
mmp2_pm_domain_init(np, pxa_unit);
|
||||
|
||||
mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
|
||||
mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
|
||||
|
||||
mmp2_main_clk_init(pxa_unit);
|
||||
|
||||
|
||||
@ -62,6 +62,8 @@
|
||||
#define APMU_EPD 0x104
|
||||
#define MPMU_UART_PLL 0x14
|
||||
|
||||
#define NR_CLKS 200
|
||||
|
||||
struct pxa168_clk_unit {
|
||||
struct mmp_clk_unit unit;
|
||||
void __iomem *mpmu_base;
|
||||
@ -321,7 +323,7 @@ static void __init pxa168_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
|
||||
mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
|
||||
|
||||
pxa168_pll_init(pxa_unit);
|
||||
|
||||
|
||||
@ -22,6 +22,9 @@
|
||||
|
||||
#define MPMU_UART_PLL 0x14
|
||||
|
||||
#define APBC_NR_CLKS 48
|
||||
#define APMU_NR_CLKS 96
|
||||
|
||||
struct pxa1928_clk_unit {
|
||||
struct mmp_clk_unit unit;
|
||||
void __iomem *mpmu_base;
|
||||
@ -235,7 +238,7 @@ static void __init pxa1928_apmu_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS);
|
||||
mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS);
|
||||
|
||||
pxa1928_axi_periph_clk_init(pxa_unit);
|
||||
}
|
||||
@ -256,7 +259,7 @@ static void __init pxa1928_apbc_clk_init(struct device_node *np)
|
||||
return;
|
||||
}
|
||||
|
||||
mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS);
|
||||
mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
|
||||
|
||||
pxa1928_apb_periph_clk_init(pxa_unit);
|
||||
pxa1928_clk_reset_init(np, pxa_unit);
|
||||
|
||||
@ -44,6 +44,8 @@
|
||||
#define APMU_DFC 0x60
|
||||
#define MPMU_UART_PLL 0x14
|
||||
|
||||
#define NR_CLKS 200
|
||||
|
||||
struct pxa910_clk_unit {
|
||||
struct mmp_clk_unit unit;
|
||||
void __iomem *mpmu_base;
|
||||
@ -296,7 +298,7 @@ static void __init pxa910_clk_init(struct device_node *np)
|
||||
goto unmap_apbc_region;
|
||||
}
|
||||
|
||||
mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
|
||||
mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
|
||||
|
||||
pxa910_pll_init(pxa_unit);
|
||||
|
||||
|
||||
@ -1,354 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* pxa168 clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
* Chao Xie <xiechao.mail@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/mmp.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define APBC_RTC 0x28
|
||||
#define APBC_TWSI0 0x2c
|
||||
#define APBC_KPC 0x30
|
||||
#define APBC_UART0 0x0
|
||||
#define APBC_UART1 0x4
|
||||
#define APBC_GPIO 0x8
|
||||
#define APBC_PWM0 0xc
|
||||
#define APBC_PWM1 0x10
|
||||
#define APBC_PWM2 0x14
|
||||
#define APBC_PWM3 0x18
|
||||
#define APBC_SSP0 0x81c
|
||||
#define APBC_SSP1 0x820
|
||||
#define APBC_SSP2 0x84c
|
||||
#define APBC_SSP3 0x858
|
||||
#define APBC_SSP4 0x85c
|
||||
#define APBC_TWSI1 0x6c
|
||||
#define APBC_UART2 0x70
|
||||
#define APMU_SDH0 0x54
|
||||
#define APMU_SDH1 0x58
|
||||
#define APMU_USB 0x5c
|
||||
#define APMU_DISP0 0x4c
|
||||
#define APMU_CCIC0 0x50
|
||||
#define APMU_DFC 0x60
|
||||
#define MPMU_UART_PLL 0x14
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||
.factor = 2,
|
||||
.num_mask = 0x1fff,
|
||||
.den_mask = 0x1fff,
|
||||
.num_shift = 16,
|
||||
.den_shift = 0,
|
||||
};
|
||||
|
||||
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||
{.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||
};
|
||||
|
||||
static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
|
||||
static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
|
||||
static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
|
||||
static const char *disp_parent[] = {"pll1_2", "pll1_12"};
|
||||
static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
|
||||
static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
|
||||
|
||||
void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
|
||||
phys_addr_t apbc_phys)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk *uart_pll;
|
||||
void __iomem *mpmu_base;
|
||||
void __iomem *apmu_base;
|
||||
void __iomem *apbc_base;
|
||||
|
||||
mpmu_base = ioremap(mpmu_phys, SZ_4K);
|
||||
if (!mpmu_base) {
|
||||
pr_err("error to ioremap MPMU base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apmu_base = ioremap(apmu_phys, SZ_4K);
|
||||
if (!apmu_base) {
|
||||
pr_err("error to ioremap APMU base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apbc_base = ioremap(apbc_phys, SZ_4K);
|
||||
if (!apbc_base) {
|
||||
pr_err("error to ioremap APBC base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
|
||||
clk_register_clkdev(clk, "clk32", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
|
||||
clk_register_clkdev(clk, "vctcxo", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
|
||||
clk_register_clkdev(clk, "pll1", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_2", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_4", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_8", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_16", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
|
||||
CLK_SET_RATE_PARENT, 1, 3);
|
||||
clk_register_clkdev(clk, "pll1_6", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_12", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_24", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_48", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_96", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
|
||||
CLK_SET_RATE_PARENT, 1, 13);
|
||||
clk_register_clkdev(clk, "pll1_13", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
|
||||
CLK_SET_RATE_PARENT, 2, 3);
|
||||
clk_register_clkdev(clk, "pll1_13_1_5", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
|
||||
CLK_SET_RATE_PARENT, 2, 3);
|
||||
clk_register_clkdev(clk, "pll1_2_1_5", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
|
||||
CLK_SET_RATE_PARENT, 3, 16);
|
||||
clk_register_clkdev(clk, "pll1_3_16", NULL);
|
||||
|
||||
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
|
||||
mpmu_base + MPMU_UART_PLL,
|
||||
&uart_factor_masks, uart_factor_tbl,
|
||||
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
|
||||
clk_set_rate(uart_pll, 14745600);
|
||||
clk_register_clkdev(uart_pll, "uart_pll", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
|
||||
apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
|
||||
apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
|
||||
|
||||
clk = mmp_clk_register_apbc("gpio", "vctcxo",
|
||||
apbc_base + APBC_GPIO, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-gpio");
|
||||
|
||||
clk = mmp_clk_register_apbc("kpc", "clk32",
|
||||
apbc_base + APBC_KPC, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa27x-keypad");
|
||||
|
||||
clk = mmp_clk_register_apbc("rtc", "clk32",
|
||||
apbc_base + APBC_RTC, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sa1100-rtc");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm0", "pll1_48",
|
||||
apbc_base + APBC_PWM0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm1", "pll1_48",
|
||||
apbc_base + APBC_PWM1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm2", "pll1_48",
|
||||
apbc_base + APBC_PWM2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm3", "pll1_48",
|
||||
apbc_base + APBC_PWM3, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, uart_pll);
|
||||
clk_register_clkdev(clk, "uart_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart0", "uart0_mux",
|
||||
apbc_base + APBC_UART0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, uart_pll);
|
||||
clk_register_clkdev(clk, "uart_mux.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart1", "uart1_mux",
|
||||
apbc_base + APBC_UART1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, uart_pll);
|
||||
clk_register_clkdev(clk, "uart_mux.2", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart2", "uart2_mux",
|
||||
apbc_base + APBC_UART2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "uart_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
|
||||
10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
|
||||
10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.1");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.2", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
|
||||
10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.2");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.3", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
|
||||
10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.3");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.4", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
|
||||
10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.4");
|
||||
|
||||
clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
|
||||
0x19b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
|
||||
ARRAY_SIZE(sdh_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sdh0_mux", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
|
||||
0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
|
||||
ARRAY_SIZE(sdh_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sdh1_mux", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
|
||||
0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
|
||||
0x9, &clk_lock);
|
||||
clk_register_clkdev(clk, "usb_clk", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
|
||||
0x12, &clk_lock);
|
||||
clk_register_clkdev(clk, "sph_clk", NULL);
|
||||
|
||||
clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
|
||||
ARRAY_SIZE(disp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("disp0", "disp0_mux",
|
||||
apmu_base + APMU_DISP0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
|
||||
|
||||
clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
|
||||
apmu_base + APMU_DISP0, 0x24, &clk_lock);
|
||||
clk_register_clkdev(clk, "hclk", "mmp-disp.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
|
||||
ARRAY_SIZE(ccic_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
|
||||
apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
|
||||
ARRAY_SIZE(ccic_phy_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
|
||||
apmu_base + APMU_CCIC0, 0x24, &clk_lock);
|
||||
clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
|
||||
|
||||
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
|
||||
10, 5, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk_div", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
|
||||
apmu_base + APMU_CCIC0, 0x300, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
|
||||
}
|
||||
@ -1,325 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* pxa910 clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
* Chao Xie <xiechao.mail@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/mmp.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define APBC_RTC 0x28
|
||||
#define APBC_TWSI0 0x2c
|
||||
#define APBC_KPC 0x18
|
||||
#define APBC_UART0 0x0
|
||||
#define APBC_UART1 0x4
|
||||
#define APBC_GPIO 0x8
|
||||
#define APBC_PWM0 0xc
|
||||
#define APBC_PWM1 0x10
|
||||
#define APBC_PWM2 0x14
|
||||
#define APBC_PWM3 0x18
|
||||
#define APBC_SSP0 0x1c
|
||||
#define APBC_SSP1 0x20
|
||||
#define APBC_SSP2 0x4c
|
||||
#define APBCP_TWSI1 0x28
|
||||
#define APBCP_UART2 0x1c
|
||||
#define APMU_SDH0 0x54
|
||||
#define APMU_SDH1 0x58
|
||||
#define APMU_USB 0x5c
|
||||
#define APMU_DISP0 0x4c
|
||||
#define APMU_CCIC0 0x50
|
||||
#define APMU_DFC 0x60
|
||||
#define MPMU_UART_PLL 0x14
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||
.factor = 2,
|
||||
.num_mask = 0x1fff,
|
||||
.den_mask = 0x1fff,
|
||||
.num_shift = 16,
|
||||
.den_shift = 0,
|
||||
};
|
||||
|
||||
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||
{.num = 8125, .den = 1536}, /*14.745MHZ */
|
||||
};
|
||||
|
||||
static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
|
||||
static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
|
||||
static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
|
||||
static const char *disp_parent[] = {"pll1_2", "pll1_12"};
|
||||
static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
|
||||
static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
|
||||
|
||||
void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
|
||||
phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk *uart_pll;
|
||||
void __iomem *mpmu_base;
|
||||
void __iomem *apmu_base;
|
||||
void __iomem *apbcp_base;
|
||||
void __iomem *apbc_base;
|
||||
|
||||
mpmu_base = ioremap(mpmu_phys, SZ_4K);
|
||||
if (!mpmu_base) {
|
||||
pr_err("error to ioremap MPMU base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apmu_base = ioremap(apmu_phys, SZ_4K);
|
||||
if (!apmu_base) {
|
||||
pr_err("error to ioremap APMU base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apbcp_base = ioremap(apbcp_phys, SZ_4K);
|
||||
if (!apbcp_base) {
|
||||
pr_err("error to ioremap APBC extension base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
apbc_base = ioremap(apbc_phys, SZ_4K);
|
||||
if (!apbc_base) {
|
||||
pr_err("error to ioremap APBC base\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
|
||||
clk_register_clkdev(clk, "clk32", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
|
||||
clk_register_clkdev(clk, "vctcxo", NULL);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
|
||||
clk_register_clkdev(clk, "pll1", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_2", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_4", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_8", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_16", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
|
||||
CLK_SET_RATE_PARENT, 1, 3);
|
||||
clk_register_clkdev(clk, "pll1_6", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_12", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_24", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_48", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clk_register_clkdev(clk, "pll1_96", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
|
||||
CLK_SET_RATE_PARENT, 1, 13);
|
||||
clk_register_clkdev(clk, "pll1_13", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
|
||||
CLK_SET_RATE_PARENT, 2, 3);
|
||||
clk_register_clkdev(clk, "pll1_13_1_5", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
|
||||
CLK_SET_RATE_PARENT, 2, 3);
|
||||
clk_register_clkdev(clk, "pll1_2_1_5", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
|
||||
CLK_SET_RATE_PARENT, 3, 16);
|
||||
clk_register_clkdev(clk, "pll1_3_16", NULL);
|
||||
|
||||
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
|
||||
mpmu_base + MPMU_UART_PLL,
|
||||
&uart_factor_masks, uart_factor_tbl,
|
||||
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
|
||||
clk_set_rate(uart_pll, 14745600);
|
||||
clk_register_clkdev(uart_pll, "uart_pll", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
|
||||
apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
|
||||
|
||||
clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
|
||||
apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
|
||||
|
||||
clk = mmp_clk_register_apbc("gpio", "vctcxo",
|
||||
apbc_base + APBC_GPIO, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-gpio");
|
||||
|
||||
clk = mmp_clk_register_apbc("kpc", "clk32",
|
||||
apbc_base + APBC_KPC, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa27x-keypad");
|
||||
|
||||
clk = mmp_clk_register_apbc("rtc", "clk32",
|
||||
apbc_base + APBC_RTC, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sa1100-rtc");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm0", "pll1_48",
|
||||
apbc_base + APBC_PWM0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm1", "pll1_48",
|
||||
apbc_base + APBC_PWM1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm2", "pll1_48",
|
||||
apbc_base + APBC_PWM2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
|
||||
|
||||
clk = mmp_clk_register_apbc("pwm3", "pll1_48",
|
||||
apbc_base + APBC_PWM3, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, uart_pll);
|
||||
clk_register_clkdev(clk, "uart_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart0", "uart0_mux",
|
||||
apbc_base + APBC_UART0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, uart_pll);
|
||||
clk_register_clkdev(clk, "uart_mux.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart1", "uart1_mux",
|
||||
apbc_base + APBC_UART1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
|
||||
|
||||
clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
|
||||
ARRAY_SIZE(uart_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
|
||||
clk_set_parent(clk, uart_pll);
|
||||
clk_register_clkdev(clk, "uart_mux.2", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("uart2", "uart2_mux",
|
||||
apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "uart_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
|
||||
apbc_base + APBC_SSP0, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
|
||||
ARRAY_SIZE(ssp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ssp_mux.1", NULL);
|
||||
|
||||
clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
|
||||
apbc_base + APBC_SSP1, 10, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-ssp.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("dfc", "pll1_4",
|
||||
apmu_base + APMU_DFC, 0x19b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
|
||||
ARRAY_SIZE(sdh_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sdh0_mux", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
|
||||
apmu_base + APMU_SDH0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
|
||||
ARRAY_SIZE(sdh_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sdh1_mux", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
|
||||
apmu_base + APMU_SDH1, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
|
||||
|
||||
clk = mmp_clk_register_apmu("usb", "usb_pll",
|
||||
apmu_base + APMU_USB, 0x9, &clk_lock);
|
||||
clk_register_clkdev(clk, "usb_clk", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("sph", "usb_pll",
|
||||
apmu_base + APMU_USB, 0x12, &clk_lock);
|
||||
clk_register_clkdev(clk, "sph_clk", NULL);
|
||||
|
||||
clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
|
||||
ARRAY_SIZE(disp_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "disp_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("disp0", "disp0_mux",
|
||||
apmu_base + APMU_DISP0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, NULL, "mmp-disp.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
|
||||
ARRAY_SIZE(ccic_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
|
||||
apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
|
||||
clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
|
||||
|
||||
clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
|
||||
ARRAY_SIZE(ccic_phy_parent),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
|
||||
apmu_base + APMU_CCIC0, 0x24, &clk_lock);
|
||||
clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
|
||||
|
||||
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
|
||||
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
|
||||
10, 5, 0, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk_div", NULL);
|
||||
|
||||
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
|
||||
apmu_base + APMU_CCIC0, 0x300, &clk_lock);
|
||||
clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
|
||||
}
|
||||
@ -240,9 +240,9 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
|
||||
GFP_KERNEL);
|
||||
if (!cp110_clk_data)
|
||||
return -ENOMEM;
|
||||
cp110_clk_data->num = CP110_CLK_NUM;
|
||||
|
||||
cp110_clks = cp110_clk_data->hws;
|
||||
cp110_clk_data->num = CP110_CLK_NUM;
|
||||
|
||||
/* Register the PLL0 which is the root of the hw tree */
|
||||
pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
|
||||
|
||||
@ -590,6 +590,7 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
|
||||
data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
data->num = 2;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
@ -605,7 +606,6 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
|
||||
|
||||
data->hws[0] = &pwrcl_pmux.clkr.hw;
|
||||
data->hws[1] = &perfcl_pmux.clkr.hw;
|
||||
data->num = 2;
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
|
||||
}
|
||||
|
||||
@ -177,7 +177,7 @@ static const struct clk_ops clk_spmi_pmic_div_ops = {
|
||||
|
||||
struct spmi_pmic_div_clk_cc {
|
||||
int nclks;
|
||||
struct clkdiv clks[];
|
||||
struct clkdiv clks[] __counted_by(nclks);
|
||||
};
|
||||
|
||||
static struct clk_hw *
|
||||
|
||||
@ -521,6 +521,7 @@ static int mt7621_clk_probe(struct platform_device *pdev)
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
clk_data->num = count;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++)
|
||||
clk_data->hws[i] = mt7621_clk_early[i];
|
||||
@ -537,8 +538,6 @@ static int mt7621_clk_probe(struct platform_device *pdev)
|
||||
goto unreg_clk_fixed;
|
||||
}
|
||||
|
||||
clk_data->num = count;
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't add clk hw provider\n");
|
||||
|
||||
@ -100,6 +100,11 @@
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1)
|
||||
#define CLKS_NR_DMC (CLK_DIV_DMCD + 1)
|
||||
#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1)
|
||||
|
||||
static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
|
||||
SRC_LEFTBUS,
|
||||
DIV_LEFTBUS,
|
||||
@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info __initconst = {
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
|
||||
.cpu_clks = exynos3250_cpu_clks,
|
||||
.nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
|
||||
.nr_clk_ids = CLK_NR_CLKS,
|
||||
.nr_clk_ids = CLKS_NR_MAIN,
|
||||
.clk_regs = exynos3250_cmu_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
|
||||
};
|
||||
@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
|
||||
.div_clks = dmc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(dmc_div_clks),
|
||||
.nr_clk_ids = NR_CLKS_DMC,
|
||||
.nr_clk_ids = CLKS_NR_DMC,
|
||||
.clk_regs = exynos3250_cmu_dmc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
|
||||
};
|
||||
@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
|
||||
.gate_clks = isp_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
|
||||
.nr_clk_ids = NR_CLKS_ISP,
|
||||
.nr_clk_ids = CLKS_NR_ISP,
|
||||
};
|
||||
|
||||
static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
|
||||
|
||||
@ -135,6 +135,9 @@
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR (CLK_DIV_CORE2 + 1)
|
||||
|
||||
/* the exynos4 soc type */
|
||||
enum exynos4_soc {
|
||||
EXYNOS4210,
|
||||
@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
|
||||
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
|
||||
|
||||
@ -22,6 +22,9 @@
|
||||
#define E4X12_GATE_ISP0 0x0800
|
||||
#define E4X12_GATE_ISP1 0x0804
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_ISP (CLK_ISP_DIV_MCUISP1 + 1)
|
||||
|
||||
/*
|
||||
* Support for CMU save/restore across system suspends
|
||||
*/
|
||||
@ -121,7 +124,7 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
|
||||
if (!exynos4x12_save_isp)
|
||||
return -ENOMEM;
|
||||
|
||||
ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS);
|
||||
ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
|
||||
|
||||
platform_set_drvdata(pdev, ctx);
|
||||
|
||||
|
||||
@ -100,6 +100,9 @@
|
||||
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
|
||||
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR (CLK_MOUT_VPLLSRC + 1)
|
||||
|
||||
/* list of PLLs to be registered */
|
||||
enum exynos5250_plls {
|
||||
apll, mpll, cpll, epll, vpll, gpll, bpll,
|
||||
@ -797,7 +800,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
||||
panic("%s: unable to determine soc\n", __func__);
|
||||
}
|
||||
|
||||
ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
|
||||
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
|
||||
|
||||
@ -15,6 +15,21 @@
|
||||
|
||||
#include <dt-bindings/clock/exynos5260-clk.h>
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
|
||||
#define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1)
|
||||
#define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1)
|
||||
#define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
|
||||
#define CLKS_NR_G3D (G3D_CLK_G3D + 1)
|
||||
#define CLKS_NR_AUD (AUD_SCLK_I2S + 1)
|
||||
#define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1)
|
||||
#define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1)
|
||||
#define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1)
|
||||
#define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1)
|
||||
#define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
|
||||
#define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1)
|
||||
#define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1)
|
||||
|
||||
/*
|
||||
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
|
||||
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
|
||||
@ -135,7 +150,7 @@ static const struct samsung_cmu_info aud_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
|
||||
.gate_clks = aud_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
|
||||
.nr_clk_ids = AUD_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_AUD,
|
||||
.clk_regs = aud_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
|
||||
};
|
||||
@ -325,7 +340,7 @@ static const struct samsung_cmu_info disp_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
|
||||
.gate_clks = disp_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
|
||||
.nr_clk_ids = DISP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_DISP,
|
||||
.clk_regs = disp_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
|
||||
};
|
||||
@ -389,7 +404,7 @@ static const struct samsung_cmu_info egl_cmu __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
|
||||
.div_clks = egl_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(egl_div_clks),
|
||||
.nr_clk_ids = EGL_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_EGL,
|
||||
.clk_regs = egl_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
|
||||
};
|
||||
@ -489,7 +504,7 @@ static const struct samsung_cmu_info fsys_cmu __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
|
||||
.gate_clks = fsys_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
|
||||
.nr_clk_ids = FSYS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS,
|
||||
.clk_regs = fsys_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
|
||||
};
|
||||
@ -580,7 +595,7 @@ static const struct samsung_cmu_info g2d_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
|
||||
.gate_clks = g2d_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
|
||||
.nr_clk_ids = G2D_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_G2D,
|
||||
.clk_regs = g2d_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
|
||||
};
|
||||
@ -643,7 +658,7 @@ static const struct samsung_cmu_info g3d_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
|
||||
.gate_clks = g3d_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
|
||||
.nr_clk_ids = G3D_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_G3D,
|
||||
.clk_regs = g3d_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
|
||||
};
|
||||
@ -776,7 +791,7 @@ static const struct samsung_cmu_info gscl_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(gscl_div_clks),
|
||||
.gate_clks = gscl_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
|
||||
.nr_clk_ids = GSCL_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_GSCL,
|
||||
.clk_regs = gscl_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
|
||||
};
|
||||
@ -895,7 +910,7 @@ static const struct samsung_cmu_info isp_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
|
||||
.gate_clks = isp_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
|
||||
.nr_clk_ids = ISP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_ISP,
|
||||
.clk_regs = isp_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
|
||||
};
|
||||
@ -959,7 +974,7 @@ static const struct samsung_cmu_info kfc_cmu __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
|
||||
.div_clks = kfc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(kfc_div_clks),
|
||||
.nr_clk_ids = KFC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_KFC,
|
||||
.clk_regs = kfc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
|
||||
};
|
||||
@ -1015,7 +1030,7 @@ static const struct samsung_cmu_info mfc_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
|
||||
.gate_clks = mfc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
|
||||
.nr_clk_ids = MFC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MFC,
|
||||
.clk_regs = mfc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
|
||||
};
|
||||
@ -1164,7 +1179,7 @@ static const struct samsung_cmu_info mif_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
|
||||
.gate_clks = mif_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
|
||||
.nr_clk_ids = MIF_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MIF,
|
||||
.clk_regs = mif_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
|
||||
};
|
||||
@ -1370,7 +1385,7 @@ static const struct samsung_cmu_info peri_cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
|
||||
.gate_clks = peri_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
|
||||
.nr_clk_ids = PERI_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERI,
|
||||
.clk_regs = peri_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
|
||||
};
|
||||
@ -1826,7 +1841,7 @@ static const struct samsung_cmu_info top_cmu __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
|
||||
.fixed_clks = fixed_rate_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_TOP,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
};
|
||||
|
||||
@ -56,6 +56,9 @@
|
||||
#define SRC_KFC 0x28200
|
||||
#define DIV_KFC0 0x28500
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR 512
|
||||
|
||||
/* list of PLLs */
|
||||
enum exynos5410_plls {
|
||||
apll, cpll, epll, mpll,
|
||||
@ -260,7 +263,7 @@ static const struct samsung_cmu_info cmu __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(exynos5410_div_clks),
|
||||
.gate_clks = exynos5410_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks),
|
||||
.nr_clk_ids = CLK_NR_CLKS,
|
||||
.nr_clk_ids = CLKS_NR,
|
||||
};
|
||||
|
||||
/* register exynos5410 clocks */
|
||||
|
||||
@ -139,6 +139,9 @@
|
||||
#define SRC_KFC 0x28200
|
||||
#define DIV_KFC0 0x28500
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1)
|
||||
|
||||
/* Exynos5x SoC type */
|
||||
enum exynos5x_soc {
|
||||
EXYNOS5420,
|
||||
@ -1587,7 +1590,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
|
||||
exynos5x_soc = soc;
|
||||
|
||||
ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
|
||||
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
|
||||
|
||||
@ -21,6 +21,29 @@
|
||||
#include "clk-exynos-arm64.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1)
|
||||
#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1)
|
||||
#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1)
|
||||
#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1)
|
||||
#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1)
|
||||
#define CLKS_NR_FSYS (CLK_PCIE + 1)
|
||||
#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1)
|
||||
#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)
|
||||
#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1)
|
||||
#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1)
|
||||
#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1)
|
||||
#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1)
|
||||
#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1)
|
||||
#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1)
|
||||
#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1)
|
||||
#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1)
|
||||
#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1)
|
||||
#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1)
|
||||
#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)
|
||||
#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1)
|
||||
#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1)
|
||||
|
||||
/*
|
||||
* Register offset definitions for CMU_TOP
|
||||
*/
|
||||
@ -798,7 +821,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
.nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
|
||||
.fixed_factor_clks = top_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_TOP,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
.suspend_regs = top_suspend_regs,
|
||||
@ -877,7 +900,7 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(cpif_div_clks),
|
||||
.gate_clks = cpif_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
|
||||
.nr_clk_ids = CPIF_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CPIF,
|
||||
.clk_regs = cpif_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
|
||||
.suspend_regs = cpif_suspend_regs,
|
||||
@ -1531,7 +1554,7 @@ static const struct samsung_cmu_info mif_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
|
||||
.fixed_factor_clks = mif_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
|
||||
.nr_clk_ids = MIF_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MIF,
|
||||
.clk_regs = mif_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
|
||||
};
|
||||
@ -1730,7 +1753,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(peric_div_clks),
|
||||
.gate_clks = peric_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
|
||||
.nr_clk_ids = PERIC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERIC,
|
||||
.clk_regs = peric_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
|
||||
.suspend_regs = peric_suspend_regs,
|
||||
@ -1924,7 +1947,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
|
||||
static const struct samsung_cmu_info peris_cmu_info __initconst = {
|
||||
.gate_clks = peris_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
|
||||
.nr_clk_ids = PERIS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERIS,
|
||||
.clk_regs = peris_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
|
||||
};
|
||||
@ -2336,7 +2359,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
|
||||
.fixed_clks = fsys_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
|
||||
.nr_clk_ids = FSYS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS,
|
||||
.clk_regs = fsys_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
|
||||
.suspend_regs = fsys_suspend_regs,
|
||||
@ -2459,7 +2482,7 @@ static const struct samsung_cmu_info g2d_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
|
||||
.gate_clks = g2d_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
|
||||
.nr_clk_ids = G2D_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_G2D,
|
||||
.clk_regs = g2d_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
|
||||
.suspend_regs = g2d_suspend_regs,
|
||||
@ -2887,7 +2910,7 @@ static const struct samsung_cmu_info disp_cmu_info __initconst = {
|
||||
.nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
|
||||
.fixed_factor_clks = disp_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
|
||||
.nr_clk_ids = DISP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_DISP,
|
||||
.clk_regs = disp_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
|
||||
.suspend_regs = disp_suspend_regs,
|
||||
@ -3057,7 +3080,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
|
||||
.fixed_clks = aud_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
|
||||
.nr_clk_ids = AUD_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_AUD,
|
||||
.clk_regs = aud_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
|
||||
.suspend_regs = aud_suspend_regs,
|
||||
@ -3189,7 +3212,7 @@ static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
|
||||
.gate_clks = bus##id##_gate_clks, \
|
||||
.nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
|
||||
.nr_clk_ids = BUSx_NR_CLK
|
||||
.nr_clk_ids = CLKS_NR_BUSX
|
||||
|
||||
static const struct samsung_cmu_info bus0_cmu_info __initconst = {
|
||||
CMU_BUS_INFO_CLKS(0),
|
||||
@ -3340,7 +3363,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
|
||||
.gate_clks = g3d_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
|
||||
.nr_clk_ids = G3D_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_G3D,
|
||||
.clk_regs = g3d_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
|
||||
.suspend_regs = g3d_suspend_regs,
|
||||
@ -3483,7 +3506,7 @@ static const struct samsung_cmu_info gscl_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
|
||||
.gate_clks = gscl_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
|
||||
.nr_clk_ids = GSCL_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_GSCL,
|
||||
.clk_regs = gscl_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
|
||||
.suspend_regs = gscl_suspend_regs,
|
||||
@ -3693,7 +3716,7 @@ static const struct samsung_cmu_info apollo_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
|
||||
.cpu_clks = apollo_cpu_clks,
|
||||
.nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks),
|
||||
.nr_clk_ids = APOLLO_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_APOLLO,
|
||||
.clk_regs = apollo_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
|
||||
};
|
||||
@ -3938,7 +3961,7 @@ static const struct samsung_cmu_info atlas_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
|
||||
.cpu_clks = atlas_cpu_clks,
|
||||
.nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks),
|
||||
.nr_clk_ids = ATLAS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_ATLAS,
|
||||
.clk_regs = atlas_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
|
||||
};
|
||||
@ -4112,7 +4135,7 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(mscl_div_clks),
|
||||
.gate_clks = mscl_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
|
||||
.nr_clk_ids = MSCL_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MSCL,
|
||||
.clk_regs = mscl_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
|
||||
.suspend_regs = mscl_suspend_regs,
|
||||
@ -4220,7 +4243,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
|
||||
.gate_clks = mfc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
|
||||
.nr_clk_ids = MFC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MFC,
|
||||
.clk_regs = mfc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
|
||||
.suspend_regs = mfc_suspend_regs,
|
||||
@ -4330,7 +4353,7 @@ static const struct samsung_cmu_info hevc_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(hevc_div_clks),
|
||||
.gate_clks = hevc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
|
||||
.nr_clk_ids = HEVC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_HEVC,
|
||||
.clk_regs = hevc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
|
||||
.suspend_regs = hevc_suspend_regs,
|
||||
@ -4583,7 +4606,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
|
||||
.gate_clks = isp_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
|
||||
.nr_clk_ids = ISP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_ISP,
|
||||
.clk_regs = isp_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
|
||||
.suspend_regs = isp_suspend_regs,
|
||||
@ -5065,7 +5088,7 @@ static const struct samsung_cmu_info cam0_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
|
||||
.fixed_clks = cam0_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
|
||||
.nr_clk_ids = CAM0_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CAM0,
|
||||
.clk_regs = cam0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
|
||||
.suspend_regs = cam0_suspend_regs,
|
||||
@ -5440,7 +5463,7 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
|
||||
.fixed_clks = cam1_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
|
||||
.nr_clk_ids = CAM1_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CAM1,
|
||||
.clk_regs = cam1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
|
||||
.suspend_regs = cam1_suspend_regs,
|
||||
@ -5472,7 +5495,7 @@ static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
|
||||
static const struct samsung_cmu_info imem_cmu_info __initconst = {
|
||||
.gate_clks = imem_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
|
||||
.nr_clk_ids = IMEM_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_IMEM,
|
||||
.clk_regs = imem_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
|
||||
.clk_name = "aclk_imem_200",
|
||||
|
||||
@ -16,6 +16,12 @@
|
||||
#include "clk.h"
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
|
||||
#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_TOP (0x12060000) */
|
||||
@ -333,7 +339,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(top_div_clks),
|
||||
.gate_clks = top_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_TOP,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
};
|
||||
@ -552,7 +558,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
|
||||
.gate_clks = peri_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
|
||||
.nr_clk_ids = PERI_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERI,
|
||||
.clk_regs = peri_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
|
||||
.clk_name = "dout_peri_bus",
|
||||
@ -661,7 +667,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(core_div_clks),
|
||||
.gate_clks = core_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
|
||||
.nr_clk_ids = CORE_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CORE,
|
||||
.clk_regs = core_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
|
||||
.clk_name = "dout_core_bus",
|
||||
@ -743,7 +749,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
|
||||
.gate_clks = fsys_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
|
||||
.nr_clk_ids = FSYS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS,
|
||||
.clk_regs = fsys_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
|
||||
.clk_name = "dout_fsys_bus",
|
||||
|
||||
@ -16,6 +16,19 @@
|
||||
#include "clk.h"
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
|
||||
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
|
||||
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
|
||||
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
|
||||
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
|
||||
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
|
||||
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_TOP (0x120e0000) */
|
||||
@ -485,7 +498,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(top_div_clks),
|
||||
.gate_clks = top_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_TOP,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
};
|
||||
@ -625,7 +638,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
|
||||
.fixed_clks = apm_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
|
||||
.nr_clk_ids = APM_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_APM,
|
||||
.clk_regs = apm_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
|
||||
.clk_name = "dout_clkcmu_apm_bus",
|
||||
@ -908,7 +921,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
|
||||
.fixed_clks = aud_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
|
||||
.nr_clk_ids = AUD_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_AUD,
|
||||
.clk_regs = aud_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
|
||||
.clk_name = "dout_aud",
|
||||
@ -1011,7 +1024,7 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
|
||||
.fixed_clks = cmgp_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
|
||||
.nr_clk_ids = CMGP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CMGP,
|
||||
.clk_regs = cmgp_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
|
||||
.clk_name = "gout_clkcmu_cmgp_bus",
|
||||
@ -1107,7 +1120,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
|
||||
.gate_clks = g3d_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
|
||||
.nr_clk_ids = G3D_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_G3D,
|
||||
.clk_regs = g3d_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
|
||||
.clk_name = "dout_g3d_switch",
|
||||
@ -1209,7 +1222,7 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
|
||||
.gate_clks = hsi_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
|
||||
.nr_clk_ids = HSI_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_HSI,
|
||||
.clk_regs = hsi_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
|
||||
.clk_name = "dout_hsi_bus",
|
||||
@ -1341,7 +1354,7 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(is_div_clks),
|
||||
.gate_clks = is_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
|
||||
.nr_clk_ids = IS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_IS,
|
||||
.clk_regs = is_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
|
||||
.clk_name = "dout_is_bus",
|
||||
@ -1450,7 +1463,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
|
||||
.gate_clks = mfcmscl_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
|
||||
.nr_clk_ids = MFCMSCL_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MFCMSCL,
|
||||
.clk_regs = mfcmscl_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
|
||||
.clk_name = "dout_mfcmscl_mfc",
|
||||
@ -1625,7 +1638,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
|
||||
.gate_clks = peri_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
|
||||
.nr_clk_ids = PERI_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERI,
|
||||
.clk_regs = peri_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
|
||||
.clk_name = "dout_peri_bus",
|
||||
@ -1732,7 +1745,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(core_div_clks),
|
||||
.gate_clks = core_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
|
||||
.nr_clk_ids = CORE_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CORE,
|
||||
.clk_regs = core_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
|
||||
.clk_name = "dout_core_bus",
|
||||
@ -1806,7 +1819,7 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(dpu_div_clks),
|
||||
.gate_clks = dpu_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
|
||||
.nr_clk_ids = DPU_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_DPU,
|
||||
.clk_regs = dpu_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
|
||||
.clk_name = "dout_dpu",
|
||||
|
||||
@ -16,6 +16,17 @@
|
||||
#include "clk.h"
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
|
||||
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
|
||||
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
|
||||
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
|
||||
#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
|
||||
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1)
|
||||
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1)
|
||||
#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1)
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------ */
|
||||
|
||||
/* Register Offset definitions for CMU_TOP (0x1b240000) */
|
||||
@ -941,7 +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
|
||||
.gate_clks = top_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_TOP,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
};
|
||||
@ -1001,7 +1012,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(busmc_div_clks),
|
||||
.gate_clks = busmc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
|
||||
.nr_clk_ids = BUSMC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_BUSMC,
|
||||
.clk_regs = busmc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
|
||||
.clk_name = "dout_clkcmu_busmc_bus",
|
||||
@ -1059,7 +1070,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(core_div_clks),
|
||||
.gate_clks = core_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
|
||||
.nr_clk_ids = CORE_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CORE,
|
||||
.clk_regs = core_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
|
||||
.clk_name = "dout_clkcmu_core_bus",
|
||||
@ -1299,7 +1310,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
|
||||
.gate_clks = fsys0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
|
||||
.nr_clk_ids = FSYS0_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS0,
|
||||
.clk_regs = fsys0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
|
||||
.clk_name = "dout_clkcmu_fsys0_bus",
|
||||
@ -1426,7 +1437,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
|
||||
.gate_clks = fsys1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
|
||||
.nr_clk_ids = FSYS1_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS1,
|
||||
.clk_regs = fsys1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
|
||||
.clk_name = "dout_clkcmu_fsys1_bus",
|
||||
@ -1493,7 +1504,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
|
||||
.gate_clks = fsys2_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
|
||||
.nr_clk_ids = FSYS2_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS2,
|
||||
.clk_regs = fsys2_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
|
||||
.clk_name = "dout_clkcmu_fsys2_bus",
|
||||
@ -1748,7 +1759,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
|
||||
.gate_clks = peric0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
|
||||
.nr_clk_ids = PERIC0_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERIC0,
|
||||
.clk_regs = peric0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
|
||||
.clk_name = "dout_clkcmu_peric0_bus",
|
||||
@ -2003,7 +2014,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
|
||||
.gate_clks = peric1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
|
||||
.nr_clk_ids = PERIC1_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERIC1,
|
||||
.clk_regs = peric1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
|
||||
.clk_name = "dout_clkcmu_peric1_bus",
|
||||
@ -2050,7 +2061,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = {
|
||||
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
|
||||
.gate_clks = peris_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
|
||||
.nr_clk_ids = PERIS_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERIS,
|
||||
.clk_regs = peris_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
|
||||
.clk_name = "dout_clkcmu_peris_bus",
|
||||
|
||||
@ -141,6 +141,7 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
clk_data->num = CLK_NUM;
|
||||
tcon_top->clk_data = clk_data;
|
||||
|
||||
spin_lock_init(&tcon_top->reg_lock);
|
||||
@ -213,8 +214,6 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
|
||||
goto err_unregister_gates;
|
||||
}
|
||||
|
||||
clk_data->num = CLK_NUM;
|
||||
|
||||
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
clk_data);
|
||||
if (ret)
|
||||
|
||||
@ -746,6 +746,7 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np)
|
||||
data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
data->num = 2;
|
||||
|
||||
snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev));
|
||||
init.ops = &qcom_edp_dp_link_clk_ops;
|
||||
@ -765,7 +766,6 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np)
|
||||
|
||||
data->hws[0] = &edp->dp_link_hw;
|
||||
data->hws[1] = &edp->dp_pixel_hw;
|
||||
data->num = 2;
|
||||
|
||||
return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data);
|
||||
}
|
||||
|
||||
@ -256,12 +256,6 @@
|
||||
#define CLK_SCLK_UART2 248
|
||||
#define CLK_SCLK_MMC2 249
|
||||
|
||||
/*
|
||||
* Total number of clocks of main CMU.
|
||||
* NOTE: Must be equal to last clock ID increased by one.
|
||||
*/
|
||||
#define CLK_NR_CLKS 250
|
||||
|
||||
/*
|
||||
* CMU DMC
|
||||
*/
|
||||
@ -283,12 +277,6 @@
|
||||
#define CLK_DIV_DMCP 19
|
||||
#define CLK_DIV_DMCD 20
|
||||
|
||||
/*
|
||||
* Total number of clocks of main CMU.
|
||||
* NOTE: Must be equal to last clock ID increased by one.
|
||||
*/
|
||||
#define NR_CLKS_DMC 21
|
||||
|
||||
/*
|
||||
* CMU ISP
|
||||
*/
|
||||
@ -344,10 +332,4 @@
|
||||
#define CLK_ASYNCAXIM 46
|
||||
#define CLK_SCLK_MPWM_ISP 47
|
||||
|
||||
/*
|
||||
* Total number of clocks of CMU_ISP.
|
||||
* NOTE: Must be equal to last clock ID increased by one.
|
||||
*/
|
||||
#define NR_CLKS_ISP 48
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
|
||||
|
||||
@ -239,9 +239,6 @@
|
||||
#define CLK_DIV_GDR 460
|
||||
#define CLK_DIV_CORE2 461
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 462
|
||||
|
||||
/* Exynos4x12 ISP clocks */
|
||||
#define CLK_ISP_FIMC_ISP 1
|
||||
#define CLK_ISP_FIMC_DRC 2
|
||||
@ -275,6 +272,4 @@
|
||||
#define CLK_ISP_DIV_MCUISP0 29
|
||||
#define CLK_ISP_DIV_MCUISP1 30
|
||||
|
||||
#define CLK_NR_ISP_CLKS 31
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
|
||||
|
||||
@ -177,7 +177,4 @@
|
||||
#define CLK_MOUT_MPLL 1029
|
||||
#define CLK_MOUT_VPLLSRC 1030
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 1031
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
|
||||
|
||||
@ -137,8 +137,6 @@
|
||||
#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122
|
||||
#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123
|
||||
#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124
|
||||
#define TOP_NR_CLK 125
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_EGL */
|
||||
|
||||
@ -153,8 +151,6 @@
|
||||
#define EGL_DOUT_ACLK_EGL 9
|
||||
#define EGL_DOUT_EGL2 10
|
||||
#define EGL_DOUT_EGL1 11
|
||||
#define EGL_NR_CLK 12
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_KFC */
|
||||
|
||||
@ -168,8 +164,6 @@
|
||||
#define KFC_DOUT_KFC_ATCLK 8
|
||||
#define KFC_DOUT_KFC2 9
|
||||
#define KFC_DOUT_KFC1 10
|
||||
#define KFC_NR_CLK 11
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_MIF */
|
||||
|
||||
@ -200,8 +194,6 @@
|
||||
#define MIF_CLK_INTMEM 25
|
||||
#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26
|
||||
#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27
|
||||
#define MIF_NR_CLK 28
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_G3D */
|
||||
|
||||
@ -211,8 +203,6 @@
|
||||
#define G3D_DOUT_ACLK_G3D 4
|
||||
#define G3D_CLK_G3D_HPM 5
|
||||
#define G3D_CLK_G3D 6
|
||||
#define G3D_NR_CLK 7
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_AUD */
|
||||
|
||||
@ -231,8 +221,6 @@
|
||||
#define AUD_SCLK_AUD_UART 13
|
||||
#define AUD_SCLK_PCM 14
|
||||
#define AUD_SCLK_I2S 15
|
||||
#define AUD_NR_CLK 16
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_MFC */
|
||||
|
||||
@ -241,8 +229,6 @@
|
||||
#define MFC_CLK_MFC 3
|
||||
#define MFC_CLK_SMMU2_MFCM1 4
|
||||
#define MFC_CLK_SMMU2_MFCM0 5
|
||||
#define MFC_NR_CLK 6
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_GSCL */
|
||||
|
||||
@ -272,8 +258,6 @@
|
||||
#define GSCL_CLK_SMMU3_MSCL1 24
|
||||
#define GSCL_SCLK_CSIS1_WRAP 25
|
||||
#define GSCL_SCLK_CSIS0_WRAP 26
|
||||
#define GSCL_NR_CLK 27
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_FSYS */
|
||||
|
||||
@ -295,8 +279,6 @@
|
||||
#define FSYS_CLK_SMMU_RTIC 16
|
||||
#define FSYS_PHYCLK_USBDRD30 17
|
||||
#define FSYS_PHYCLK_USBHOST20 18
|
||||
#define FSYS_NR_CLK 19
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_PERI */
|
||||
|
||||
@ -366,8 +348,6 @@
|
||||
#define PERI_SCLK_SPDIF 64
|
||||
#define PERI_SCLK_I2S 65
|
||||
#define PERI_SCLK_PCM1 66
|
||||
#define PERI_NR_CLK 67
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_DISP */
|
||||
|
||||
@ -406,8 +386,6 @@
|
||||
#define DISP_CLK_DP 33
|
||||
#define DISP_SCLK_PIXEL 34
|
||||
#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35
|
||||
#define DISP_NR_CLK 36
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_G2D */
|
||||
|
||||
@ -423,8 +401,6 @@
|
||||
#define G2D_CLK_SMMU_SSS 10
|
||||
#define G2D_CLK_SMMU_MDMA 11
|
||||
#define G2D_CLK_SMMU3_G2D 12
|
||||
#define G2D_NR_CLK 13
|
||||
|
||||
|
||||
/* List Of Clocks For CMU_ISP */
|
||||
|
||||
@ -461,6 +437,5 @@
|
||||
#define ISP_SCLK_SPI0_EXT 31
|
||||
#define ISP_SCLK_SPI1_EXT 32
|
||||
#define ISP_SCLK_UART_EXT 33
|
||||
#define ISP_NR_CLK 34
|
||||
|
||||
#endif
|
||||
|
||||
@ -61,6 +61,4 @@
|
||||
#define CLK_USBD301 367
|
||||
#define CLK_SSS 471
|
||||
|
||||
#define CLK_NR_CLKS 512
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
|
||||
|
||||
@ -271,7 +271,4 @@
|
||||
#define CLK_DOUT_PCLK_DREX0 798
|
||||
#define CLK_DOUT_PCLK_DREX1 799
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 800
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
|
||||
|
||||
@ -188,8 +188,6 @@
|
||||
#define CLK_SCLK_ISP_SPI0_CAM1 252
|
||||
#define CLK_SCLK_HDMI_SPDIF_DISP 253
|
||||
|
||||
#define TOP_NR_CLK 254
|
||||
|
||||
/* CMU_CPIF */
|
||||
#define CLK_FOUT_MPHY_PLL 1
|
||||
|
||||
@ -200,8 +198,6 @@
|
||||
#define CLK_SCLK_MPHY_PLL 11
|
||||
#define CLK_SCLK_UFS_MPHY 11
|
||||
|
||||
#define CPIF_NR_CLK 12
|
||||
|
||||
/* CMU_MIF */
|
||||
#define CLK_FOUT_MEM0_PLL 1
|
||||
#define CLK_FOUT_MEM1_PLL 2
|
||||
@ -396,8 +392,6 @@
|
||||
#define CLK_SCLK_BUS_PLL_APOLLO 199
|
||||
#define CLK_SCLK_BUS_PLL_ATLAS 200
|
||||
|
||||
#define MIF_NR_CLK 201
|
||||
|
||||
/* CMU_PERIC */
|
||||
#define CLK_PCLK_SPI2 1
|
||||
#define CLK_PCLK_SPI1 2
|
||||
@ -468,8 +462,6 @@
|
||||
#define CLK_DIV_SCLK_SCI 70
|
||||
#define CLK_DIV_SCLK_SC_IN 71
|
||||
|
||||
#define PERIC_NR_CLK 72
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_PCLK_HPM_APBIF 1
|
||||
#define CLK_PCLK_TMU1_APBIF 2
|
||||
@ -513,8 +505,6 @@
|
||||
#define CLK_SCLK_ANTIRBK_CNT 40
|
||||
#define CLK_SCLK_OTP_CON 41
|
||||
|
||||
#define PERIS_NR_CLK 42
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_MOUT_ACLK_FSYS_200_USER 1
|
||||
#define CLK_MOUT_SCLK_MMC2_USER 2
|
||||
@ -621,8 +611,6 @@
|
||||
#define CLK_SCLK_USBDRD30 114
|
||||
#define CLK_PCIE 115
|
||||
|
||||
#define FSYS_NR_CLK 116
|
||||
|
||||
/* CMU_G2D */
|
||||
#define CLK_MUX_ACLK_G2D_266_USER 1
|
||||
#define CLK_MUX_ACLK_G2D_400_USER 2
|
||||
@ -653,8 +641,6 @@
|
||||
#define CLK_PCLK_G2D 25
|
||||
#define CLK_PCLK_SMMU_G2D 26
|
||||
|
||||
#define G2D_NR_CLK 27
|
||||
|
||||
/* CMU_DISP */
|
||||
#define CLK_FOUT_DISP_PLL 1
|
||||
|
||||
@ -771,8 +757,6 @@
|
||||
#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
|
||||
#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
|
||||
|
||||
#define DISP_NR_CLK 116
|
||||
|
||||
/* CMU_AUD */
|
||||
#define CLK_MOUT_AUD_PLL_USER 1
|
||||
#define CLK_MOUT_SCLK_AUD_PCM 2
|
||||
@ -824,8 +808,6 @@
|
||||
#define CLK_SCLK_I2S_BCLK 46
|
||||
#define CLK_SCLK_AUD_I2S 47
|
||||
|
||||
#define AUD_NR_CLK 48
|
||||
|
||||
/* CMU_BUS{0|1|2} */
|
||||
#define CLK_DIV_PCLK_BUS_133 1
|
||||
|
||||
@ -840,8 +822,6 @@
|
||||
#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
|
||||
#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
|
||||
|
||||
#define BUSx_NR_CLK 11
|
||||
|
||||
/* CMU_G3D */
|
||||
#define CLK_FOUT_G3D_PLL 1
|
||||
|
||||
@ -865,8 +845,6 @@
|
||||
#define CLK_PCLK_SYSREG_G3D 18
|
||||
#define CLK_SCLK_HPM_G3D 19
|
||||
|
||||
#define G3D_NR_CLK 20
|
||||
|
||||
/* CMU_GSCL */
|
||||
#define CLK_MOUT_ACLK_GSCL_111_USER 1
|
||||
#define CLK_MOUT_ACLK_GSCL_333_USER 2
|
||||
@ -898,8 +876,6 @@
|
||||
#define CLK_PCLK_SMMU_GSCL1 27
|
||||
#define CLK_PCLK_SMMU_GSCL2 28
|
||||
|
||||
#define GSCL_NR_CLK 29
|
||||
|
||||
/* CMU_APOLLO */
|
||||
#define CLK_FOUT_APOLLO_PLL 1
|
||||
|
||||
@ -935,8 +911,6 @@
|
||||
#define CLK_SCLK_HPM_APOLLO 29
|
||||
#define CLK_SCLK_APOLLO 30
|
||||
|
||||
#define APOLLO_NR_CLK 31
|
||||
|
||||
/* CMU_ATLAS */
|
||||
#define CLK_FOUT_ATLAS_PLL 1
|
||||
|
||||
@ -981,8 +955,6 @@
|
||||
#define CLK_ATCLK 38
|
||||
#define CLK_SCLK_ATLAS 39
|
||||
|
||||
#define ATLAS_NR_CLK 40
|
||||
|
||||
/* CMU_MSCL */
|
||||
#define CLK_MOUT_SCLK_JPEG_USER 1
|
||||
#define CLK_MOUT_ACLK_MSCL_400_USER 2
|
||||
@ -1016,8 +988,6 @@
|
||||
#define CLK_PCLK_SMMU_JPEG 28
|
||||
#define CLK_SCLK_JPEG 29
|
||||
|
||||
#define MSCL_NR_CLK 30
|
||||
|
||||
/* CMU_MFC */
|
||||
#define CLK_MOUT_ACLK_MFC_400_USER 1
|
||||
|
||||
@ -1040,8 +1010,6 @@
|
||||
#define CLK_PCLK_SMMU_MFC_1 17
|
||||
#define CLK_PCLK_SMMU_MFC_0 18
|
||||
|
||||
#define MFC_NR_CLK 19
|
||||
|
||||
/* CMU_HEVC */
|
||||
#define CLK_MOUT_ACLK_HEVC_400_USER 1
|
||||
|
||||
@ -1064,8 +1032,6 @@
|
||||
#define CLK_PCLK_SMMU_HEVC_1 17
|
||||
#define CLK_PCLK_SMMU_HEVC_0 18
|
||||
|
||||
#define HEVC_NR_CLK 19
|
||||
|
||||
/* CMU_ISP */
|
||||
#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
|
||||
#define CLK_MOUT_ACLK_ISP_400_USER 2
|
||||
@ -1147,8 +1113,6 @@
|
||||
#define CLK_SCLK_PIXELASYNCS_ISPC 76
|
||||
#define CLK_SCLK_PIXELASYNCM_ISPC 77
|
||||
|
||||
#define ISP_NR_CLK 78
|
||||
|
||||
/* CMU_CAM0 */
|
||||
#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
|
||||
#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
|
||||
@ -1285,8 +1249,6 @@
|
||||
#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
|
||||
#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
|
||||
|
||||
#define CAM0_NR_CLK 134
|
||||
|
||||
/* CMU_CAM1 */
|
||||
#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
|
||||
|
||||
@ -1404,12 +1366,8 @@
|
||||
#define CLK_ATCLK_ISP 111
|
||||
#define CLK_SCLK_ISP_CA5 112
|
||||
|
||||
#define CAM1_NR_CLK 113
|
||||
|
||||
/* CMU_IMEM */
|
||||
#define CLK_ACLK_SLIMSSS 2
|
||||
#define CLK_PCLK_SLIMSSS 35
|
||||
|
||||
#define IMEM_NR_CLK 36
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
|
||||
|
||||
@ -69,7 +69,6 @@
|
||||
#define CLK_GOUT_FSYS_MMC_EMBD 58
|
||||
#define CLK_GOUT_FSYS_MMC_SDIO 59
|
||||
#define CLK_GOUT_FSYS_USB30DRD 60
|
||||
#define TOP_NR_CLK 61
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
@ -86,7 +85,6 @@
|
||||
#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12
|
||||
#define CLK_GOUT_TREX_P_CORE_PCLK 13
|
||||
#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14
|
||||
#define CORE_NR_CLK 15
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_MOUT_PERI_BUS_USER 1
|
||||
@ -132,7 +130,6 @@
|
||||
#define CLK_GOUT_SYSREG_PERI_PCLK 41
|
||||
#define CLK_GOUT_WDT0_PCLK 42
|
||||
#define CLK_GOUT_WDT1_PCLK 43
|
||||
#define PERI_NR_CLK 44
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
@ -146,6 +143,5 @@
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define FSYS_NR_CLK 11
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
|
||||
|
||||
@ -88,7 +88,6 @@
|
||||
#define CLK_MOUT_G3D_SWITCH 76
|
||||
#define CLK_GOUT_G3D_SWITCH 77
|
||||
#define CLK_DOUT_G3D_SWITCH 78
|
||||
#define TOP_NR_CLK 79
|
||||
|
||||
/* CMU_APM */
|
||||
#define CLK_RCO_I3C_PMIC 1
|
||||
@ -115,7 +114,6 @@
|
||||
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
|
||||
#define CLK_GOUT_PMU_ALIVE_PCLK 23
|
||||
#define CLK_GOUT_SYSREG_APM_PCLK 24
|
||||
#define APM_NR_CLK 25
|
||||
|
||||
/* CMU_AUD */
|
||||
#define CLK_DOUT_AUD_AUDIF 1
|
||||
@ -179,7 +177,6 @@
|
||||
#define IOCLK_AUDIOCDCLK6 59
|
||||
#define TICK_USB 60
|
||||
#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
|
||||
#define AUD_NR_CLK 62
|
||||
|
||||
/* CMU_CMGP */
|
||||
#define CLK_RCO_CMGP 1
|
||||
@ -197,7 +194,6 @@
|
||||
#define CLK_GOUT_CMGP_USI1_IPCLK 13
|
||||
#define CLK_GOUT_CMGP_USI1_PCLK 14
|
||||
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
|
||||
#define CMGP_NR_CLK 16
|
||||
|
||||
/* CMU_G3D */
|
||||
#define CLK_FOUT_G3D_PLL 1
|
||||
@ -212,7 +208,6 @@
|
||||
#define CLK_GOUT_G3D_BUSD_CLK 10
|
||||
#define CLK_GOUT_G3D_BUSP_CLK 11
|
||||
#define CLK_GOUT_G3D_SYSREG_PCLK 12
|
||||
#define G3D_NR_CLK 13
|
||||
|
||||
/* CMU_HSI */
|
||||
#define CLK_MOUT_HSI_BUS_USER 1
|
||||
@ -231,7 +226,6 @@
|
||||
#define CLK_GOUT_HSI_PPMU_ACLK 14
|
||||
#define CLK_GOUT_HSI_PPMU_PCLK 15
|
||||
#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
|
||||
#define HSI_NR_CLK 17
|
||||
|
||||
/* CMU_IS */
|
||||
#define CLK_MOUT_IS_BUS_USER 1
|
||||
@ -257,7 +251,6 @@
|
||||
#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
|
||||
#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
|
||||
#define CLK_GOUT_IS_SYSREG_PCLK 23
|
||||
#define IS_NR_CLK 24
|
||||
|
||||
/* CMU_MFCMSCL */
|
||||
#define CLK_MOUT_MFCMSCL_MFC_USER 1
|
||||
@ -275,7 +268,6 @@
|
||||
#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
|
||||
#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
|
||||
#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
|
||||
#define MFCMSCL_NR_CLK 16
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_MOUT_PERI_BUS_USER 1
|
||||
@ -312,7 +304,6 @@
|
||||
#define CLK_GOUT_UART_PCLK 32
|
||||
#define CLK_GOUT_WDT0_PCLK 33
|
||||
#define CLK_GOUT_WDT1_PCLK 34
|
||||
#define PERI_NR_CLK 35
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
@ -329,7 +320,6 @@
|
||||
#define CLK_GOUT_SSS_PCLK 12
|
||||
#define CLK_GOUT_GPIO_CORE_PCLK 13
|
||||
#define CLK_GOUT_SYSREG_CORE_PCLK 14
|
||||
#define CORE_NR_CLK 15
|
||||
|
||||
/* CMU_DPU */
|
||||
#define CLK_MOUT_DPU_USER 1
|
||||
|
||||
@ -164,4 +164,32 @@
|
||||
|
||||
#define IMX_ADMA_LPCG_CLK_END 45
|
||||
|
||||
#define IMX_ADMA_ACM_AUD_CLK0_SEL 0
|
||||
#define IMX_ADMA_ACM_AUD_CLK1_SEL 1
|
||||
#define IMX_ADMA_ACM_MCLKOUT0_SEL 2
|
||||
#define IMX_ADMA_ACM_MCLKOUT1_SEL 3
|
||||
#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4
|
||||
#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5
|
||||
#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6
|
||||
#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7
|
||||
#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8
|
||||
#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9
|
||||
#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10
|
||||
#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11
|
||||
#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12
|
||||
#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13
|
||||
#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14
|
||||
#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15
|
||||
#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16
|
||||
#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17
|
||||
#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18
|
||||
#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19
|
||||
#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20
|
||||
#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21
|
||||
#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22
|
||||
#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23
|
||||
#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24
|
||||
|
||||
#define IMX_ADMA_ACM_CLK_END 25
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
|
||||
|
||||
@ -130,7 +130,7 @@
|
||||
#define IMX8MP_CLK_SAI1 123
|
||||
#define IMX8MP_CLK_SAI2 124
|
||||
#define IMX8MP_CLK_SAI3 125
|
||||
#define IMX8MP_CLK_SAI4 126
|
||||
/* #define IMX8MP_CLK_SAI4 126 */
|
||||
#define IMX8MP_CLK_SAI5 127
|
||||
#define IMX8MP_CLK_SAI6 128
|
||||
#define IMX8MP_CLK_ENET_QOS 129
|
||||
|
||||
@ -203,6 +203,7 @@
|
||||
#define IMX93_CLK_ARM_PLL 198
|
||||
#define IMX93_CLK_A55_SEL 199
|
||||
#define IMX93_CLK_A55_CORE 200
|
||||
#define IMX93_CLK_END 201
|
||||
#define IMX93_CLK_PDM_IPG 201
|
||||
#define IMX93_CLK_END 202
|
||||
|
||||
#endif
|
||||
|
||||
@ -6,5 +6,4 @@
|
||||
#define MMP2_CLK_AUDIO_SSPA0 1
|
||||
#define MMP2_CLK_AUDIO_SSPA1 2
|
||||
|
||||
#define MMP2_CLK_AUDIO_NR_CLKS 3
|
||||
#endif
|
||||
|
||||
@ -91,5 +91,4 @@
|
||||
#define MMP3_CLK_SDH4 126
|
||||
#define MMP2_CLK_AUDIO 127
|
||||
|
||||
#define MMP2_NR_CLKS 200
|
||||
#endif
|
||||
|
||||
@ -63,5 +63,4 @@
|
||||
#define PXA168_CLK_SDH01_AXI 111
|
||||
#define PXA168_CLK_SDH23_AXI 112
|
||||
|
||||
#define PXA168_NR_CLKS 200
|
||||
#endif
|
||||
|
||||
@ -36,7 +36,6 @@
|
||||
#define PXA1928_CLK_THSENS_CPU 0x26
|
||||
#define PXA1928_CLK_THSENS_VPU 0x27
|
||||
#define PXA1928_CLK_THSENS_GC 0x28
|
||||
#define PXA1928_APBC_NR_CLKS 0x30
|
||||
|
||||
|
||||
/* axi peripherals */
|
||||
@ -53,6 +52,4 @@
|
||||
#define PXA1928_CLK_GC3D 0x5d
|
||||
#define PXA1928_CLK_GC2D 0x5f
|
||||
|
||||
#define PXA1928_APMU_NR_CLKS 0x60
|
||||
|
||||
#endif
|
||||
|
||||
@ -55,5 +55,4 @@
|
||||
#define PXA910_CLK_CCIC0_PHY 108
|
||||
#define PXA910_CLK_CCIC0_SPHY 109
|
||||
|
||||
#define PXA910_NR_CLKS 200
|
||||
#endif
|
||||
|
||||
@ -166,16 +166,12 @@
|
||||
#define GOUT_CLKCMU_PERIC1_IP 248
|
||||
#define GOUT_CLKCMU_PERIS_BUS 249
|
||||
|
||||
#define TOP_NR_CLK 250
|
||||
|
||||
/* CMU_BUSMC */
|
||||
#define CLK_MOUT_BUSMC_BUS_USER 1
|
||||
#define CLK_DOUT_BUSMC_BUSP 2
|
||||
#define CLK_GOUT_BUSMC_PDMA0_PCLK 3
|
||||
#define CLK_GOUT_BUSMC_SPDMA_PCLK 4
|
||||
|
||||
#define BUSMC_NR_CLK 5
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
#define CLK_DOUT_CORE_BUSP 2
|
||||
@ -183,8 +179,6 @@
|
||||
#define CLK_GOUT_CORE_CCI_PCLK 4
|
||||
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
|
||||
|
||||
#define CORE_NR_CLK 6
|
||||
|
||||
/* CMU_FSYS0 */
|
||||
#define CLK_MOUT_FSYS0_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS0_PCIE_USER 2
|
||||
@ -226,8 +220,6 @@
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
|
||||
#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
|
||||
|
||||
#define FSYS0_NR_CLK 37
|
||||
|
||||
/* CMU_FSYS1 */
|
||||
#define FOUT_MMC_PLL 1
|
||||
|
||||
@ -251,8 +243,6 @@
|
||||
#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
|
||||
#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
|
||||
|
||||
#define FSYS1_NR_CLK 19
|
||||
|
||||
/* CMU_FSYS2 */
|
||||
#define CLK_MOUT_FSYS2_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
|
||||
@ -262,8 +252,6 @@
|
||||
#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6
|
||||
#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7
|
||||
|
||||
#define FSYS2_NR_CLK 8
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC0_IP_USER 2
|
||||
@ -308,8 +296,6 @@
|
||||
#define CLK_GOUT_PERIC0_PCLK_10 42
|
||||
#define CLK_GOUT_PERIC0_PCLK_11 43
|
||||
|
||||
#define PERIC0_NR_CLK 44
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC1_IP_USER 2
|
||||
@ -354,14 +340,10 @@
|
||||
#define CLK_GOUT_PERIC1_PCLK_10 42
|
||||
#define CLK_GOUT_PERIC1_PCLK_11 43
|
||||
|
||||
#define PERIC1_NR_CLK 44
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_BUS_USER 1
|
||||
#define CLK_GOUT_SYSREG_PERIS_PCLK 2
|
||||
#define CLK_GOUT_WDT_CLUSTER0 3
|
||||
#define CLK_GOUT_WDT_CLUSTER1 4
|
||||
|
||||
#define PERIS_NR_CLK 5
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
|
||||
|
||||
@ -1379,7 +1379,7 @@ struct clk_onecell_data {
|
||||
|
||||
struct clk_hw_onecell_data {
|
||||
unsigned int num;
|
||||
struct clk_hw *hws[];
|
||||
struct clk_hw *hws[] __counted_by(num);
|
||||
};
|
||||
|
||||
#define CLK_OF_DECLARE(name, compat, fn) \
|
||||
|
||||
@ -1,18 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __CLK_MMP_H
|
||||
#define __CLK_MMP_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
extern void pxa168_clk_init(phys_addr_t mpmu_phys,
|
||||
phys_addr_t apmu_phys,
|
||||
phys_addr_t apbc_phys);
|
||||
extern void pxa910_clk_init(phys_addr_t mpmu_phys,
|
||||
phys_addr_t apmu_phys,
|
||||
phys_addr_t apbc_phys,
|
||||
phys_addr_t apbcp_phys);
|
||||
extern void mmp2_clk_init(phys_addr_t mpmu_phys,
|
||||
phys_addr_t apmu_phys,
|
||||
phys_addr_t apbc_phys);
|
||||
|
||||
#endif
|
||||
@ -22,6 +22,7 @@
|
||||
#define IMX_CHIP_REVISION_3_3 0x33
|
||||
#define IMX_CHIP_REVISION_UNKNOWN 0xff
|
||||
|
||||
int mx25_revision(void);
|
||||
int mx27_revision(void);
|
||||
int mx31_revision(void);
|
||||
int mx35_revision(void);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user