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arm: iop13xx: Use sparse irqs for MSI

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No need for a private allocator. The core code handles it
already. 

Allocate the non MSI irqs right at boot time via machine_desc->nr_irqs
and let the sparse core handle the MSI space.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20140507154333.809210026@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner 2014-05-07 15:44:04 +00:00
parent 67bb90fd74
commit 37ebbcff78
8 changed files with 19 additions and 42 deletions
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1
arch/arm/Kconfig
View File

@ -480,6 +480,7 @@ config ARCH_IOP13XX
select PCI
select PLAT_IOP
select VMSPLIT_1G
select SPARSE_IRQ
help
Support for Intel's IOP13XX (XScale) family of processors.

2
arch/arm/mach-iop13xx/include/mach/irqs.h
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@ -191,6 +191,4 @@ static inline u32 read_intpnd_3(void)
#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
#endif
#define NR_IRQS NR_IOP13XX_IRQS
#endif /* _IOP13XX_IRQ_H_ */

3
arch/arm/mach-iop13xx/include/mach/time.h
View File

@ -1,5 +1,8 @@
#ifndef _IOP13XX_TIME_H_
#define _IOP13XX_TIME_H_
#include <mach/irqs.h>
#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
#define IOP_TMR_EN 0x02

1
arch/arm/mach-iop13xx/iq81340mc.c
View File

@ -93,4 +93,5 @@ MACHINE_START(IQ81340MC, "Intel IQ81340MC")
.init_time = iq81340mc_timer_init,
.init_machine = iq81340mc_init,
.restart = iop13xx_restart,
.nr_irqs = NR_IOP13XX_IRQS,
MACHINE_END

1
arch/arm/mach-iop13xx/iq81340sc.c
View File

@ -95,4 +95,5 @@ MACHINE_START(IQ81340SC, "Intel IQ81340SC")
.init_time = iq81340sc_timer_init,
.init_machine = iq81340sc_init,
.restart = iop13xx_restart,
.nr_irqs = NR_IOP13XX_IRQS,
MACHINE_END

51
arch/arm/mach-iop13xx/msi.c
View File

@ -24,10 +24,6 @@
#include <asm/mach/irq.h>
#include <asm/irq.h>
#define IOP13XX_NUM_MSI_IRQS 128
static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
/* IMIPR0 CP6 R8 Page 1
*/
static u32 read_imipr_0(void)
@ -121,41 +117,6 @@ void __init iop13xx_msi_init(void)
irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
}
/*
* Dynamic irq allocate and deallocation
*/
int create_irq(void)
{
int irq, pos;
again:
pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
irq = IRQ_IOP13XX_MSI_0 + pos;
if (irq > NR_IRQS)
return -ENOSPC;
/* test_and_set_bit operates on 32-bits at a time */
if (test_and_set_bit(pos, msi_irq_in_use))
goto again;
dynamic_irq_init(irq);
return irq;
}
void destroy_irq(unsigned int irq)
{
int pos = irq - IRQ_IOP13XX_MSI_0;
dynamic_irq_cleanup(irq);
clear_bit(pos, msi_irq_in_use);
}
void arch_teardown_msi_irq(unsigned int irq)
{
destroy_irq(irq);
}
static void iop13xx_msi_nop(struct irq_data *d)
{
return;
@ -172,12 +133,17 @@ static struct irq_chip iop13xx_msi_chip = {
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
int id, irq = create_irq();
int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
struct msi_msg msg;
if (irq < 0)
return irq;
if (irq >= NR_IOP13XX_IRQS) {
irq_free_desc(irq);
return -ENOSPC;
}
irq_set_msi_desc(irq, desc);
msg.address_hi = 0x0;
@ -191,3 +157,8 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
return 0;
}
void arch_teardown_msi_irq(unsigned int irq)
{
irq_free_desc(irq);
}

1
arch/arm/mach-iop13xx/setup.c
View File

@ -27,6 +27,7 @@
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/hardware/iop_adma.h>
#include <mach/irqs.h>
#define IOP13XX_UART_XTAL 33334000
#define IOP13XX_SETUP_DEBUG 0

1
arch/arm/mach-iop13xx/tpmi.c
View File

@ -24,6 +24,7 @@
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <mach/irqs.h>
/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))