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stmmac: Replace infinite loops by timeouts in mdio r/w

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This patch removes the infinite waits from the mdio read and
write interfaces. These infinite waits have been replaced by
the timeout handling. In case if a time out occurs, an error is
returned.

Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Deepak SIKRI 2012-04-04 04:33:24 +00:00 committed by David S. Miller
parent 8327eb65e7
commit 39b401dbd3
1 changed files with 25 additions and 7 deletions
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32
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
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@ -34,6 +34,22 @@
#define MII_BUSY 0x00000001 #define MII_BUSY 0x00000001
#define MII_WRITE 0x00000002 #define MII_WRITE 0x00000002
static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
{
unsigned long curr;
unsigned long finish = jiffies + 3 * HZ;
do {
curr = jiffies;
if (readl(ioaddr + mii_addr) & MII_BUSY)
cpu_relax();
else
return 0;
} while (!time_after_eq(curr, finish));
return -EBUSY;
}
/** /**
* stmmac_mdio_read * stmmac_mdio_read
* @bus: points to the mii_bus structure * @bus: points to the mii_bus structure
@ -56,9 +72,13 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
((phyreg << 6) & (0x000007C0))); ((phyreg << 6) & (0x000007C0)));
regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
return -EBUSY;
writel(regValue, priv->ioaddr + mii_address); writel(regValue, priv->ioaddr + mii_address);
do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
return -EBUSY;
/* Read the data from the MII data register */ /* Read the data from the MII data register */
data = (int)readl(priv->ioaddr + mii_data); data = (int)readl(priv->ioaddr + mii_data);
@ -88,18 +108,16 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
/* Wait until any existing MII operation is complete */ /* Wait until any existing MII operation is complete */
do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
return -EBUSY;
/* Set the MII address register to write */ /* Set the MII address register to write */
writel(phydata, priv->ioaddr + mii_data); writel(phydata, priv->ioaddr + mii_data);
writel(value, priv->ioaddr + mii_address); writel(value, priv->ioaddr + mii_address);
/* Wait until any existing MII operation is complete */ /* Wait until any existing MII operation is complete */
do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
return 0;
} }
/** /**