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soc: fixes for 6.13, part 2
Two more small fixes, correcting the cacheline size on Raspberry Pi 5 and fixing a logic mistake in the microchip mpfs firmware driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmdnPmkACgkQYKtH/8kJ UicYsw//V/P84VpktPuSbZ4Uy41ns35DNmkSmZRGl5qTjTND6yjdl1ZkngzhHfC5 7yrq6OcHseErfUsv4OKpRYtsmSEl/hJcVKQTKP3m9qZ+TCpym0bmQc+pbnbNtwXI 1Um9Y5QL0yKw60elNW4ysJ+vUGlgMBIQG0gtz4aNu0BeLR2pEbs+WsodTm0z5Z8j AptHtB2Z1+ODM+uxJ44sVEd+uyC8cc3u8yWgMKNXVTPbI9xGm7IOoXb95rJGyFid WLgyU7ZDvPOMUwwbsp87bY0PUP8fQpMrxqnz51/TbzJiMs1U6Ikmg4imIPjAemh0 yb+8sH8M1mY8nV4efP/W5BEftGo1fc1yrzlEkb0Bgds10Ys4ra2JI/s5QJ7VOAY9 pZ/ajSiGjQ9elvd/es4KKbKwDnlccw77TaauKEkTyD6ZVmNZR7/s8IZ2/Zy//k3A 2bXP07GSgSH7Z5FUB3ExlDWRGoqjmzF9z8D7x3/MTL1pmWImXfDcclzAA5lj9yhM /LkploVbEcZ5ArV7oISu7GUfrxsxLNgobzEVUt2iRylw18YZJFFcvTlez5R0n4Zg fMiVW+fhpun5FJkGDL3B/BU2c+RUkL0RiIwElnUOBRXIrRyI4XjCTbw9vnPKZxHk XQkV+OZzlogq3TdtHqJ94Nwt3UKzSSMF4aAVOvcAzusHjMnyBdk= =UZKA -----END PGP SIGNATURE----- Merge tag 'soc-fixes-6.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "Two more small fixes, correcting the cacheline size on Raspberry Pi 5 and fixing a logic mistake in the microchip mpfs firmware driver" * tag 'soc-fixes-6.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5 firmware: microchip: fix UL_IAP lock check in mpfs_auto_update_state()
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commit
48f506ad0b
@ -67,7 +67,7 @@ cpu0: cpu@0 {
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l2_cache_l0: l2-cache-l0 {
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l2_cache_l0: l2-cache-l0 {
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compatible = "cache";
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compatible = "cache";
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cache-size = <0x80000>;
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-level = <2>;
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cache-unified;
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cache-unified;
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@ -91,7 +91,7 @@ cpu1: cpu@1 {
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l2_cache_l1: l2-cache-l1 {
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l2_cache_l1: l2-cache-l1 {
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compatible = "cache";
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compatible = "cache";
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cache-size = <0x80000>;
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-level = <2>;
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cache-unified;
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cache-unified;
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@ -115,7 +115,7 @@ cpu2: cpu@2 {
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l2_cache_l2: l2-cache-l2 {
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l2_cache_l2: l2-cache-l2 {
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compatible = "cache";
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compatible = "cache";
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cache-size = <0x80000>;
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-level = <2>;
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cache-unified;
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cache-unified;
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@ -139,7 +139,7 @@ cpu3: cpu@3 {
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l2_cache_l3: l2-cache-l3 {
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l2_cache_l3: l2-cache-l3 {
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compatible = "cache";
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compatible = "cache";
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cache-size = <0x80000>;
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-line-size = <64>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-level = <2>;
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cache-unified;
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cache-unified;
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@ -402,10 +402,10 @@ static int mpfs_auto_update_available(struct mpfs_auto_update_priv *priv)
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return -EIO;
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return -EIO;
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/*
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/*
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* Bit 5 of byte 1 is "UL_Auto Update" & if it is set, Auto Update is
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* Bit 5 of byte 1 is "UL_IAP" & if it is set, Auto Update is
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* not possible.
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* not possible.
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*/
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*/
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if (response_msg[1] & AUTO_UPDATE_FEATURE_ENABLED)
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if ((((u8 *)response_msg)[1] & AUTO_UPDATE_FEATURE_ENABLED))
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return -EPERM;
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return -EPERM;
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return 0;
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return 0;
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