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clocksource/drivers/arc_timer: Eliminate redefined macro error
In drivers/clocksource/, 3 drivers use "TIMER_CTRL_IE" with 3 different
values. Two of them (mps2-timer.c and timer-sp804.c/timer-sp.h) are
localized and left unmodifed.
One of them uses a shared header file (<soc/arc/timers.h>), which is
what is causing the "redefined" warnings, so change the macro name in
that driver only. Also change the TIMER_CTRL_NH macro name.
Both macro names are prefixed with "ARC_" to reduce the likelihood
of future name collisions.
In file included from ../drivers/clocksource/timer-sp804.c:24:
../drivers/clocksource/timer-sp.h:25: error: "TIMER_CTRL_IE" redefined [-Werror]
25 | #define TIMER_CTRL_IE (1 << 5) /* VR */
../include/soc/arc/timers.h:20: note: this is the location of the previous definition
20 | #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
Fixes: b26c2e3823
("ARC: breakout timer include code into separate header")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Vineet Gupta <vgupta@kernel.org>
Cc: linux-snps-arc@lists.infradead.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shahab Vahedi <Shahab.Vahedi@synopsys.com>
Acked-by: Vineet Gupta <vgupta@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20210924020825.20317-1-rdunlap@infradead.org
This commit is contained in:
parent
d25a025201
commit
58100c34f7
@ -225,7 +225,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node)
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH);
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sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
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sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
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@ -245,7 +245,7 @@ static void arc_timer_event_setup(unsigned int cycles)
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write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
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write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH);
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}
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}
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@ -294,7 +294,7 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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* explicitly clears IP bit
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* explicitly clears IP bit
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* 2. Re-arm interrupt if periodic by writing to IE bit [0]
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* 2. Re-arm interrupt if periodic by writing to IE bit [0]
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*/
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*/
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH);
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evt->event_handler(evt);
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evt->event_handler(evt);
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@ -17,8 +17,8 @@
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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/* CTRL reg bits */
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/* CTRL reg bits */
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#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
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#define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMERN_MAX 0xFFFFFFFF
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#define ARC_TIMERN_MAX 0xFFFFFFFF
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