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spi: stm32: use bitfield macros

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To avoid defining shift and mask separately and hand-coding the bit
manipulation, use the bitfield macros.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/1612551572-495-4-git-send-email-alain.volmat@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Amelie Delaunay 2021-02-05 19:59:27 +01:00 committed by Mark Brown
parent 8f8d0e3e33
commit 5a380b833a
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 18 additions and 36 deletions
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54
drivers/spi/spi-stm32.c
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@ -5,6 +5,7 @@
// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/clk.h>
#include <linux/delay.h>
@ -94,27 +95,22 @@
#define STM32H7_SPI_CR1_SSI BIT(12)
/* STM32H7_SPI_CR2 bit fields */
#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
/* STM32H7_SPI_CFG1 bit fields */
#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR_MIN 0
#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32H7_SPI_CFG2 bit fields */
#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
#define STM32H7_SPI_CFG2_COMM_SHIFT 17
#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
#define STM32H7_SPI_CFG2_SP_SHIFT 19
#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
#define STM32H7_SPI_CFG2_MASTER BIT(22)
#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
@ -140,7 +136,6 @@
#define STM32H7_SPI_SR_OVR BIT(6)
#define STM32H7_SPI_SR_MODF BIT(9)
#define STM32H7_SPI_SR_SUSP BIT(11)
#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
#define STM32H7_SPI_SR_RXWNE BIT(15)
@ -417,9 +412,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
STM32H7_SPI_CFG1_DSIZE_SHIFT;
max_bpw += 1;
max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
spin_unlock_irqrestore(&spi->lock, flags);
@ -587,8 +580,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
{
u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
STM32H7_SPI_SR_RXPLVL_SHIFT;
u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
while ((spi->rx_len > 0) &&
((sr & STM32H7_SPI_SR_RXP) ||
@ -615,8 +607,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
}
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
STM32H7_SPI_SR_RXPLVL_SHIFT;
rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
}
dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@ -1385,15 +1376,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
bpw = spi->cur_bpw - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
STM32H7_SPI_CFG1_DSIZE;
cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
STM32H7_SPI_CFG1_FTHLV;
cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
@ -1411,8 +1400,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
u32 clrb = 0, setb = 0;
clrb |= spi->cfg->regs->br.mask;
setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
spi->cfg->regs->br.mask;
setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
~clrb) | setb,
@ -1503,8 +1491,7 @@ static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
}
cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
STM32H7_SPI_CFG2_COMM;
cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
@ -1527,14 +1514,15 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
if ((len > 1) && (spi->cur_midi > 0)) {
u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
(u32)STM32H7_SPI_CFG2_MIDI >>
STM32H7_SPI_CFG2_MIDI_SHIFT);
u32 midi = min_t(u32,
DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
FIELD_GET(STM32H7_SPI_CFG2_MIDI,
STM32H7_SPI_CFG2_MIDI));
dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
sck_period_ns, midi, midi * sck_period_ns);
cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
STM32H7_SPI_CFG2_MIDI;
cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
}
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
@ -1549,14 +1537,8 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
*/
static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
{
u32 cr2_clrb = 0, cr2_setb = 0;
if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
STM32H7_SPI_CR2_TSIZE_SHIFT)) {
cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
~cr2_clrb) | cr2_setb,
if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
spi->base + STM32H7_SPI_CR2);
} else {
return -EMSGSIZE;