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clk: cygnus: add clock support for Broadcom Cygnus
The Broadcom Cygnus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied from an onboard crystal. Cygnus also has various ASIU clocks that are derived directly from the onboard crystal. Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
Ray Jui
Michael Turquette
parent
69a0b2c559
commit
61ca7b0c7f
@ -3,3 +3,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
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obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
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265
drivers/clk/bcm/clk-cygnus.c
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265
drivers/clk/bcm/clk-cygnus.c
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@ -0,0 +1,265 @@
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/*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clkdev.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <dt-bindings/clock/bcm-cygnus.h>
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#include "clk-iproc.h"
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#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
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#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
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#define asiu_div_val(o, es, hs, hw, ls, lw) \
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{ .offset = o, .en_shift = es, .high_shift = hs, \
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.high_width = hw, .low_shift = ls, .low_width = lw }
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#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
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.reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
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.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
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#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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.hold_shift = hs, .bypass_shift = bs }
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#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
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static void __init cygnus_armpll_init(struct device_node *node)
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{
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iproc_armpll_setup(node);
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}
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CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
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static const struct iproc_pll_ctrl genpll = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_PLL_NEEDS_SW_CFG,
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.aon = aon_val(0x0, 2, 1, 0),
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.reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
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.sw_ctrl = sw_ctrl_val(0x10, 31),
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.ndiv_int = reg_val(0x10, 20, 10),
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.ndiv_frac = reg_val(0x10, 0, 20),
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.pdiv = reg_val(0x14, 0, 4),
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.vco_ctrl = vco_ctrl_val(0x18, 0x1c),
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.status = reg_val(0x28, 12, 1),
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};
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static const struct iproc_clk_ctrl genpll_clk[] = {
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[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x4, 6, 0, 12),
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.mdiv = reg_val(0x20, 0, 8),
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},
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[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x4, 7, 1, 13),
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.mdiv = reg_val(0x20, 10, 8),
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},
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[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x4, 8, 2, 14),
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.mdiv = reg_val(0x20, 20, 8),
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},
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[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x4, 9, 3, 15),
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.mdiv = reg_val(0x24, 0, 8),
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},
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[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x4, 10, 4, 16),
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.mdiv = reg_val(0x24, 10, 8),
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},
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[BCM_CYGNUS_GENPLL_CAN_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_CAN_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x4, 11, 5, 17),
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.mdiv = reg_val(0x24, 20, 8),
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},
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};
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static void __init cygnus_genpll_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
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ARRAY_SIZE(genpll_clk));
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}
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CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
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static const struct iproc_pll_ctrl lcpll0 = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
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.aon = aon_val(0x0, 2, 5, 4),
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.reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
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.sw_ctrl = sw_ctrl_val(0x4, 31),
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.ndiv_int = reg_val(0x4, 16, 10),
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.pdiv = reg_val(0x4, 26, 4),
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.vco_ctrl = vco_ctrl_val(0x10, 0x14),
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.status = reg_val(0x18, 12, 1),
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};
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static const struct iproc_clk_ctrl lcpll0_clk[] = {
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[BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x0, 7, 1, 13),
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.mdiv = reg_val(0x8, 0, 8),
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},
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[BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x0, 8, 2, 14),
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.mdiv = reg_val(0x8, 10, 8),
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},
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[BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x0, 9, 3, 15),
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.mdiv = reg_val(0x8, 20, 8),
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},
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[BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x0, 10, 4, 16),
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.mdiv = reg_val(0xc, 0, 8),
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},
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[BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x0, 11, 5, 17),
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.mdiv = reg_val(0xc, 10, 8),
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},
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[BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
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.channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = enable_val(0x0, 12, 6, 18),
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.mdiv = reg_val(0xc, 20, 8),
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},
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};
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static void __init cygnus_lcpll0_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
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ARRAY_SIZE(lcpll0_clk));
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}
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CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
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/*
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* MIPI PLL VCO frequency parameter table
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*/
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static const struct iproc_pll_vco_param mipipll_vco_params[] = {
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/* rate (Hz) ndiv_int ndiv_frac pdiv */
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{ 750000000UL, 30, 0, 1 },
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{ 1000000000UL, 40, 0, 1 },
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{ 1350000000ul, 54, 0, 1 },
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{ 2000000000UL, 80, 0, 1 },
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{ 2100000000UL, 84, 0, 1 },
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{ 2250000000UL, 90, 0, 1 },
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{ 2500000000UL, 100, 0, 1 },
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{ 2700000000UL, 54, 0, 0 },
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{ 2975000000UL, 119, 0, 1 },
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{ 3100000000UL, 124, 0, 1 },
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{ 3150000000UL, 126, 0, 1 },
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};
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static const struct iproc_pll_ctrl mipipll = {
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.flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_NEEDS_READ_BACK,
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.aon = aon_val(0x0, 4, 17, 16),
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.asiu = asiu_gate_val(0x0, 3),
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.reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
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.ndiv_int = reg_val(0x10, 20, 10),
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.ndiv_frac = reg_val(0x10, 0, 20),
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.pdiv = reg_val(0x14, 0, 4),
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.vco_ctrl = vco_ctrl_val(0x18, 0x1c),
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.status = reg_val(0x28, 12, 1),
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};
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static const struct iproc_clk_ctrl mipipll_clk[] = {
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[BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = enable_val(0x4, 12, 6, 18),
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.mdiv = reg_val(0x20, 0, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = enable_val(0x4, 13, 7, 19),
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.mdiv = reg_val(0x20, 10, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = enable_val(0x4, 14, 8, 20),
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.mdiv = reg_val(0x20, 20, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = enable_val(0x4, 15, 9, 21),
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.mdiv = reg_val(0x24, 0, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = enable_val(0x4, 16, 10, 22),
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.mdiv = reg_val(0x24, 10, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = enable_val(0x4, 17, 11, 23),
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.mdiv = reg_val(0x24, 20, 8),
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},
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};
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static void __init cygnus_mipipll_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params,
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ARRAY_SIZE(mipipll_vco_params), mipipll_clk,
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ARRAY_SIZE(mipipll_clk));
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}
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CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
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static const struct iproc_asiu_div asiu_div[] = {
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[BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10),
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[BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10),
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[BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10),
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};
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static const struct iproc_asiu_gate asiu_gate[] = {
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[BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7),
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[BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9),
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[BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0),
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};
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static void __init cygnus_asiu_init(struct device_node *node)
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{
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iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div));
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}
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CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
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68
include/dt-bindings/clock/bcm-cygnus.h
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68
include/dt-bindings/clock/bcm-cygnus.h
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@ -0,0 +1,68 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_BCM_CYGNUS_H
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#define _CLOCK_BCM_CYGNUS_H
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/* GENPLL clock ID */
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#define BCM_CYGNUS_GENPLL 0
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#define BCM_CYGNUS_GENPLL_AXI21_CLK 1
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#define BCM_CYGNUS_GENPLL_250MHZ_CLK 2
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#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 3
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#define BCM_CYGNUS_GENPLL_ENET_SW_CLK 4
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#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK 5
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#define BCM_CYGNUS_GENPLL_CAN_CLK 6
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/* LCPLL0 clock ID */
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#define BCM_CYGNUS_LCPLL0 0
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#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 1
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#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 2
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#define BCM_CYGNUS_LCPLL0_SDIO_CLK 3
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#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 4
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#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 5
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#define BCM_CYGNUS_LCPLL0_CH5_UNUSED 6
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/* MIPI PLL clock ID */
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#define BCM_CYGNUS_MIPIPLL 0
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#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED 1
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#define BCM_CYGNUS_MIPIPLL_CH1_LCD 2
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#define BCM_CYGNUS_MIPIPLL_CH2_V3D 3
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#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED 4
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#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED 5
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#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED 6
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/* ASIU clock ID */
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#define BCM_CYGNUS_ASIU_KEYPAD_CLK 0
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#define BCM_CYGNUS_ASIU_ADC_CLK 1
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#define BCM_CYGNUS_ASIU_PWM_CLK 2
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#endif /* _CLOCK_BCM_CYGNUS_H */
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