mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-18 02:46:06 +00:00
clk: renesas: Updates for v5.14
- Add support for CPU core clock boost modes on R-Car Gen3,
- Add ISPCS (Image Signal Processor) clocks on R-Car V3U,
- Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate(),
and improve support for multiple parents,
- Switch RZ/N1 divider clocks to .determine_rate(),
- Add ZA2 (Audio Clock Generator) clock on R-Car D3,
- Minor fixes and improvements.
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Merge tag 'renesas-clk-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for CPU core clock boost modes on R-Car Gen3
- Add ISPCS (Image Signal Processor) clocks on R-Car V3U
- Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate()
and improve support for multiple parents
- Switch RZ/N1 divider clocks to .determine_rate()
- Add ZA2 (Audio Clock Generator) clock on R-Car D3
- Minor fixes and improvements
* tag 'renesas-clk-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a77995: Add ZA2 clock
clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
clk: renesas: r9a06g032: Switch to .determine_rate()
clk: renesas: div6: Implement range checking
clk: renesas: div6: Consider all parents for requested rate
clk: renesas: div6: Switch to .determine_rate()
clk: renesas: div6: Simplify src mask handling
clk: renesas: div6: Use clamp() instead of clamp_t()
clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()
clk: renesas: r8a779a0: Add ISPCS clocks
clk: renesas: rcar-gen3: Add boost support to Z clocks
clk: renesas: rcar-gen3: Add custom clock for PLLs
clk: renesas: rcar-gen3: Increase Z clock accuracy
clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/
clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()
clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32
clk: renesas: rcar-gen3: Update Z clock rate formula in comments
This commit is contained in:
Stephen Boyd
commit
6435c49913
@ -28,8 +28,7 @@
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* @hw: handle between common and hardware-specific interfaces
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* @reg: IO-remapped register
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* @div: divisor value (1-64)
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* @src_shift: Shift to access the register bits to select the parent clock
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* @src_width: Number of register bits to select the parent clock (may be 0)
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* @src_mask: Bitmask covering the register bits to select the parent clock
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* @nb: Notifier block to save/restore clock state for system resume
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* @parents: Array to map from valid parent clocks indices to hardware indices
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*/
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@ -37,8 +36,7 @@ struct div6_clock {
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struct clk_hw hw;
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void __iomem *reg;
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unsigned int div;
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u32 src_shift;
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u32 src_width;
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u32 src_mask;
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struct notifier_block nb;
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u8 parents[];
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};
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@ -99,15 +97,52 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
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rate = 1;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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return clamp_t(unsigned int, div, 1, 64);
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return clamp(div, 1U, 64U);
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}
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static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
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unsigned long prate, calc_rate, diff, best_rate, best_prate;
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unsigned int num_parents = clk_hw_get_num_parents(hw);
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struct clk_hw *parent, *best_parent = NULL;
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unsigned int i, min_div, max_div, div;
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unsigned long min_diff = ULONG_MAX;
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return *parent_rate / div;
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for (i = 0; i < num_parents; i++) {
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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prate = clk_hw_get_rate(parent);
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if (!prate)
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continue;
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min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);
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max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;
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if (max_div < min_div)
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continue;
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div = cpg_div6_clock_calc_div(req->rate, prate);
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div = clamp(div, min_div, max_div);
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calc_rate = prate / div;
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diff = calc_rate > req->rate ? calc_rate - req->rate
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: req->rate - calc_rate;
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if (diff < min_diff) {
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best_rate = calc_rate;
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best_parent = parent;
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best_prate = prate;
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min_diff = diff;
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}
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}
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if (!best_parent)
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return -EINVAL;
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req->best_parent_rate = best_prate;
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req->best_parent_hw = best_parent;
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req->rate = best_rate;
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return 0;
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}
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static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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@ -133,11 +168,11 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
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unsigned int i;
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u8 hw_index;
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if (clock->src_width == 0)
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if (clock->src_mask == 0)
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return 0;
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hw_index = (readl(clock->reg) >> clock->src_shift) &
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(BIT(clock->src_width) - 1);
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hw_index = (readl(clock->reg) & clock->src_mask) >>
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__ffs(clock->src_mask);
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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if (clock->parents[i] == hw_index)
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return i;
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@ -151,18 +186,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
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static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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u8 hw_index;
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u32 mask;
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u32 src;
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if (index >= clk_hw_get_num_parents(hw))
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return -EINVAL;
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mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
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hw_index = clock->parents[index];
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writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
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clock->reg);
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src = clock->parents[index] << __ffs(clock->src_mask);
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writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);
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return 0;
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}
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@ -173,7 +203,7 @@ static const struct clk_ops cpg_div6_clock_ops = {
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.get_parent = cpg_div6_clock_get_parent,
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.set_parent = cpg_div6_clock_set_parent,
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.recalc_rate = cpg_div6_clock_recalc_rate,
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.round_rate = cpg_div6_clock_round_rate,
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.determine_rate = cpg_div6_clock_determine_rate,
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.set_rate = cpg_div6_clock_set_rate,
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};
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@ -236,17 +266,15 @@ struct clk * __init cpg_div6_register(const char *name,
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switch (num_parents) {
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case 1:
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/* fixed parent clock */
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clock->src_shift = clock->src_width = 0;
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clock->src_mask = 0;
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break;
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case 4:
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/* clock with EXSRC bits 6-7 */
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clock->src_shift = 6;
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clock->src_width = 2;
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clock->src_mask = GENMASK(7, 6);
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break;
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case 8:
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/* VCLK with EXSRC bits 12-14 */
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clock->src_shift = 12;
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clock->src_width = 3;
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clock->src_mask = GENMASK(14, 12);
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break;
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default:
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pr_err("%s: invalid number of parents for DIV6 clock %s\n",
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@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
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DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
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/* Core Clock Outputs */
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DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
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DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
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DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
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DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
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@ -180,6 +180,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
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DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
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DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
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DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
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DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
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DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
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DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
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DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
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DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
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DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
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DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),
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@ -604,20 +604,19 @@ r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
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return div;
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}
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static long
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r9a06g032_div_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *prate)
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static int
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r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
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u32 div = DIV_ROUND_UP(*prate, rate);
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u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
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pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
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hw->clk, rate, *prate, div);
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hw->clk, req->rate, req->best_parent_rate, div);
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pr_devel(" min %d (%ld) max %d (%ld)\n",
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clk->min, DIV_ROUND_UP(*prate, clk->min),
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clk->max, DIV_ROUND_UP(*prate, clk->max));
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clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
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clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
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div = r9a06g032_div_clamp_div(clk, rate, *prate);
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div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
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/*
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* this is a hack. Currently the serial driver asks for a clock rate
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* that is 16 times the baud rate -- and that is wildly outside the
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@ -630,11 +629,13 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
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if (clk->index == R9A06G032_DIV_UART ||
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clk->index == R9A06G032_DIV_P2_PG) {
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pr_devel("%s div uart hack!\n", __func__);
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return clk_get_rate(hw->clk);
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req->rate = clk_get_rate(hw->clk);
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return 0;
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}
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req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
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pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
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*prate, div, DIV_ROUND_UP(*prate, div));
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return DIV_ROUND_UP(*prate, div);
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req->best_parent_rate, div, req->rate);
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return 0;
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}
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static int
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@ -663,7 +664,7 @@ r9a06g032_div_set_rate(struct clk_hw *hw,
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static const struct clk_ops r9a06g032_clk_div_ops = {
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.recalc_rate = r9a06g032_div_recalc_rate,
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.round_rate = r9a06g032_div_round_rate,
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.determine_rate = r9a06g032_div_determine_rate,
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.set_rate = r9a06g032_div_set_rate,
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};
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@ -26,19 +26,135 @@
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#include "rcar-cpg-lib.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_PLL0CR 0x00d8
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#define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */
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#define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */
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#define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */
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#define CPG_PLL2CR 0x002c
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#define CPG_PLL4CR 0x01f4
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#define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
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#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
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/* PLL Clocks */
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struct cpg_pll_clk {
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struct clk_hw hw;
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void __iomem *pllcr_reg;
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void __iomem *pllecr_reg;
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unsigned int fixed_mult;
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u32 pllecr_pllst_mask;
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};
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#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
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static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
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unsigned int mult;
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u32 val;
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val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
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mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;
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return parent_rate * mult * pll_clk->fixed_mult;
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}
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static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
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unsigned int min_mult, max_mult, mult;
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unsigned long prate;
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prate = req->best_parent_rate * pll_clk->fixed_mult;
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min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
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max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
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if (max_mult < min_mult)
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return -EINVAL;
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mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
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mult = clamp(mult, min_mult, max_mult);
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req->rate = prate * mult;
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return 0;
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}
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static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
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unsigned int mult, i;
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u32 val;
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mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
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mult = clamp(mult, 1U, 128U);
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val = readl(pll_clk->pllcr_reg);
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val &= ~CPG_PLLnCR_STC_MASK;
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val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
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writel(val, pll_clk->pllcr_reg);
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for (i = 1000; i; i--) {
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if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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|
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static const struct clk_ops cpg_pll_clk_ops = {
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.recalc_rate = cpg_pll_clk_recalc_rate,
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.determine_rate = cpg_pll_clk_determine_rate,
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.set_rate = cpg_pll_clk_set_rate,
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};
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static struct clk * __init cpg_pll_clk_register(const char *name,
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const char *parent_name,
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void __iomem *base,
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unsigned int mult,
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unsigned int offset,
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unsigned int index)
|
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|
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{
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struct cpg_pll_clk *pll_clk;
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struct clk_init_data init = {};
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struct clk *clk;
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &cpg_pll_clk_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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|
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pll_clk->hw.init = &init;
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pll_clk->pllcr_reg = base + offset;
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pll_clk->pllecr_reg = base + CPG_PLLECR;
|
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pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
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pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
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|
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clk = clk_register(NULL, &pll_clk->hw);
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if (IS_ERR(clk))
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kfree(pll_clk);
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return clk;
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}
|
||||
|
||||
/*
|
||||
* Z Clock & Z2 Clock
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
|
||||
* rate - rate is adjustable.
|
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* clk->rate = (parent->rate * mult / 32 ) / fixed_div
|
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* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
#define CPG_FRQCRB 0x00000004
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@ -49,8 +165,9 @@ struct cpg_z_clk {
|
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struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
void __iomem *kick_reg;
|
||||
unsigned long mask;
|
||||
unsigned long max_rate; /* Maximum rate for normal mode */
|
||||
unsigned int fixed_div;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
|
||||
@ -74,7 +191,18 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
unsigned long prate;
|
||||
unsigned long rate, prate;
|
||||
|
||||
rate = min(req->rate, req->max_rate);
|
||||
if (rate <= zclk->max_rate) {
|
||||
/* Set parent rate to initial value for normal modes */
|
||||
prate = zclk->max_rate;
|
||||
} else {
|
||||
/* Set increased parent rate for boost modes */
|
||||
prate = rate;
|
||||
}
|
||||
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
|
||||
prate * zclk->fixed_div);
|
||||
|
||||
prate = req->best_parent_rate / zclk->fixed_div;
|
||||
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
|
||||
@ -82,10 +210,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
mult = div64_ul(req->rate * 32ULL, prate);
|
||||
mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
req->rate = div_u64((u64)prate * mult, 32);
|
||||
req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -103,8 +231,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
return -EBUSY;
|
||||
|
||||
cpg_reg_modify(zclk->reg, zclk->mask,
|
||||
((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
|
||||
cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
|
||||
|
||||
/*
|
||||
* Set KICK bit in FRQCRB to update hardware setting and wait for
|
||||
@ -117,7 +244,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
*
|
||||
* Using experimental measurements, it seems that no more than
|
||||
* ~10 iterations are needed, independently of the CPU rate.
|
||||
* Since this value might be dependent of external xtal rate, pll1
|
||||
* Since this value might be dependent on external xtal rate, pll1
|
||||
* rate or even the other emulation clocks rate, use 1000 as a
|
||||
* "super" safe value.
|
||||
*/
|
||||
@ -153,7 +280,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
|
||||
|
||||
init.name = name;
|
||||
init.ops = &cpg_z_clk_ops;
|
||||
init.flags = 0;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
@ -164,9 +291,13 @@ static struct clk * __init cpg_z_clk_register(const char *name,
|
||||
zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
|
||||
|
||||
clk = clk_register(NULL, &zclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(zclk);
|
||||
return clk;
|
||||
}
|
||||
|
||||
zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
|
||||
zclk->fixed_div;
|
||||
return clk;
|
||||
}
|
||||
|
||||
@ -314,16 +445,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
||||
|
||||
case CLK_TYPE_GEN3_PLL0:
|
||||
/*
|
||||
* PLL0 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
* PLL0 is implemented as a custom clock, to change the
|
||||
* multiplier when cpufreq changes between normal and boost
|
||||
* modes.
|
||||
*/
|
||||
value = readl(base + CPG_PLL0CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
if (cpg_quirks & PLL_ERRATA)
|
||||
mult *= 2;
|
||||
break;
|
||||
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
|
||||
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
|
||||
base, mult, CPG_PLL0CR, 0);
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
@ -332,16 +460,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
||||
|
||||
case CLK_TYPE_GEN3_PLL2:
|
||||
/*
|
||||
* PLL2 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
* PLL2 is implemented as a custom clock, to change the
|
||||
* multiplier when cpufreq changes between normal and boost
|
||||
* modes.
|
||||
*/
|
||||
value = readl(base + CPG_PLL2CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
if (cpg_quirks & PLL_ERRATA)
|
||||
mult *= 2;
|
||||
break;
|
||||
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
|
||||
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
|
||||
base, mult, CPG_PLL2CR, 2);
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
|
||||
@ -128,10 +128,8 @@ static int rcar_usb2_clock_sel_resume(struct device *dev)
|
||||
static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct usb2_clock_sel_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
of_clk_del_provider(dev->of_node);
|
||||
clk_hw_unregister(&priv->hw);
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
@ -164,9 +162,6 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(priv->rsts))
|
||||
return PTR_ERR(priv->rsts);
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
clk = devm_clk_get(dev, "usb_extal");
|
||||
if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
|
||||
priv->extal = !!clk_get_rate(clk);
|
||||
@ -183,6 +178,8 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
pm_runtime_get_sync(dev);
|
||||
platform_set_drvdata(pdev, priv);
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
@ -190,11 +187,20 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
||||
init.ops = &usb2_clock_sel_clock_ops;
|
||||
priv->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &priv->hw);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
ret = devm_clk_hw_register(NULL, &priv->hw);
|
||||
if (ret)
|
||||
goto pm_put;
|
||||
|
||||
return of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
|
||||
if (ret)
|
||||
goto pm_put;
|
||||
|
||||
return 0;
|
||||
|
||||
pm_put:
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = {
|
||||
|
||||
@ -100,13 +100,9 @@ static const u16 srcr_for_v3u[] = {
|
||||
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
|
||||
};
|
||||
|
||||
/* Realtime Module Stop Control Register offsets */
|
||||
#define RMSTPCR(i) (smstpcr[i] - 0x20)
|
||||
|
||||
/* Modem Module Stop Control Register offsets (r8a73a4) */
|
||||
#define MMSTPCR(i) (smstpcr[i] + 0x20)
|
||||
|
||||
/* Software Reset Clearing Register offsets */
|
||||
/*
|
||||
* Software Reset Clearing Register offsets
|
||||
*/
|
||||
|
||||
static const u16 srstclr[] = {
|
||||
0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user