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riscv: fix misalgned trap vector base address

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The trap vector marked by label .Lsecondary_park must align on a
4-byte boundary, as the {m,s}tvec is defined to require 4-byte
alignment.

Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Fixes: e011995e826f ("RISC-V: Move relocate and few other functions out of __init")
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Chen Lu 2021-10-18 13:22:38 +08:00 committed by Palmer Dabbelt
parent 3ef6ca4f35
commit 64a19591a2
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1 changed files with 1 additions and 0 deletions
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arch/riscv/kernel/head.S
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@ -193,6 +193,7 @@ setup_trap_vector:
csrw CSR_SCRATCH, zero
ret
.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi