From 1d0f9e1e1e46939ae52804917647982b43754996 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 13 Nov 2019 11:18:09 +0100 Subject: [PATCH 01/99] pinctrl: sh-pfc: Make legacy function GPIO handling less fragile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If there are no function GPIOs, sh_pfc_register_gpiochip() returns early with a success indicator. This is fragile, as new code may be added after the #ifdef block, which won't be executed in case of early return. Invert the logic, so the code always continues until the end of the function on success. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20191113101809.28600-1-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/gpio.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 5a55b8da7919..8213e118aa40 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -386,12 +386,11 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) } /* Register the function GPIOs chip. */ - if (pfc->info->nr_func_gpios == 0) - return 0; - - chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); - if (IS_ERR(chip)) - return PTR_ERR(chip); + if (pfc->info->nr_func_gpios) { + chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); + if (IS_ERR(chip)) + return PTR_ERR(chip); + } #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */ return 0; From 539d8bde72c22d760013bf81436d6bb94eb67aed Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 24 Oct 2019 17:33:42 +0300 Subject: [PATCH 02/99] pinctrl: baytrail: Allocate IRQ chip dynamic Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. Fixes: 9f573b98ca50 ("pinctrl: baytrail: Update irq chip operations") Depends-on: ca8a958e2acb ("pinctrl: baytrail: Pass irqchip when adding gpiochip") Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-baytrail.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 55141d5de29e..72ffd19448e5 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -107,6 +107,7 @@ struct byt_gpio_pin_context { struct byt_gpio { struct gpio_chip chip; + struct irq_chip irqchip; struct platform_device *pdev; struct pinctrl_dev *pctl_dev; struct pinctrl_desc pctl_desc; @@ -1395,15 +1396,6 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip byt_irqchip = { - .name = "BYT-GPIO", - .irq_ack = byt_irq_ack, - .irq_mask = byt_irq_mask, - .irq_unmask = byt_irq_unmask, - .irq_set_type = byt_irq_type, - .flags = IRQCHIP_SKIP_SET_WAKE, -}; - static void byt_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); @@ -1551,8 +1543,15 @@ static int byt_gpio_probe(struct byt_gpio *vg) if (irq_rc && irq_rc->start) { struct gpio_irq_chip *girq; + vg->irqchip.name = "BYT-GPIO", + vg->irqchip.irq_ack = byt_irq_ack, + vg->irqchip.irq_mask = byt_irq_mask, + vg->irqchip.irq_unmask = byt_irq_unmask, + vg->irqchip.irq_set_type = byt_irq_type, + vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE, + girq = &gc->irq; - girq->chip = &byt_irqchip; + girq->chip = &vg->irqchip; girq->init_hw = byt_gpio_irq_init_hw; girq->parent_handler = byt_gpio_irq_handler; girq->num_parents = 1; From ab68b220e81fd03383c0d9e1a87b51f9bbe4db77 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 24 Oct 2019 17:33:43 +0300 Subject: [PATCH 03/99] pinctrl: baytrail: Group GPIO IRQ chip initialization After commit 5ea422750a9f ("pinctrl: baytrail: Pass irqchip when adding gpiochip") the GPIO IRQ chip structure is being initialized under conditional when IRQ resource has been discovered. But that commit left aside the assignment of ->init_valid_mask() callback that is done unconditionally. For sake of consistency and preventing some garbage in GPIO IRQ chip structure group initialization together. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-baytrail.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 72ffd19448e5..d829843314ba 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1529,7 +1529,6 @@ static int byt_gpio_probe(struct byt_gpio *vg) gc->add_pin_ranges = byt_gpio_add_pin_ranges; gc->parent = &vg->pdev->dev; gc->ngpio = vg->soc_data->npins; - gc->irq.init_valid_mask = byt_init_irq_valid_mask; #ifdef CONFIG_PM_SLEEP vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, @@ -1553,6 +1552,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) girq = &gc->irq; girq->chip = &vg->irqchip; girq->init_hw = byt_gpio_irq_init_hw; + girq->init_valid_mask = byt_init_irq_valid_mask; girq->parent_handler = byt_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(&vg->pdev->dev, girq->num_parents, From 73ae2cb424950f917829a8b78359ae1e4b175f3c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Dec 2019 17:39:36 +0100 Subject: [PATCH 04/99] pinctrl: samsung: Enable compile test for build coverage The Samsung pinctrl drivers require only GPIOLIB and OF for building. The drivers should be buildable on all architectures so enable COMPILE_TEST. Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/Kconfig | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index 425fadd6c346..cbf1ce48fddb 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -9,7 +9,8 @@ config PINCTRL_SAMSUNG config PINCTRL_EXYNOS bool "Pinctrl driver data for Samsung EXYNOS SoCs" - depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210) + depends on OF && GPIOLIB + depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST select PINCTRL_SAMSUNG select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210) select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS @@ -24,10 +25,11 @@ config PINCTRL_EXYNOS_ARM64 config PINCTRL_S3C24XX bool "Samsung S3C24XX SoC pinctrl driver" - depends on ARCH_S3C24XX && OF + depends on OF + depends on ARCH_S3C24XX || COMPILE_TEST select PINCTRL_SAMSUNG config PINCTRL_S3C64XX bool "Samsung S3C64XX SoC pinctrl driver" - depends on ARCH_S3C64XX + depends on ARCH_S3C64XX || COMPILE_TEST select PINCTRL_SAMSUNG From 56d9625e8cc6d2fb6f59a3829d1c258944535609 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Dec 2019 17:39:37 +0100 Subject: [PATCH 05/99] pinctrl: samsung: Clarify the option titles/names The config options toggle Samsung Exynos SoCs pinctrl drivers, not the driver data. Clarify this in the option title/name and also make it consistent with other Samsung entries. No functional change. Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index cbf1ce48fddb..779c0e9eca3f 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -8,7 +8,7 @@ config PINCTRL_SAMSUNG select PINCONF config PINCTRL_EXYNOS - bool "Pinctrl driver data for Samsung EXYNOS SoCs" + bool "Pinctrl common driver part for Samsung Exynos SoCs" depends on OF && GPIOLIB depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST select PINCTRL_SAMSUNG @@ -16,11 +16,11 @@ config PINCTRL_EXYNOS select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS config PINCTRL_EXYNOS_ARM - bool "ARMv7-specific pinctrl driver data for Exynos" if COMPILE_TEST + bool "ARMv7-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST depends on PINCTRL_EXYNOS config PINCTRL_EXYNOS_ARM64 - bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST + bool "ARMv8-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST depends on PINCTRL_EXYNOS config PINCTRL_S3C24XX From c81d37bc9f055d28af020107e11b21867ddbd8e8 Mon Sep 17 00:00:00 2001 From: Nishad Kamdar Date: Wed, 27 Nov 2019 22:12:33 +0530 Subject: [PATCH 06/99] pinctrl: mediatek: Use the correct style for SPDX License Identifier This patch corrects the SPDX License Identifier style in header file related mediatek mt2712 pinctrl driver. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches Signed-off-by: Nishad Kamdar Link: https://lore.kernel.org/r/2994fb2f3375790e832396cdbb0a279dc8c8839f.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h index ba2356a8ab89..845c408b5fdb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018 MediaTek Inc. * Author: Zhiyong Tao From 86951164f3b3670529cf839e33ca62fe19b410f6 Mon Sep 17 00:00:00 2001 From: Nishad Kamdar Date: Wed, 27 Nov 2019 22:14:22 +0530 Subject: [PATCH 07/99] pinctrl: meson-axg: Use the correct style for SPDX License Identifier This patch corrects the SPDX License Identifier style in header file related Meson axg SoC pinctrl driver. It assigns explicit block comment for the SPDX License Identifier. Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches Signed-off-by: Nishad Kamdar Link: https://lore.kernel.org/r/bcb86aa22d8d8499502bbd8c54a364be24886a86.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h index 8ff88bf2e849..aa79d7ecee00 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ /* * Copyright (c) 2017 Baylibre SAS. * Author: Jerome Brunet @@ -5,7 +6,6 @@ * Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) */ struct meson_pmx_bank { From a7caba8ac04c042afab91f77b7a4f74b79c9bbef Mon Sep 17 00:00:00 2001 From: Nishad Kamdar Date: Wed, 27 Nov 2019 22:17:46 +0530 Subject: [PATCH 08/99] pinctrl: stm32: Use the correct style for SPDX License Identifier This patch corrects the SPDX License Identifier style in header file related to STMicroelectronics pinctrl driver. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches Signed-off-by: Nishad Kamdar Link: https://lore.kernel.org/r/14bb695da50f7af8499e7dfc32c2ab753d92a3e9.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index ec0d34c33903..b0882d120765 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) Maxime Coquelin 2015 * Copyright (C) STMicroelectronics 2017 From 6f0ebdf45c0bb74cf004f6e195f31882bfbf058b Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 2 Dec 2019 16:44:26 +1030 Subject: [PATCH 09/99] dt-bindings: pinctrl: aspeed-g6: Add USB functions and groups The AST2600 provides two USB ports (A and B) that expose various host, device and HID functions. Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-2-andrew@aj.id.au Signed-off-by: Linus Walleij --- .../bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 064b7dfc4252..3749fa233e87 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -54,8 +54,9 @@ patternProperties: TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, - UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, - WDTRST3, WDTRST4, ] + UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP, + USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, + WDTRST4, ] groups: allOf: - $ref: "/schemas/types.yaml#/definitions/string" @@ -85,8 +86,8 @@ patternProperties: TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0, - UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB, - VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ] + UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA, + USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ] required: - compatible From 8b99fb9feb0149fd1dc80552b50993137d75611a Mon Sep 17 00:00:00 2001 From: Johnny Huang Date: Mon, 2 Dec 2019 16:44:27 +1030 Subject: [PATCH 10/99] pinctrl: aspeed-g6: Add AST2600 I3C1 and I3C2 pinmux config These pins only expose a single function but are not fixed-function as their I3C capability can be disabled. Signed-off-by: Johnny Huang [AJ: Tweak commit message, sort pins list] Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-3-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index c6800d220920..49fc4824ccee 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -37,7 +37,7 @@ #define SCU510 0x510 /* Hardware Strap 2 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ -#define ASPEED_G6_NR_PINS 248 +#define ASPEED_G6_NR_PINS 252 #define M24 0 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); @@ -1542,6 +1542,26 @@ GROUP_DECL(I3C4, AE25, AF24); FUNC_DECL_2(I3C4, HVI3C4, I3C4); FUNC_GROUP_DECL(FSI2, AE25, AF24); +#define AF23 248 +SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16)); +PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL)); + +#define AE24 249 +SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17)); +PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA)); + +FUNC_GROUP_DECL(I3C1, AF23, AE24); + +#define AF22 250 +SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18)); +PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL)); + +#define AE22 251 +SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19)); +PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA)); + +FUNC_GROUP_DECL(I3C2, AF22, AE22); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { @@ -1633,6 +1653,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AE16), ASPEED_PINCTRL_PIN(AE18), ASPEED_PINCTRL_PIN(AE19), + ASPEED_PINCTRL_PIN(AE22), + ASPEED_PINCTRL_PIN(AE24), ASPEED_PINCTRL_PIN(AE25), ASPEED_PINCTRL_PIN(AE26), ASPEED_PINCTRL_PIN(AE7), @@ -1642,6 +1664,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AF12), ASPEED_PINCTRL_PIN(AF14), ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF22), + ASPEED_PINCTRL_PIN(AF23), ASPEED_PINCTRL_PIN(AF24), ASPEED_PINCTRL_PIN(AF25), ASPEED_PINCTRL_PIN(AF7), @@ -1855,6 +1879,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(I2C7), ASPEED_PINCTRL_GROUP(I2C8), ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(I3C1), + ASPEED_PINCTRL_GROUP(I3C2), ASPEED_PINCTRL_GROUP(I3C3), ASPEED_PINCTRL_GROUP(I3C4), ASPEED_PINCTRL_GROUP(I3C5), @@ -2087,6 +2113,8 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(I2C7), ASPEED_PINCTRL_FUNC(I2C8), ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(I3C1), + ASPEED_PINCTRL_FUNC(I3C2), ASPEED_PINCTRL_FUNC(I3C3), ASPEED_PINCTRL_FUNC(I3C4), ASPEED_PINCTRL_FUNC(I3C5), From 22d6919039838226d2041cc22e279985b4230f64 Mon Sep 17 00:00:00 2001 From: Johnny Huang Date: Mon, 2 Dec 2019 16:44:28 +1030 Subject: [PATCH 11/99] pinctrl: aspeed-g6: Add support for the AST2600 USB pinmux AST2600 has two USB ports, A, B: Port A supports 4 distinct modes: 1. PCIe EHCI to Hub 2. Hub to PHY 3. BMC EHCI to PHY 4. PCIe EHCI to PHY Port B support 3 modes: 1. USB1.1 HID controller 2. USB2.0 Device controller 3. BMC EHCI port2 Implement pinmux support by mapping each ports' functions onto a single pin group for each port. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-4-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 69 +++++++++++++++++++++- drivers/pinctrl/aspeed/pinmux-aspeed.h | 1 + 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 49fc4824ccee..22e6c07149c3 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -26,6 +26,7 @@ #define SCU430 0x430 /* Multi-function Pin Control #8 */ #define SCU434 0x434 /* Multi-function Pin Control #9 */ #define SCU438 0x438 /* Multi-function Pin Control #10 */ +#define SCU440 0x440 /* USB Multi-function Pin Control #12 */ #define SCU450 0x450 /* Multi-function Pin Control #14 */ #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ @@ -36,8 +37,9 @@ #define SCU500 0x500 /* Hardware Strap 1 */ #define SCU510 0x510 /* Hardware Strap 2 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ +#define SCUC20 0xC20 /* PCIE configuration Setting Control */ -#define ASPEED_G6_NR_PINS 252 +#define ASPEED_G6_NR_PINS 256 #define M24 0 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); @@ -1562,6 +1564,58 @@ PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA)); FUNC_GROUP_DECL(I3C2, AF22, AE22); +#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 } +#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 } +#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 } +#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 } +#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 } +#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 } +#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 } + +#define A4 252 +SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC, + SIG_DESC_SET(SCUC20, 16)); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC); +PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP), + SIG_EXPR_LIST_PTR(A4, USB2AHDP)); + +#define B4 253 +SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC); +PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN), + SIG_EXPR_LIST_PTR(B4, USB2AHDN)); + +GROUP_DECL(USBA, A4, B4); + +FUNC_DECL_1(USB2ADP, USBA); +FUNC_DECL_1(USB2AD, USBA); +FUNC_DECL_1(USB2AH, USBA); +FUNC_DECL_1(USB2AHP, USBA); + +#define A6 254 +SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC); +SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC); +PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP), + SIG_EXPR_LIST_PTR(A6, USB2BHDP)); + +#define B6 255 +SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC); +SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC); +PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN), + SIG_EXPR_LIST_PTR(B6, USB2BHDN)); + +GROUP_DECL(USBB, A6, B6); + +FUNC_DECL_1(USB11BHID, USBB); +FUNC_DECL_1(USB2BD, USBB); +FUNC_DECL_1(USB2BH, USBB); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { @@ -1582,6 +1636,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(A24), ASPEED_PINCTRL_PIN(A25), ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(A4), + ASPEED_PINCTRL_PIN(A6), ASPEED_PINCTRL_PIN(AA11), ASPEED_PINCTRL_PIN(AA12), ASPEED_PINCTRL_PIN(AA16), @@ -1686,6 +1742,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(B25), ASPEED_PINCTRL_PIN(B26), ASPEED_PINCTRL_PIN(B3), + ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B6), ASPEED_PINCTRL_PIN(C1), ASPEED_PINCTRL_PIN(C11), ASPEED_PINCTRL_PIN(C12), @@ -2046,6 +2104,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(UART7), ASPEED_PINCTRL_GROUP(UART8), ASPEED_PINCTRL_GROUP(UART9), + ASPEED_PINCTRL_GROUP(USBA), + ASPEED_PINCTRL_GROUP(USBB), ASPEED_PINCTRL_GROUP(VB), ASPEED_PINCTRL_GROUP(VGAHS), ASPEED_PINCTRL_GROUP(VGAVS), @@ -2257,6 +2317,13 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(UART7), ASPEED_PINCTRL_FUNC(UART8), ASPEED_PINCTRL_FUNC(UART9), + ASPEED_PINCTRL_FUNC(USB11BHID), + ASPEED_PINCTRL_FUNC(USB2AD), + ASPEED_PINCTRL_FUNC(USB2ADP), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2AHP), + ASPEED_PINCTRL_FUNC(USB2BD), + ASPEED_PINCTRL_FUNC(USB2BH), ASPEED_PINCTRL_FUNC(VB), ASPEED_PINCTRL_FUNC(VGAHS), ASPEED_PINCTRL_FUNC(VGAVS), diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index 140c5ce9fbc1..f86739e800c3 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -737,6 +737,7 @@ struct aspeed_pin_desc { #define FUNC_DECL_(func, ...) \ static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } +#define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group) #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) #define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three) From a79bcd51ae06b134c97d1fa707b7c7385d2d61af Mon Sep 17 00:00:00 2001 From: Johnny Huang Date: Mon, 2 Dec 2019 16:44:29 +1030 Subject: [PATCH 12/99] pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 160 ++++++++-------- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 202 ++++++++++----------- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 7 + 3 files changed, 188 insertions(+), 181 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 95ea593fa29d..c56ded0ac57e 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2439,88 +2439,88 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { static const struct aspeed_pin_config aspeed_g4_configs[] = { /* GPIO banks ranges [A, B], [D, J], [M, R] */ - { PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 }, - { PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31), /* GPIOs T[0-5] (RGMII1 Tx pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12), /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14), /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13), /* GPIOs V[2-7] (RGMII2 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15), /* ADC pull-downs (SCUA8[19:4]) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19), /* * Debounce settings for GPIOs D and E passthrough mode are in @@ -2531,14 +2531,14 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = { * controller. Due to this tangle between GPIO and pinctrl we don't yet * fully support pass-through debounce. */ - { PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 }, + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27), }; static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index d8a804b9f958..b2fe47b98fa0 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2476,124 +2476,124 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { static struct aspeed_pin_config aspeed_g5_configs[] = { /* GPIOA, GPIOQ */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16), /* GPIOB, GPIOR */ - { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17), /* GPIOC, GPIOS*/ - { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18), /* GPIOD, GPIOY */ - { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19), /* GPIOE, GPIOZ */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20), /* GPIOF, GPIOAA */ - { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21), - /* GPIOG, GPIOAB */ - { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 }, + /* GPIOG, GPIOAB */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22), /* GPIOH, GPIOAC */ - { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23), /* GPIOs [I, P] */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 }, - { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31), /* GPIOs T[0-5] (RGMII1 Tx pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 }, - { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12), /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 }, - { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14), /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13), /* GPIOs V[2-7] (RGMII2 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15), /* ADC pull-downs (SCUA8[19:4]) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19), /* * Debounce settings for GPIOs D and E passthrough mode are in @@ -2604,14 +2604,14 @@ static struct aspeed_pin_config aspeed_g5_configs[] = { * controller. Due to this tangle between GPIO and pinctrl we don't yet * fully support pass-through debounce. */ - { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 }, + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27), }; static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index a5d83986f32e..a7db31202033 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -35,6 +35,13 @@ struct aspeed_pin_config { .drv_data = (void *) &(PIN_SYM(name_)) \ } +#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \ + .param = param_, \ + .pins = {pin0_, pin1_}, \ + .reg = reg_, \ + .bit = bit_ \ +} + struct aspeed_pinctrl_data { struct regmap *scu; From 5b854f2842458d2bbb2a49c20d958c9f6f610465 Mon Sep 17 00:00:00 2001 From: Johnny Huang Date: Mon, 2 Dec 2019 16:44:30 +1030 Subject: [PATCH 13/99] pinctrl: aspeed: Move aspeed_pin_config_map to separate source file The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 10 ++++++ drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 10 ++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.c | 38 +++------------------- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 19 +++++++++++ 4 files changed, 44 insertions(+), 33 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index c56ded0ac57e..62b8aa53b627 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2594,6 +2594,14 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, +}; + static const struct aspeed_pinmux_ops aspeed_g4_ops = { .set = aspeed_g4_sig_expr_set, }; @@ -2610,6 +2618,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { }, .configs = aspeed_g4_configs, .nconfigs = ARRAY_SIZE(aspeed_g4_configs), + .confmaps = aspeed_g4_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map), }; static const struct pinmux_ops aspeed_g4_pinmux_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index b2fe47b98fa0..2acbcf3d508a 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2780,6 +2780,14 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, +}; + static const struct aspeed_pinmux_ops aspeed_g5_ops = { .eval = aspeed_g5_sig_expr_eval, .set = aspeed_g5_sig_expr_set, @@ -2797,6 +2805,8 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { }, .configs = aspeed_g5_configs, .nconfigs = ARRAY_SIZE(aspeed_g5_configs), + .confmaps = aspeed_g5_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map), }; static const struct pinmux_ops aspeed_g5_pinmux_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 54933665b5f8..fc68aca7b36c 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -411,49 +411,21 @@ static inline const struct aspeed_pin_config *find_pinconf_config( return NULL; } -/* - * Aspeed pin configuration description. - * - * @param: pinconf configuration parameter - * @arg: The supported argument for @param, or -1 if any value is supported - * @val: The register value to write to configure @arg for @param - * - * The map is to be used in conjunction with the configuration array supplied - * by the driver implementation. - */ -struct aspeed_pin_config_map { - enum pin_config_param param; - s32 arg; - u32 val; -}; - enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL }; -/* Aspeed consistently both: - * - * 1. Defines "disable bits" for internal pull-downs - * 2. Uses 8mA or 16mA drive strengths - */ -static const struct aspeed_pin_config_map pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 }, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 }, - { PIN_CONFIG_BIAS_DISABLE, -1, 1 }, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0 }, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1 }, -}; - static const struct aspeed_pin_config_map *find_pinconf_map( + const struct aspeed_pinctrl_data *pdata, enum pin_config_param param, enum aspeed_pin_config_map_type type, s64 value) { int i; - for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) { + for (i = 0; i < pdata->nconfmaps; i++) { const struct aspeed_pin_config_map *elem; bool match; - elem = &pin_config_map[i]; + elem = &pdata->confmaps[i]; switch (type) { case MAP_TYPE_ARG: @@ -491,7 +463,7 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, if (rc < 0) return rc; - pmap = find_pinconf_map(param, MAP_TYPE_VAL, + pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL, (val & BIT(pconf->bit)) >> pconf->bit); if (!pmap) @@ -535,7 +507,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, if (!pconf) return -ENOTSUPP; - pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg); + pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg); if (WARN_ON(!pmap)) return -EINVAL; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index a7db31202033..27d3929b6aca 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -42,6 +42,22 @@ struct aspeed_pin_config { .bit = bit_ \ } +/* + * Aspeed pin configuration description. + * + * @param: pinconf configuration parameter + * @arg: The supported argument for @param, or -1 if any value is supported + * @val: The register value to write to configure @arg for @param + * + * The map is to be used in conjunction with the configuration array supplied + * by the driver implementation. + */ +struct aspeed_pin_config_map { + enum pin_config_param param; + s32 arg; + u32 val; +}; + struct aspeed_pinctrl_data { struct regmap *scu; @@ -52,6 +68,9 @@ struct aspeed_pinctrl_data { const unsigned int nconfigs; struct aspeed_pinmux_data pinmux; + + const struct aspeed_pin_config_map *confmaps; + const unsigned int nconfmaps; }; /* Aspeed pinctrl helpers */ From 5f52c853847ffdc9654e5b685e1a1ae5bee83e65 Mon Sep 17 00:00:00 2001 From: Johnny Huang Date: Mon, 2 Dec 2019 16:44:31 +1030 Subject: [PATCH 14/99] pinctrl: aspeed: Use masks to describe pinconf bitfields Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. Signed-off-by: Johnny Huang [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-7-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 10 +++++----- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 10 +++++----- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 ++++++------ drivers/pinctrl/aspeed/pinctrl-aspeed.h | 7 ++++--- 4 files changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 62b8aa53b627..bfed0e274643 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2595,11 +2595,11 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, } static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, - { PIN_CONFIG_BIAS_DISABLE, -1, 1}, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, }; static const struct aspeed_pinmux_ops aspeed_g4_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 2acbcf3d508a..0cab4c2576e2 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2781,11 +2781,11 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, } static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, - { PIN_CONFIG_BIAS_DISABLE, -1, 1}, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, }; static const struct aspeed_pinmux_ops aspeed_g5_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index fc68aca7b36c..b625a657171e 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -464,7 +464,7 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, return rc; pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL, - (val & BIT(pconf->bit)) >> pconf->bit); + (val & pconf->mask) >> __ffs(pconf->mask)); if (!pmap) return -EINVAL; @@ -512,17 +512,17 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, if (WARN_ON(!pmap)) return -EINVAL; - val = pmap->val << pconf->bit; + val = pmap->val << __ffs(pconf->mask); rc = regmap_update_bits(pdata->scu, pconf->reg, - BIT(pconf->bit), val); + pmap->mask, val); if (rc < 0) return rc; - pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n", - __func__, pconf->reg, pconf->bit, pmap->val, - param, arg, offset); + pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n", + __func__, pconf->reg, __ffs(pconf->mask), + pmap->val, param, arg, offset); } return 0; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 27d3929b6aca..6f0f03395617 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -24,8 +24,7 @@ struct aspeed_pin_config { enum pin_config_param param; unsigned int pins[2]; unsigned int reg; - u8 bit; - u8 value; + u32 mask; }; #define ASPEED_PINCTRL_PIN(name_) \ @@ -39,7 +38,7 @@ struct aspeed_pin_config { .param = param_, \ .pins = {pin0_, pin1_}, \ .reg = reg_, \ - .bit = bit_ \ + .mask = BIT_MASK(bit_) \ } /* @@ -48,6 +47,7 @@ struct aspeed_pin_config { * @param: pinconf configuration parameter * @arg: The supported argument for @param, or -1 if any value is supported * @val: The register value to write to configure @arg for @param + * @mask: The bitfield mask for @val * * The map is to be used in conjunction with the configuration array supplied * by the driver implementation. @@ -56,6 +56,7 @@ struct aspeed_pin_config_map { enum pin_config_param param; s32 arg; u32 val; + u32 mask; }; struct aspeed_pinctrl_data { From 15711ba6ff197c3152c655dd9c55f5c1694e8272 Mon Sep 17 00:00:00 2001 From: Johnny Huang Date: Mon, 2 Dec 2019 16:44:32 +1030 Subject: [PATCH 15/99] pinctrl: aspeed-g6: Add AST2600 pinconf support The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-8-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 290 +++++++++++++++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.h | 7 + 2 files changed, 297 insertions(+) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 22e6c07149c3..eb0c11a9fbf2 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -28,6 +28,8 @@ #define SCU438 0x438 /* Multi-function Pin Control #10 */ #define SCU440 0x440 /* USB Multi-function Pin Control #12 */ #define SCU450 0x450 /* Multi-function Pin Control #14 */ +#define SCU454 0x454 /* Multi-function Pin Control #15 */ +#define SCU458 0x458 /* Multi-function Pin Control #16 */ #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ #define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */ @@ -36,6 +38,13 @@ #define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */ #define SCU500 0x500 /* Hardware Strap 1 */ #define SCU510 0x510 /* Hardware Strap 2 */ +#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */ +#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */ +#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */ +#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */ +#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ +#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ +#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ #define SCUC20 0xC20 /* PCIE configuration Setting Control */ @@ -2333,6 +2342,260 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(WDTRST4), }; +static struct aspeed_pin_config aspeed_g6_configs[] = { + /* GPIOB7 */ + ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15), + /* GPIOB6 */ + ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14), + /* GPIOB5 */ + ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13), + /* GPIOB4 */ + ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12), + /* GPIOB3 */ + ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11), + /* GPIOB2 */ + ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10), + /* GPIOB1 */ + ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9), + /* GPIOB0 */ + ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8), + + /* GPIOH3 */ + ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27), + /* GPIOH2 */ + ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26), + /* GPIOH1 */ + ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25), + /* GPIOH0 */ + ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24), + + /* GPIOL7 */ + ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31), + /* GPIOL6 */ + ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30), + /* GPIOL5 */ + ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29), + /* GPIOL4 */ + ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28), + + /* GPIOJ7 */ + ASPEED_PULL_UP_PINCONF(D19, SCU618, 15), + /* GPIOJ6 */ + ASPEED_PULL_UP_PINCONF(C20, SCU618, 14), + /* GPIOJ5 */ + ASPEED_PULL_UP_PINCONF(A19, SCU618, 13), + /* GPIOJ4 */ + ASPEED_PULL_UP_PINCONF(C19, SCU618, 12), + /* GPIOJ3 */ + ASPEED_PULL_UP_PINCONF(D20, SCU618, 11), + /* GPIOJ2 */ + ASPEED_PULL_UP_PINCONF(E19, SCU618, 10), + /* GPIOJ1 */ + ASPEED_PULL_UP_PINCONF(A20, SCU618, 9), + /* GPIOJ0 */ + ASPEED_PULL_UP_PINCONF(B20, SCU618, 8), + + /* GPIOI7 */ + ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7), + /* GPIOI6 */ + ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6), + /* GPIOI5 */ + ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5), + /* GPIOI4 */ + ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4), + /* GPIOI3 */ + ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3), + /* GPIOI2 */ + ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2), + /* GPIOI1 */ + ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1), + /* GPIOI0 */ + ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0), + + /* GPIOP7 */ + ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31), + /* GPIOP6 */ + ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30), + /* GPIOP5 */ + ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29), + /* GPIOP4 */ + ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28), + /* GPIOP3 */ + ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27), + /* GPIOP2 */ + ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26), + /* GPIOP1 */ + ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25), + /* GPIOP0 */ + ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24), + + /* GPIOO7 */ + ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23), + /* GPIOO6 */ + ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22), + /* GPIOO5 */ + ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21), + /* GPIOO4 */ + ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20), + /* GPIOO3 */ + ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19), + /* GPIOO2 */ + ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18), + /* GPIOO1 */ + ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17), + /* GPIOO0 */ + ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16), + + /* GPION7 */ + ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15), + /* GPION6 */ + ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14), + /* GPION5 */ + ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13), + /* GPION4 */ + ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12), + /* GPION3 */ + ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11), + /* GPION2 */ + ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10), + /* GPION1 */ + ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9), + /* GPION0 */ + ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8), + + /* GPIOM7 */ + ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7), + /* GPIOM6 */ + ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6), + /* GPIOM5 */ + ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5), + /* GPIOM4 */ + ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4), + /* GPIOM3 */ + ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3), + /* GPIOM2 */ + ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2), + /* GPIOM1 */ + ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1), + /* GPIOM0 */ + ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0), + + /* GPIOS7 */ + ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23), + /* GPIOS6 */ + ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22), + /* GPIOS5 */ + ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21), + /* GPIOS4 */ + ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20), + /* GPIOS3*/ + ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19), + /* GPIOS2 */ + ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18), + /* GPIOS1 */ + ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17), + /* GPIOS0 */ + ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16), + + /* GPIOR7 */ + ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15), + /* GPIOR6 */ + ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14), + /* GPIOR5 */ + ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13), + /* GPIOR4 */ + ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12), + /* GPIOR3*/ + ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11), + /* GPIOR2 */ + ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10), + /* GPIOR1 */ + ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9), + /* GPIOR0 */ + ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8), + + /* GPIOX7 */ + ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31), + /* GPIOX6 */ + ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30), + /* GPIOX5 */ + ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29), + /* GPIOX4 */ + ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28), + /* GPIOX3*/ + ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27), + /* GPIOX2 */ + ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26), + /* GPIOX1 */ + ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25), + /* GPIOX0 */ + ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24), + + /* GPIOV7 */ + ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15), + /* GPIOV6 */ + ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14), + /* GPIOV5 */ + ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13), + /* GPIOV4 */ + ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12), + /* GPIOV3*/ + ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11), + /* GPIOV2 */ + ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10), + /* GPIOV1 */ + ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9), + /* GPIOV0 */ + ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8), + + /* GPIOZ7 */ + ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15), + /* GPIOZ6 */ + ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14), + /* GPIOZ5 */ + ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13), + /* GPIOZ4 */ + ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12), + /* GPIOZ3*/ + ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11), + + /* GPIOZ1 */ + ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9), + /* GPIOZ0 */ + ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8), + + /* GPIOY6 */ + ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6), + /* GPIOY5 */ + ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5), + /* GPIOY4 */ + ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4), + /* GPIOY3 */ + ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3), + /* GPIOY2 */ + ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2), + /* GPIOY1 */ + ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1), + /* GPIOY0 */ + ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0), + + /* LAD3 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)}, + /* LAD2 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)}, + /* LAD1 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)}, + /* LAD0 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)}, + + /* MAC3 */ + { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)}, + { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)}, + /* MAC4 */ + { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)}, + { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)}, +}; + /** * Configure a pin's signal by applying an expression's descriptor state for * all descriptors in the expression. @@ -2400,6 +2663,20 @@ static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)}, + { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)}, + { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)}, +}; + static const struct aspeed_pinmux_ops aspeed_g5_ops = { .set = aspeed_g6_sig_expr_set, }; @@ -2414,6 +2691,10 @@ static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = { .functions = aspeed_g6_functions, .nfunctions = ARRAY_SIZE(aspeed_g6_functions), }, + .configs = aspeed_g6_configs, + .nconfigs = ARRAY_SIZE(aspeed_g6_configs), + .confmaps = aspeed_g6_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map), }; static const struct pinmux_ops aspeed_g6_pinmux_ops = { @@ -2434,12 +2715,21 @@ static const struct pinctrl_ops aspeed_g6_pinctrl_ops = { .dt_free_map = pinctrl_utils_free_map, }; +static const struct pinconf_ops aspeed_g6_conf_ops = { + .is_generic = true, + .pin_config_get = aspeed_pin_config_get, + .pin_config_set = aspeed_pin_config_set, + .pin_config_group_get = aspeed_pin_config_group_get, + .pin_config_group_set = aspeed_pin_config_group_set, +}; + static struct pinctrl_desc aspeed_g6_pinctrl_desc = { .name = "aspeed-g6-pinctrl", .pins = aspeed_g6_pins, .npins = ARRAY_SIZE(aspeed_g6_pins), .pctlops = &aspeed_g6_pinctrl_ops, .pmxops = &aspeed_g6_pinmux_ops, + .confops = &aspeed_g6_conf_ops, }; static int aspeed_g6_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 6f0f03395617..4dcde3bc29c8 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -41,6 +41,13 @@ struct aspeed_pin_config { .mask = BIT_MASK(bit_) \ } +#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) + +#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) /* * Aspeed pin configuration description. * From 0cf24c8f29bb06551c38210b96f5ea99d908749a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 11 Dec 2019 11:03:08 +0100 Subject: [PATCH 16/99] pinctrl: sh-pfc: Remove use of ARCH_R8A7796 CONFIG_ARCH_R8A7796 was renamed to CONFIG_ARCH_R8A77960 in commit 39e57e14d7eaf818 ("soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W"), so its users can be removed. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191211100308.6958-1-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 28d66e7cb098..ecf3b045bf75 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -27,7 +27,7 @@ config PINCTRL_SH_PFC select PINCTRL_PFC_R8A7793 if ARCH_R8A7793 select PINCTRL_PFC_R8A7794 if ARCH_R8A7794 select PINCTRL_PFC_R8A7795 if ARCH_R8A7795 - select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796 + select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 select PINCTRL_PFC_R8A77961 if ARCH_R8A77961 select PINCTRL_PFC_R8A77965 if ARCH_R8A77965 select PINCTRL_PFC_R8A77970 if ARCH_R8A77970 From e70982b3abec4fb6e2ce9489f071080ca84e4bc7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 5 Nov 2019 16:23:24 +0200 Subject: [PATCH 17/99] pinctrl: baytrail: Move IRQ valid mask initialization to a dedicated callback There is a logical continuation of the commit 5fbe5b5883f8 ("gpio: Initialize the irqchip valid_mask with a callback") to split IRQ initialization to hardware and valid mask setup parts. Acked-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index d829843314ba..ea61a19857c1 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1432,23 +1432,11 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) static void byt_init_irq_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) -{ - /* - * FIXME: currently the valid_mask is filled in as part of - * initializing the irq_chip below in byt_gpio_irq_init_hw(). - * when converting this driver to the new way of passing the - * gpio_irq_chip along when adding the gpio_chip, move the - * mask initialization into this callback instead. Right now - * this callback is here to make sure the mask gets allocated. - */ -} - -static int byt_gpio_irq_init_hw(struct gpio_chip *chip) { struct byt_gpio *vg = gpiochip_get_data(chip); struct device *dev = &vg->pdev->dev; void __iomem *reg; - u32 base, value; + u32 value; int i; /* @@ -1469,13 +1457,20 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) value = readl(reg); if (value & BYT_DIRECT_IRQ_EN) { - clear_bit(i, chip->irq.valid_mask); + clear_bit(i, valid_mask); dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { byt_gpio_clear_triggering(vg, i); dev_dbg(dev, "disabling GPIO %d\n", i); } } +} + +static int byt_gpio_irq_init_hw(struct gpio_chip *chip) +{ + struct byt_gpio *vg = gpiochip_get_data(chip); + void __iomem *reg; + u32 base, value; /* clear interrupt status trigger registers */ for (base = 0; base < vg->soc_data->npins; base += 32) { From faf86c0c572ad134003a5f5895a42a4749dae5f3 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Thu, 12 Dec 2019 08:35:52 +0200 Subject: [PATCH 18/99] pinctrl: baytrail: Use GPIO direction definitions Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen Acked-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index ea61a19857c1..0e131d2e094d 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1162,9 +1162,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) raw_spin_unlock_irqrestore(&byt_lock, flags); if (!(value & BYT_OUTPUT_EN)) - return 0; + return GPIO_LINE_DIRECTION_OUT; if (!(value & BYT_INPUT_EN)) - return 1; + return GPIO_LINE_DIRECTION_IN; return -EINVAL; } From 90a1eb18503d916ca5b089ef79d783c6dc6a5836 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Thu, 12 Dec 2019 08:35:19 +0200 Subject: [PATCH 19/99] pinctrl: cherryview: Use GPIO direction definitions Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 60527b93a711..4c74fdde576d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1289,7 +1289,10 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; - return direction != CHV_PADCTRL0_GPIOCFG_GPO; + if (direction == CHV_PADCTRL0_GPIOCFG_GPO) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; } static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) From 6a304752eb6934e4bfa236a346ae440c74e02e07 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Thu, 12 Dec 2019 08:34:32 +0200 Subject: [PATCH 20/99] pinctrl: intel: Use GPIO direction definitions Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 4860bc9a4e48..2ba2ad8a55d9 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -944,7 +944,10 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) if (padcfg0 & PADCFG0_PMODE_MASK) return -EINVAL; - return !!(padcfg0 & PADCFG0_GPIOTXDIS); + if (padcfg0 & PADCFG0_GPIOTXDIS) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; } static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) From 66c812d22ecdca74015477429a271697655dbfd4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 25 Oct 2019 12:10:28 +0300 Subject: [PATCH 21/99] pinctrl: intel: Share struct intel_pinctrl for wider use There are few drivers for Intel SoC GPIO which may utilize the same data structure to describe this IP. Share struct intel_pinctrl for wider user. Acked-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 35 +-------------------- drivers/pinctrl/intel/pinctrl-intel.h | 44 +++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 34 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 2ba2ad8a55d9..06be75a636ba 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -8,8 +8,8 @@ */ #include -#include #include +#include #include #include #include @@ -85,39 +85,6 @@ struct intel_community_context { u32 *hostown; }; -struct intel_pinctrl_context { - struct intel_pad_context *pads; - struct intel_community_context *communities; -}; - -/** - * struct intel_pinctrl - Intel pinctrl private structure - * @dev: Pointer to the device structure - * @lock: Lock to serialize register access - * @pctldesc: Pin controller description - * @pctldev: Pointer to the pin controller device - * @chip: GPIO chip in this pin controller - * @irqchip: IRQ chip in this pin controller - * @soc: SoC/PCH specific pin configuration data - * @communities: All communities in this pin controller - * @ncommunities: Number of communities in this pin controller - * @context: Configuration saved over system sleep - * @irq: pinctrl/GPIO chip irq number - */ -struct intel_pinctrl { - struct device *dev; - raw_spinlock_t lock; - struct pinctrl_desc pctldesc; - struct pinctrl_dev *pctldev; - struct gpio_chip chip; - struct irq_chip irqchip; - const struct intel_pinctrl_soc_data *soc; - struct intel_community *communities; - size_t ncommunities; - struct intel_pinctrl_context context; - int irq; -}; - #define pin_to_padno(c, p) ((p) - (c)->pin_base) #define padgroup_offset(g, p) ((p) - (g)->base) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 34b38a321760..c6f066f6d3fb 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -10,7 +10,10 @@ #ifndef PINCTRL_INTEL_H #define PINCTRL_INTEL_H +#include +#include #include +#include struct pinctrl_pin_desc; struct platform_device; @@ -174,6 +177,47 @@ struct intel_pinctrl_soc_data { size_t ncommunities; }; +struct intel_pad_context; +struct intel_community_context; + +/** + * struct intel_pinctrl_context - context to be saved during suspend-resume + * @pads: Opaque context per pad (driver dependent) + * @communities: Opaque context per community (driver dependent) + */ +struct intel_pinctrl_context { + struct intel_pad_context *pads; + struct intel_community_context *communities; +}; + +/** + * struct intel_pinctrl - Intel pinctrl private structure + * @dev: Pointer to the device structure + * @lock: Lock to serialize register access + * @pctldesc: Pin controller description + * @pctldev: Pointer to the pin controller device + * @chip: GPIO chip in this pin controller + * @irqchip: IRQ chip in this pin controller + * @soc: SoC/PCH specific pin configuration data + * @communities: All communities in this pin controller + * @ncommunities: Number of communities in this pin controller + * @context: Configuration saved over system sleep + * @irq: pinctrl/GPIO chip irq number + */ +struct intel_pinctrl { + struct device *dev; + raw_spinlock_t lock; + struct pinctrl_desc pctldesc; + struct pinctrl_dev *pctldev; + struct gpio_chip chip; + struct irq_chip irqchip; + const struct intel_pinctrl_soc_data *soc; + struct intel_community *communities; + size_t ncommunities; + struct intel_pinctrl_context context; + int irq; +}; + int intel_pinctrl_probe_by_hid(struct platform_device *pdev); int intel_pinctrl_probe_by_uid(struct platform_device *pdev); From 990ec243cb77c682e12bb84c98906880536132aa Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 17:56:41 +0200 Subject: [PATCH 22/99] pinctrl: baytrail: Keep pointer to struct device instead of its container There is no need to keep pointer to struct platform_device, which is container of struct device, because the latter is what have been used everywhere outside of ->probe() path. In any case we may derive pointer to the container when needed. Acked-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 58 ++++++++++++------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 0e131d2e094d..6e79138fc7f5 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -106,9 +106,9 @@ struct byt_gpio_pin_context { } struct byt_gpio { + struct device *dev; struct gpio_chip chip; struct irq_chip irqchip; - struct platform_device *pdev; struct pinctrl_dev *pctl_dev; struct pinctrl_desc pctl_desc; const struct intel_pinctrl_soc_data *soc_data; @@ -668,7 +668,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg, padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); if (!padcfg0) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Group %s, pin %i not muxed (no padcfg0)\n", group.name, i); continue; @@ -698,7 +698,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg, padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); if (!padcfg0) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Group %s, pin %i not muxed (no padcfg0)\n", group.name, i); continue; @@ -785,13 +785,12 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, value |= gpio_mux; writel(value, reg); - dev_warn(&vg->pdev->dev, FW_BUG - "pin %u forcibly re-configured as GPIO\n", offset); + dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset); } raw_spin_unlock_irqrestore(&byt_lock, flags); - pm_runtime_get(&vg->pdev->dev); + pm_runtime_get(vg->dev); return 0; } @@ -803,7 +802,7 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); byt_gpio_clear_triggering(vg, offset); - pm_runtime_put(&vg->pdev->dev); + pm_runtime_put(vg->dev); } static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, @@ -1013,7 +1012,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, if (val & BYT_INPUT_EN) { val &= ~BYT_INPUT_EN; writel(val, val_reg); - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "pin %u forcibly set to input mode\n", offset); } @@ -1035,7 +1034,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, if (val & BYT_INPUT_EN) { val &= ~BYT_INPUT_EN; writel(val, val_reg); - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "pin %u forcibly set to input mode\n", offset); } @@ -1412,7 +1411,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); if (!reg) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Pin %i: could not retrieve interrupt status register\n", base); continue; @@ -1434,7 +1433,6 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, unsigned int ngpios) { struct byt_gpio *vg = gpiochip_get_data(chip); - struct device *dev = &vg->pdev->dev; void __iomem *reg; u32 value; int i; @@ -1449,7 +1447,7 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Pin %i: could not retrieve conf0 register\n", i); continue; @@ -1458,10 +1456,10 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, value = readl(reg); if (value & BYT_DIRECT_IRQ_EN) { clear_bit(i, valid_mask); - dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); + dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i); } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { byt_gpio_clear_triggering(vg, i); - dev_dbg(dev, "disabling GPIO %d\n", i); + dev_dbg(vg->dev, "disabling GPIO %d\n", i); } } } @@ -1477,7 +1475,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); if (!reg) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Pin %i: could not retrieve irq status reg\n", base); continue; @@ -1488,7 +1486,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) might be misconfigured in bios */ value = readl(reg); if (value) - dev_err(&vg->pdev->dev, + dev_err(vg->dev, "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n", base / 32, value); } @@ -1499,7 +1497,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) { struct byt_gpio *vg = gpiochip_get_data(chip); - struct device *dev = &vg->pdev->dev; + struct device *dev = vg->dev; int ret; ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc_data->npins); @@ -1511,6 +1509,7 @@ static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) static int byt_gpio_probe(struct byt_gpio *vg) { + struct platform_device *pdev = to_platform_device(vg->dev); struct gpio_chip *gc; struct resource *irq_rc; int ret; @@ -1518,22 +1517,22 @@ static int byt_gpio_probe(struct byt_gpio *vg) /* Set up gpio chip */ vg->chip = byt_gpio_chip; gc = &vg->chip; - gc->label = dev_name(&vg->pdev->dev); + gc->label = dev_name(vg->dev); gc->base = -1; gc->can_sleep = false; gc->add_pin_ranges = byt_gpio_add_pin_ranges; - gc->parent = &vg->pdev->dev; + gc->parent = vg->dev; gc->ngpio = vg->soc_data->npins; #ifdef CONFIG_PM_SLEEP - vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, + vg->saved_context = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->saved_context), GFP_KERNEL); if (!vg->saved_context) return -ENOMEM; #endif /* set up interrupts */ - irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0); + irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (irq_rc && irq_rc->start) { struct gpio_irq_chip *girq; @@ -1550,7 +1549,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) girq->init_valid_mask = byt_init_irq_valid_mask; girq->parent_handler = byt_gpio_irq_handler; girq->num_parents = 1; - girq->parents = devm_kcalloc(&vg->pdev->dev, girq->num_parents, + girq->parents = devm_kcalloc(vg->dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; @@ -1559,9 +1558,9 @@ static int byt_gpio_probe(struct byt_gpio *vg) girq->handler = handle_bad_irq; } - ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); + ret = devm_gpiochip_add_data(vg->dev, gc, vg); if (ret) { - dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n"); + dev_err(vg->dev, "failed adding byt-gpio chip\n"); return ret; } @@ -1571,10 +1570,11 @@ static int byt_gpio_probe(struct byt_gpio *vg) static int byt_set_soc_data(struct byt_gpio *vg, const struct intel_pinctrl_soc_data *soc_data) { + struct platform_device *pdev = to_platform_device(vg->dev); int i; vg->soc_data = soc_data; - vg->communities_copy = devm_kcalloc(&vg->pdev->dev, + vg->communities_copy = devm_kcalloc(vg->dev, soc_data->ncommunities, sizeof(*vg->communities_copy), GFP_KERNEL); @@ -1586,7 +1586,7 @@ static int byt_set_soc_data(struct byt_gpio *vg, *comm = vg->soc_data->communities[i]; - comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0); + comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(comm->pad_regs)) return PTR_ERR(comm->pad_regs); } @@ -1628,7 +1628,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) if (!vg) return -ENOMEM; - vg->pdev = pdev; + vg->dev = &pdev->dev; ret = byt_set_soc_data(vg, soc_data); if (ret) { dev_err(&pdev->dev, "failed to set soc data\n"); @@ -1672,7 +1672,7 @@ static int byt_gpio_suspend(struct device *dev) reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Pin %i: could not retrieve conf0 register\n", i); continue; @@ -1704,7 +1704,7 @@ static int byt_gpio_resume(struct device *dev) reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { - dev_warn(&vg->pdev->dev, + dev_warn(vg->dev, "Pin %i: could not retrieve conf0 register\n", i); continue; From 2c02af709bff42e7a85e25c7ba8af7c55f034f27 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 18:34:43 +0200 Subject: [PATCH 23/99] pinctrl: baytrail: Use local variable to keep device pointer Use local variable to keep device pointer in order to increase readability of the driver. Acked-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 6e79138fc7f5..f6c9132b3b14 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1604,15 +1604,16 @@ static int byt_pinctrl_probe(struct platform_device *pdev) { const struct intel_pinctrl_soc_data *soc_data = NULL; const struct intel_pinctrl_soc_data **soc_table; + struct device *dev = &pdev->dev; struct acpi_device *acpi_dev; struct byt_gpio *vg; int i, ret; - acpi_dev = ACPI_COMPANION(&pdev->dev); + acpi_dev = ACPI_COMPANION(dev); if (!acpi_dev) return -ENODEV; - soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev); + soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev); for (i = 0; soc_table[i]; i++) { if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { @@ -1624,25 +1625,25 @@ static int byt_pinctrl_probe(struct platform_device *pdev) if (!soc_data) return -ENODEV; - vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL); + vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); if (!vg) return -ENOMEM; - vg->dev = &pdev->dev; + vg->dev = dev; ret = byt_set_soc_data(vg, soc_data); if (ret) { - dev_err(&pdev->dev, "failed to set soc data\n"); + dev_err(dev, "failed to set soc data\n"); return ret; } vg->pctl_desc = byt_pinctrl_desc; - vg->pctl_desc.name = dev_name(&pdev->dev); + vg->pctl_desc.name = dev_name(dev); vg->pctl_desc.pins = vg->soc_data->pins; vg->pctl_desc.npins = vg->soc_data->npins; - vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg); + vg->pctl_dev = devm_pinctrl_register(dev, &vg->pctl_desc, vg); if (IS_ERR(vg->pctl_dev)) { - dev_err(&pdev->dev, "failed to register pinctrl driver\n"); + dev_err(dev, "failed to register pinctrl driver\n"); return PTR_ERR(vg->pctl_dev); } @@ -1651,7 +1652,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) return ret; platform_set_drvdata(pdev, vg); - pm_runtime_enable(&pdev->dev); + pm_runtime_enable(dev); return 0; } From 5d33e0eb7ffa2a4f4c431af1deca49f433faba8a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 18:37:22 +0200 Subject: [PATCH 24/99] pinctrl: baytrail: Reuse struct intel_pinctrl in the driver We may use now available struct intel_pinctrl in the driver. No functional change implied. Acked-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 186 +++++++++++------------ 1 file changed, 87 insertions(+), 99 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index f6c9132b3b14..cb0c04c5269c 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -93,7 +93,7 @@ #define BYT_DEFAULT_GPIO_MUX 0 #define BYT_ALTER_GPIO_MUX 1 -struct byt_gpio_pin_context { +struct intel_pad_context { u32 conf0; u32 val; }; @@ -105,17 +105,6 @@ struct byt_gpio_pin_context { .pad_map = (map),\ } -struct byt_gpio { - struct device *dev; - struct gpio_chip chip; - struct irq_chip irqchip; - struct pinctrl_dev *pctl_dev; - struct pinctrl_desc pctl_desc; - const struct intel_pinctrl_soc_data *soc_data; - struct intel_community *communities_copy; - struct byt_gpio_pin_context *saved_context; -}; - /* SCORE pins, aka GPIOC_ or GPIO_S0_SC[] */ static const struct pinctrl_pin_desc byt_score_pins[] = { PINCTRL_PIN(0, "SATA_GP0"), @@ -551,14 +540,14 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = { static DEFINE_RAW_SPINLOCK(byt_lock); -static struct intel_community *byt_get_community(struct byt_gpio *vg, +static struct intel_community *byt_get_community(struct intel_pinctrl *vg, unsigned int pin) { struct intel_community *comm; int i; - for (i = 0; i < vg->soc_data->ncommunities; i++) { - comm = vg->communities_copy + i; + for (i = 0; i < vg->ncommunities; i++) { + comm = vg->communities + i; if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) return comm; } @@ -566,7 +555,7 @@ static struct intel_community *byt_get_community(struct byt_gpio *vg, return NULL; } -static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, +static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, int reg) { struct intel_community *comm = byt_get_community(vg, offset); @@ -593,17 +582,17 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, static int byt_get_groups_count(struct pinctrl_dev *pctldev) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - return vg->soc_data->ngroups; + return vg->soc->ngroups; } static const char *byt_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - return vg->soc_data->groups[selector].name; + return vg->soc->groups[selector].name; } static int byt_get_group_pins(struct pinctrl_dev *pctldev, @@ -611,10 +600,10 @@ static int byt_get_group_pins(struct pinctrl_dev *pctldev, const unsigned int **pins, unsigned int *num_pins) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - *pins = vg->soc_data->groups[selector].pins; - *num_pins = vg->soc_data->groups[selector].npins; + *pins = vg->soc->groups[selector].pins; + *num_pins = vg->soc->groups[selector].npins; return 0; } @@ -627,17 +616,17 @@ static const struct pinctrl_ops byt_pinctrl_ops = { static int byt_get_functions_count(struct pinctrl_dev *pctldev) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - return vg->soc_data->nfunctions; + return vg->soc->nfunctions; } static const char *byt_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - return vg->soc_data->functions[selector].name; + return vg->soc->functions[selector].name; } static int byt_get_function_groups(struct pinctrl_dev *pctldev, @@ -645,15 +634,15 @@ static int byt_get_function_groups(struct pinctrl_dev *pctldev, const char * const **groups, unsigned int *num_groups) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - *groups = vg->soc_data->functions[selector].groups; - *num_groups = vg->soc_data->functions[selector].ngroups; + *groups = vg->soc->functions[selector].groups; + *num_groups = vg->soc->functions[selector].ngroups; return 0; } -static void byt_set_group_simple_mux(struct byt_gpio *vg, +static void byt_set_group_simple_mux(struct intel_pinctrl *vg, const struct intel_pingroup group, unsigned int func) { @@ -683,7 +672,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg, raw_spin_unlock_irqrestore(&byt_lock, flags); } -static void byt_set_group_mixed_mux(struct byt_gpio *vg, +static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, const struct intel_pingroup group, const unsigned int *func) { @@ -716,9 +705,9 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg, static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, unsigned int group_selector) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); - const struct intel_function func = vg->soc_data->functions[func_selector]; - const struct intel_pingroup group = vg->soc_data->groups[group_selector]; + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); + const struct intel_function func = vg->soc->functions[func_selector]; + const struct intel_pingroup group = vg->soc->groups[group_selector]; if (group.modes) byt_set_group_mixed_mux(vg, group, group.modes); @@ -730,22 +719,22 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, return 0; } -static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset) +static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) { /* SCORE pin 92-93 */ - if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) && + if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && offset >= 92 && offset <= 93) return BYT_ALTER_GPIO_MUX; /* SUS pin 11-21 */ - if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) && + if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && offset >= 11 && offset <= 21) return BYT_ALTER_GPIO_MUX; return BYT_DEFAULT_GPIO_MUX; } -static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) +static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) { void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); unsigned long flags; @@ -762,7 +751,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, struct pinctrl_gpio_range *range, unsigned int offset) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); u32 value, gpio_mux; unsigned long flags; @@ -799,7 +788,7 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, struct pinctrl_gpio_range *range, unsigned int offset) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); byt_gpio_clear_triggering(vg, offset); pm_runtime_put(vg->dev); @@ -810,7 +799,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, unsigned int offset, bool input) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); unsigned long flags; @@ -893,7 +882,7 @@ static int byt_set_pull_strength(u32 *reg, u16 strength) static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, unsigned long *config) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); enum pin_config_param param = pinconf_to_config_param(*config); void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); @@ -978,7 +967,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, unsigned long *configs, unsigned int num_configs) { - struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); + struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); unsigned int param, arg; void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); @@ -1115,7 +1104,7 @@ static const struct pinctrl_desc byt_pinctrl_desc = { static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); unsigned long flags; u32 val; @@ -1129,7 +1118,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); unsigned long flags; u32 old_val; @@ -1148,7 +1137,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); unsigned long flags; u32 value; @@ -1188,11 +1177,11 @@ static int byt_gpio_direction_output(struct gpio_chip *chip, static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); int i; u32 conf0, val; - for (i = 0; i < vg->soc_data->npins; i++) { + for (i = 0; i < vg->soc->npins; i++) { const struct intel_community *comm; const char *pull_str = NULL; const char *pull = NULL; @@ -1202,7 +1191,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned int pin; raw_spin_lock_irqsave(&byt_lock, flags); - pin = vg->soc_data->pins[i].number; + pin = vg->soc->pins[i].number; reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { seq_printf(s, @@ -1297,7 +1286,7 @@ static const struct gpio_chip byt_gpio_chip = { static void byt_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct byt_gpio *vg = gpiochip_get_data(gc); + struct intel_pinctrl *vg = gpiochip_get_data(gc); unsigned int offset = irqd_to_hwirq(d); void __iomem *reg; @@ -1313,7 +1302,7 @@ static void byt_irq_ack(struct irq_data *d) static void byt_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct byt_gpio *vg = gpiochip_get_data(gc); + struct intel_pinctrl *vg = gpiochip_get_data(gc); byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); } @@ -1321,7 +1310,7 @@ static void byt_irq_mask(struct irq_data *d) static void byt_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct byt_gpio *vg = gpiochip_get_data(gc); + struct intel_pinctrl *vg = gpiochip_get_data(gc); unsigned int offset = irqd_to_hwirq(d); unsigned long flags; void __iomem *reg; @@ -1359,7 +1348,7 @@ static void byt_irq_unmask(struct irq_data *d) static int byt_irq_type(struct irq_data *d, unsigned int type) { - struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); u32 offset = irqd_to_hwirq(d); u32 value; unsigned long flags; @@ -1398,8 +1387,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) static void byt_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); - struct byt_gpio *vg = gpiochip_get_data( - irq_desc_get_handler_data(desc)); + struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); struct irq_chip *chip = irq_data_get_irq_chip(data); u32 base, pin; void __iomem *reg; @@ -1432,7 +1420,7 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); void __iomem *reg; u32 value; int i; @@ -1442,8 +1430,8 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, * do not use direct IRQ mode. This will prevent spurious * interrupts from misconfigured pins. */ - for (i = 0; i < vg->soc_data->npins; i++) { - unsigned int pin = vg->soc_data->pins[i].number; + for (i = 0; i < vg->soc->npins; i++) { + unsigned int pin = vg->soc->pins[i].number; reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { @@ -1466,12 +1454,12 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, static int byt_gpio_irq_init_hw(struct gpio_chip *chip) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); void __iomem *reg; u32 base, value; /* clear interrupt status trigger registers */ - for (base = 0; base < vg->soc_data->npins; base += 32) { + for (base = 0; base < vg->soc->npins; base += 32) { reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); if (!reg) { @@ -1496,18 +1484,18 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) { - struct byt_gpio *vg = gpiochip_get_data(chip); + struct intel_pinctrl *vg = gpiochip_get_data(chip); struct device *dev = vg->dev; int ret; - ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc_data->npins); + ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); if (ret) dev_err(dev, "failed to add GPIO pin range\n"); return ret; } -static int byt_gpio_probe(struct byt_gpio *vg) +static int byt_gpio_probe(struct intel_pinctrl *vg) { struct platform_device *pdev = to_platform_device(vg->dev); struct gpio_chip *gc; @@ -1522,12 +1510,12 @@ static int byt_gpio_probe(struct byt_gpio *vg) gc->can_sleep = false; gc->add_pin_ranges = byt_gpio_add_pin_ranges; gc->parent = vg->dev; - gc->ngpio = vg->soc_data->npins; + gc->ngpio = vg->soc->npins; #ifdef CONFIG_PM_SLEEP - vg->saved_context = devm_kcalloc(vg->dev, gc->ngpio, - sizeof(*vg->saved_context), GFP_KERNEL); - if (!vg->saved_context) + vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), + GFP_KERNEL); + if (!vg->context.pads) return -ENOMEM; #endif @@ -1567,24 +1555,24 @@ static int byt_gpio_probe(struct byt_gpio *vg) return ret; } -static int byt_set_soc_data(struct byt_gpio *vg, - const struct intel_pinctrl_soc_data *soc_data) +static int byt_set_soc_data(struct intel_pinctrl *vg, + const struct intel_pinctrl_soc_data *soc) { struct platform_device *pdev = to_platform_device(vg->dev); int i; - vg->soc_data = soc_data; - vg->communities_copy = devm_kcalloc(vg->dev, - soc_data->ncommunities, - sizeof(*vg->communities_copy), - GFP_KERNEL); - if (!vg->communities_copy) + vg->soc = soc; + + vg->ncommunities = vg->soc->ncommunities; + vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, + sizeof(*vg->communities), GFP_KERNEL); + if (!vg->communities) return -ENOMEM; - for (i = 0; i < soc_data->ncommunities; i++) { - struct intel_community *comm = vg->communities_copy + i; + for (i = 0; i < vg->soc->ncommunities; i++) { + struct intel_community *comm = vg->communities + i; - *comm = vg->soc_data->communities[i]; + *comm = vg->soc->communities[i]; comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(comm->pad_regs)) @@ -1606,7 +1594,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) const struct intel_pinctrl_soc_data **soc_table; struct device *dev = &pdev->dev; struct acpi_device *acpi_dev; - struct byt_gpio *vg; + struct intel_pinctrl *vg; int i, ret; acpi_dev = ACPI_COMPANION(dev); @@ -1636,15 +1624,15 @@ static int byt_pinctrl_probe(struct platform_device *pdev) return ret; } - vg->pctl_desc = byt_pinctrl_desc; - vg->pctl_desc.name = dev_name(dev); - vg->pctl_desc.pins = vg->soc_data->pins; - vg->pctl_desc.npins = vg->soc_data->npins; + vg->pctldesc = byt_pinctrl_desc; + vg->pctldesc.name = dev_name(dev); + vg->pctldesc.pins = vg->soc->pins; + vg->pctldesc.npins = vg->soc->npins; - vg->pctl_dev = devm_pinctrl_register(dev, &vg->pctl_desc, vg); - if (IS_ERR(vg->pctl_dev)) { + vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); + if (IS_ERR(vg->pctldev)) { dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(vg->pctl_dev); + return PTR_ERR(vg->pctldev); } ret = byt_gpio_probe(vg); @@ -1660,16 +1648,16 @@ static int byt_pinctrl_probe(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP static int byt_gpio_suspend(struct device *dev) { - struct byt_gpio *vg = dev_get_drvdata(dev); + struct intel_pinctrl *vg = dev_get_drvdata(dev); unsigned long flags; int i; raw_spin_lock_irqsave(&byt_lock, flags); - for (i = 0; i < vg->soc_data->npins; i++) { + for (i = 0; i < vg->soc->npins; i++) { void __iomem *reg; u32 value; - unsigned int pin = vg->soc_data->pins[i].number; + unsigned int pin = vg->soc->pins[i].number; reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { @@ -1679,11 +1667,11 @@ static int byt_gpio_suspend(struct device *dev) continue; } value = readl(reg) & BYT_CONF0_RESTORE_MASK; - vg->saved_context[i].conf0 = value; + vg->context.pads[i].conf0 = value; reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); value = readl(reg) & BYT_VAL_RESTORE_MASK; - vg->saved_context[i].val = value; + vg->context.pads[i].val = value; } raw_spin_unlock_irqrestore(&byt_lock, flags); @@ -1692,16 +1680,16 @@ static int byt_gpio_suspend(struct device *dev) static int byt_gpio_resume(struct device *dev) { - struct byt_gpio *vg = dev_get_drvdata(dev); + struct intel_pinctrl *vg = dev_get_drvdata(dev); unsigned long flags; int i; raw_spin_lock_irqsave(&byt_lock, flags); - for (i = 0; i < vg->soc_data->npins; i++) { + for (i = 0; i < vg->soc->npins; i++) { void __iomem *reg; u32 value; - unsigned int pin = vg->soc_data->pins[i].number; + unsigned int pin = vg->soc->pins[i].number; reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); if (!reg) { @@ -1712,9 +1700,9 @@ static int byt_gpio_resume(struct device *dev) } value = readl(reg); if ((value & BYT_CONF0_RESTORE_MASK) != - vg->saved_context[i].conf0) { + vg->context.pads[i].conf0) { value &= ~BYT_CONF0_RESTORE_MASK; - value |= vg->saved_context[i].conf0; + value |= vg->context.pads[i].conf0; writel(value, reg); dev_info(dev, "restored pin %d conf0 %#08x", i, value); } @@ -1722,11 +1710,11 @@ static int byt_gpio_resume(struct device *dev) reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); value = readl(reg); if ((value & BYT_VAL_RESTORE_MASK) != - vg->saved_context[i].val) { + vg->context.pads[i].val) { u32 v; v = value & ~BYT_VAL_RESTORE_MASK; - v |= vg->saved_context[i].val; + v |= vg->context.pads[i].val; if (v != value) { writel(v, reg); dev_dbg(dev, "restored pin %d val %#08x\n", From eb83479e18999e34b3b800f54aa31137f7f41c33 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 22 Aug 2019 18:40:50 +0300 Subject: [PATCH 25/99] pinctrl: lynxpoint: Move GPIO driver to pin controller folder Move Lynxpoint GPIO driver under Intel pin control umbrella for further transformation to a real pin control driver. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- MAINTAINERS | 1 - drivers/gpio/Kconfig | 8 -------- drivers/gpio/Makefile | 1 - drivers/pinctrl/intel/Kconfig | 10 ++++++++++ drivers/pinctrl/intel/Makefile | 1 + .../intel/pinctrl-lynxpoint.c} | 0 6 files changed, 11 insertions(+), 10 deletions(-) rename drivers/{gpio/gpio-lynxpoint.c => pinctrl/intel/pinctrl-lynxpoint.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index bd5847e802de..6ea3cba0a9b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8344,7 +8344,6 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git F: drivers/gpio/gpio-ich.c F: drivers/gpio/gpio-intel-mid.c -F: drivers/gpio/gpio-lynxpoint.c F: drivers/gpio/gpio-merrifield.c F: drivers/gpio/gpio-ml-ioh.c F: drivers/gpio/gpio-pch.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8adffd42f8cb..6923142fd874 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -335,14 +335,6 @@ config GPIO_LPC32XX Select this option to enable GPIO driver for NXP LPC32XX devices. -config GPIO_LYNXPOINT - tristate "Intel Lynxpoint GPIO support" - depends on ACPI && X86 - select GPIOLIB_IRQCHIP - help - driver for GPIO functionality on Intel Lynxpoint PCH chipset - Requires ACPI device enumeration code to set up a platform device. - config GPIO_MB86S7X tristate "GPIO support for Fujitsu MB86S7x Platforms" help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 34eb8b2b12dd..55b2b645391e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -76,7 +76,6 @@ obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o -obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 6091947a8f51..c2e6bc9e3e04 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -31,6 +31,16 @@ config PINCTRL_CHERRYVIEW Cherryview/Braswell pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. +config PINCTRL_LYNXPOINT + tristate "Intel Lynxpoint pinctrl and GPIO driver" + depends on ACPI + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Lynxpoint is the PCH of Intel Haswell. This pinctrl driver + provides an interface that allows configuring of PCH pins and + using them as GPIOs. + config PINCTRL_MERRIFIELD tristate "Intel Merrifield pinctrl driver" depends on X86_INTEL_MID diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 7e620b471ef6..f60f99cfa7aa 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o +obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o diff --git a/drivers/gpio/gpio-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c similarity index 100% rename from drivers/gpio/gpio-lynxpoint.c rename to drivers/pinctrl/intel/pinctrl-lynxpoint.c From b2e05d63c295529879aabeb8781f947e1e2dca7b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 18 Nov 2019 20:04:54 +0200 Subject: [PATCH 26/99] pinctrl: lynxpoint: Use raw_spinlock for locking The Intel Lynxpoint pinctrl driver implements irqchip callbacks which are called with desc->lock raw_spinlock held. In mainline this is fine because spinlock resolves to raw_spinlock. However, running the same code in -rt we will get a BUG() asserted. This is because in -rt spinlocks are preemptible so taking the driver private spinlock in irqchip callbacks causes might_sleep() to trigger. In order to keep -rt happy but at the same time make sure that register accesses get serialized, convert the driver to use raw_spinlock instead. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 490ce7bae25e..c30fd86846a7 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -47,7 +47,7 @@ struct lp_gpio { struct gpio_chip chip; struct platform_device *pdev; - spinlock_t lock; + raw_spinlock_t lock; unsigned long reg_base; }; @@ -144,7 +144,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type) if (hwirq >= lg->chip.ngpio) return -EINVAL; - spin_lock_irqsave(&lg->lock, flags); + raw_spin_lock_irqsave(&lg->lock, flags); value = inl(reg); /* set both TRIG_SEL and INV bits to 0 for rising edge */ @@ -170,7 +170,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type) else if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); - spin_unlock_irqrestore(&lg->lock, flags); + raw_spin_unlock_irqrestore(&lg->lock, flags); return 0; } @@ -187,14 +187,14 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; - spin_lock_irqsave(&lg->lock, flags); + raw_spin_lock_irqsave(&lg->lock, flags); if (value) outl(inl(reg) | OUT_LVL_BIT, reg); else outl(inl(reg) & ~OUT_LVL_BIT, reg); - spin_unlock_irqrestore(&lg->lock, flags); + raw_spin_unlock_irqrestore(&lg->lock, flags); } static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) @@ -203,9 +203,9 @@ static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; - spin_lock_irqsave(&lg->lock, flags); + raw_spin_lock_irqsave(&lg->lock, flags); outl(inl(reg) | DIR_BIT, reg); - spin_unlock_irqrestore(&lg->lock, flags); + raw_spin_unlock_irqrestore(&lg->lock, flags); return 0; } @@ -219,9 +219,9 @@ static int lp_gpio_direction_output(struct gpio_chip *chip, lp_gpio_set(chip, offset, value); - spin_lock_irqsave(&lg->lock, flags); + raw_spin_lock_irqsave(&lg->lock, flags); outl(inl(reg) & ~DIR_BIT, reg); - spin_unlock_irqrestore(&lg->lock, flags); + raw_spin_unlock_irqrestore(&lg->lock, flags); return 0; } @@ -272,9 +272,9 @@ static void lp_irq_enable(struct irq_data *d) unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; - spin_lock_irqsave(&lg->lock, flags); + raw_spin_lock_irqsave(&lg->lock, flags); outl(inl(reg) | BIT(hwirq % 32), reg); - spin_unlock_irqrestore(&lg->lock, flags); + raw_spin_unlock_irqrestore(&lg->lock, flags); } static void lp_irq_disable(struct irq_data *d) @@ -285,9 +285,9 @@ static void lp_irq_disable(struct irq_data *d) unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; - spin_lock_irqsave(&lg->lock, flags); + raw_spin_lock_irqsave(&lg->lock, flags); outl(inl(reg) & ~BIT(hwirq % 32), reg); - spin_unlock_irqrestore(&lg->lock, flags); + raw_spin_unlock_irqrestore(&lg->lock, flags); } static struct irq_chip lp_irqchip = { @@ -351,7 +351,7 @@ static int lp_gpio_probe(struct platform_device *pdev) return -EBUSY; } - spin_lock_init(&lg->lock); + raw_spin_lock_init(&lg->lock); gc = &lg->chip; gc->label = dev_name(dev); From 7c0bc7bb39ac89a454317d55262c06ec0048628b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 25 Oct 2019 21:25:43 +0300 Subject: [PATCH 27/99] pinctrl: lynxpoint: Correct amount of pins When we count from 0 it's possible to get into off-by-one error. That's what had happened to this driver. So, correct amount of pins and related typos in the code. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index c30fd86846a7..162fc38c929d 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -18,9 +18,9 @@ #include #include -/* LynxPoint chipset has support for 94 gpio pins */ +/* LynxPoint chipset has support for 95 GPIO pins */ -#define LP_NUM_GPIO 94 +#define LP_NUM_GPIO 95 /* Bitmapped register offsets */ #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ @@ -54,11 +54,11 @@ struct lp_gpio { /* * Lynxpoint gpios are controlled through both bitmapped registers and * per gpio specific registers. The bitmapped registers are in chunks of - * 3 x 32bit registers to cover all 94 gpios + * 3 x 32bit registers to cover all 95 GPIOs * * per gpio specific registers consist of two 32bit registers per gpio - * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of - * 188 config registers. + * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of + * 190 config registers. * * A simplified view of the register layout look like this: * @@ -67,7 +67,7 @@ struct lp_gpio { * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 * ... * LP_INT_ENABLE[31:0] ... - * LP_INT_ENABLE[63:31] ... + * LP_INT_ENABLE[63:32] ... * LP_INT_ENABLE[94:64] ... * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 From 3b4c2d8ef0bd88828336e0690459d1b2120eb9e4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 18:01:19 +0200 Subject: [PATCH 28/99] pinctrl: lynxpoint: Drop useless assignment There is no need to assign ret variable in ->probe(). Drop useless assignment. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 162fc38c929d..6f074323e00e 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -325,7 +325,7 @@ static int lp_gpio_probe(struct platform_device *pdev) struct resource *io_rc, *irq_rc; struct device *dev = &pdev->dev; unsigned long reg_len; - int ret = -ENODEV; + int ret; lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL); if (!lg) From caedcbd053bca446f8d66faf74adeb8eb3d2913f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 25 Oct 2019 20:23:46 +0300 Subject: [PATCH 29/99] pinctrl: lynxpoint: Use %pR to print IO resource Replace explicit casting by pointer to struct resource with specifier replacement to %pR to print the IO resource. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 6f074323e00e..36978a7c2a85 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -346,8 +346,7 @@ static int lp_gpio_probe(struct platform_device *pdev) reg_len = resource_size(io_rc); if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) { - dev_err(dev, "failed requesting IO region 0x%x\n", - (unsigned int)lg->reg_base); + dev_err(dev, "failed requesting IO region %pR\n", &io_rc); return -EBUSY; } From a718e68ede16957e091ee8f35f7b73765e51a092 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 18:26:35 +0200 Subject: [PATCH 30/99] pinctrl: lynxpoint: Use standard pattern for memory allocation The pattern foo = kmalloc(sizeof(*foo), GFP_KERNEL); has an advantage when foo type is changed. Since we are planning a such, better to be prepared by using standard pattern for memory allocation. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 36978a7c2a85..17a7843c8dc9 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -327,7 +327,7 @@ static int lp_gpio_probe(struct platform_device *pdev) unsigned long reg_len; int ret; - lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL); + lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); if (!lg) return -ENOMEM; From 76347d7ad250b46c4dbeb0e1fe629ed3c72cf004 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 19:15:34 +0200 Subject: [PATCH 31/99] pinctrl: lynxpoint: Assume 2 bits for mode selector New generations can use 2 bits for mode selector. Update the code to support it. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 17a7843c8dc9..4b2e3f298641 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -38,7 +38,9 @@ #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ -#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */ +#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ +#define USE_SEL_NATIVE (0 << 0) +#define USE_SEL_GPIO (1 << 0) /* LP_CONFIG2 reg bits */ #define GPINDIS_BIT BIT(2) /* disable input sensing */ @@ -111,7 +113,7 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) return -EBUSY; } /* Fail if pin is in alternate function mode (not GPIO mode) */ - if (!(inl(reg) & USE_SEL_BIT)) + if ((inl(reg) & USE_SEL_MASK) != USE_SEL_GPIO) return -ENODEV; /* enable input sensing */ From 03fb681badafa3035d2af4cb48870f69ad993dcb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 19:19:56 +0200 Subject: [PATCH 32/99] pinctrl: lynxpoint: Relax GPIO request rules A pin in native mode still can be requested as GPIO, though we assume that firmware has configured it properly, which sometimes is not the case. Here we allow turning the pin as GPIO to avoid potential issues, but issue warning that something might be wrong. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 4b2e3f298641..3ac95f9d6a7f 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -104,6 +104,7 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); + u32 value; pm_runtime_get(&lg->pdev->dev); /* should we put if failed */ @@ -112,9 +113,16 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset); return -EBUSY; } - /* Fail if pin is in alternate function mode (not GPIO mode) */ - if ((inl(reg) & USE_SEL_MASK) != USE_SEL_GPIO) - return -ENODEV; + + /* + * Reconfigure pin to GPIO mode if needed and issue a warning, + * since we expect firmware to configure it properly. + */ + value = inl(reg); + if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { + outl((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); + dev_warn(&lg->pdev->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); + } /* enable input sensing */ outl(inl(conf2) & ~GPINDIS_BIT, conf2); From 1e78ea71226b68cec24dca53c53e673de60211bf Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 25 Oct 2019 11:56:11 +0300 Subject: [PATCH 33/99] pinctrl: lynxpoint: Keep pointer to struct device instead of its container There is no need to keep pointer to struct platform_device, which is container of struct device, because the latter is what have been used everywhere outside of ->probe() path. In any case we may derive pointer to the container when needed. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 3ac95f9d6a7f..1d5f5053fe14 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -48,7 +48,7 @@ struct lp_gpio { struct gpio_chip chip; - struct platform_device *pdev; + struct device *dev; raw_spinlock_t lock; unsigned long reg_base; }; @@ -106,11 +106,11 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); u32 value; - pm_runtime_get(&lg->pdev->dev); /* should we put if failed */ + pm_runtime_get(lg->dev); /* should we put if failed */ /* Fail if BIOS reserved pin for ACPI use */ if (!(inl(acpi_use) & BIT(offset % 32))) { - dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset); + dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset); return -EBUSY; } @@ -121,7 +121,7 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) value = inl(reg); if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { outl((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); - dev_warn(&lg->pdev->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); + dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); } /* enable input sensing */ @@ -139,7 +139,7 @@ static void lp_gpio_free(struct gpio_chip *chip, unsigned offset) /* disable input sensing */ outl(inl(conf2) | GPINDIS_BIT, conf2); - pm_runtime_put(&lg->pdev->dev); + pm_runtime_put(lg->dev); } static int lp_irq_type(struct irq_data *d, unsigned type) @@ -341,7 +341,7 @@ static int lp_gpio_probe(struct platform_device *pdev) if (!lg) return -ENOMEM; - lg->pdev = pdev; + lg->dev = dev; platform_set_drvdata(pdev, lg); io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); @@ -385,7 +385,7 @@ static int lp_gpio_probe(struct platform_device *pdev) girq->init_hw = lp_gpio_irq_init_hw; girq->parent_handler = lp_gpio_irq_handler; girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, + girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) From e1940adeb17b33bb30ce02abe257c80a492f1707 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 19:30:31 +0200 Subject: [PATCH 34/99] pinctrl: lynxpoint: Switch to memory mapped IO accessors Convert driver to use memory mapped IO accessors. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 88 +++++++++++------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 1d5f5053fe14..4ed2d4daea19 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -50,7 +50,7 @@ struct lp_gpio { struct gpio_chip chip; struct device *dev; raw_spinlock_t lock; - unsigned long reg_base; + void __iomem *regs; }; /* @@ -82,7 +82,7 @@ struct lp_gpio { * LP94_CONFIG2 (gpio 94) ... */ -static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset, +static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned offset, int reg) { struct lp_gpio *lg = gpiochip_get_data(chip); @@ -95,21 +95,21 @@ static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset, /* bitmapped registers */ reg_offset = (offset / 32) * 4; - return lg->reg_base + reg + reg_offset; + return lg->regs + reg + reg_offset; } static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) { struct lp_gpio *lg = gpiochip_get_data(chip); - unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); - unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); - unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); + void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); + void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); + void __iomem *acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); u32 value; pm_runtime_get(lg->dev); /* should we put if failed */ /* Fail if BIOS reserved pin for ACPI use */ - if (!(inl(acpi_use) & BIT(offset % 32))) { + if (!(ioread32(acpi_use) & BIT(offset % 32))) { dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset); return -EBUSY; } @@ -118,14 +118,14 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) * Reconfigure pin to GPIO mode if needed and issue a warning, * since we expect firmware to configure it properly. */ - value = inl(reg); + value = ioread32(reg); if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { - outl((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); + iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); } /* enable input sensing */ - outl(inl(conf2) & ~GPINDIS_BIT, conf2); + iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); return 0; @@ -134,10 +134,10 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) static void lp_gpio_free(struct gpio_chip *chip, unsigned offset) { struct lp_gpio *lg = gpiochip_get_data(chip); - unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); + void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); /* disable input sensing */ - outl(inl(conf2) | GPINDIS_BIT, conf2); + iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); pm_runtime_put(lg->dev); } @@ -147,15 +147,15 @@ static int lp_irq_type(struct irq_data *d, unsigned type) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct lp_gpio *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); + void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); unsigned long flags; u32 value; - unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); if (hwirq >= lg->chip.ngpio) return -EINVAL; raw_spin_lock_irqsave(&lg->lock, flags); - value = inl(reg); + value = ioread32(reg); /* set both TRIG_SEL and INV bits to 0 for rising edge */ if (type & IRQ_TYPE_EDGE_RISING) @@ -173,7 +173,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type) if (type & IRQ_TYPE_LEVEL_HIGH) value |= TRIG_SEL_BIT | INT_INV_BIT; - outl(value, reg); + iowrite32(value, reg); if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); @@ -187,22 +187,22 @@ static int lp_irq_type(struct irq_data *d, unsigned type) static int lp_gpio_get(struct gpio_chip *chip, unsigned offset) { - unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); - return !!(inl(reg) & IN_LVL_BIT); + void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); + return !!(ioread32(reg) & IN_LVL_BIT); } static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct lp_gpio *lg = gpiochip_get_data(chip); - unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); + void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; raw_spin_lock_irqsave(&lg->lock, flags); if (value) - outl(inl(reg) | OUT_LVL_BIT, reg); + iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); else - outl(inl(reg) & ~OUT_LVL_BIT, reg); + iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); raw_spin_unlock_irqrestore(&lg->lock, flags); } @@ -210,11 +210,11 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct lp_gpio *lg = gpiochip_get_data(chip); - unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); + void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; raw_spin_lock_irqsave(&lg->lock, flags); - outl(inl(reg) | DIR_BIT, reg); + iowrite32(ioread32(reg) | DIR_BIT, reg); raw_spin_unlock_irqrestore(&lg->lock, flags); return 0; @@ -224,13 +224,13 @@ static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { struct lp_gpio *lg = gpiochip_get_data(chip); - unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); + void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; lp_gpio_set(chip, offset, value); raw_spin_lock_irqsave(&lg->lock, flags); - outl(inl(reg) & ~DIR_BIT, reg); + iowrite32(ioread32(reg) & ~DIR_BIT, reg); raw_spin_unlock_irqrestore(&lg->lock, flags); return 0; @@ -242,7 +242,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct lp_gpio *lg = gpiochip_get_data(gc); struct irq_chip *chip = irq_data_get_irq_chip(data); - unsigned long reg, ena, pending; + void __iomem *reg, *ena; + unsigned long pending; u32 base, pin; /* check from GPIO controller which pin triggered the interrupt */ @@ -251,13 +252,13 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); /* Only interrupts that are enabled */ - pending = inl(reg) & inl(ena); + pending = ioread32(reg) & ioread32(ena); for_each_set_bit(pin, &pending, 32) { unsigned irq; /* Clear before handling so we don't lose an edge */ - outl(BIT(pin), reg); + iowrite32(BIT(pin), reg); irq = irq_find_mapping(lg->chip.irq.domain, base + pin); generic_handle_irq(irq); @@ -279,11 +280,11 @@ static void lp_irq_enable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct lp_gpio *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); - unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); + void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; raw_spin_lock_irqsave(&lg->lock, flags); - outl(inl(reg) | BIT(hwirq % 32), reg); + iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); raw_spin_unlock_irqrestore(&lg->lock, flags); } @@ -292,11 +293,11 @@ static void lp_irq_disable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct lp_gpio *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); - unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); + void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; raw_spin_lock_irqsave(&lg->lock, flags); - outl(inl(reg) & ~BIT(hwirq % 32), reg); + iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); raw_spin_unlock_irqrestore(&lg->lock, flags); } @@ -313,16 +314,16 @@ static struct irq_chip lp_irqchip = { static int lp_gpio_irq_init_hw(struct gpio_chip *chip) { struct lp_gpio *lg = gpiochip_get_data(chip); - unsigned long reg; + void __iomem *reg; unsigned base; for (base = 0; base < lg->chip.ngpio; base += 32) { /* disable gpio pin interrupts */ reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); - outl(0, reg); + iowrite32(0, reg); /* Clear interrupt status register */ reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); - outl(0xffffffff, reg); + iowrite32(0xffffffff, reg); } return 0; @@ -334,7 +335,7 @@ static int lp_gpio_probe(struct platform_device *pdev) struct gpio_chip *gc; struct resource *io_rc, *irq_rc; struct device *dev = &pdev->dev; - unsigned long reg_len; + void __iomem *regs; int ret; lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); @@ -345,21 +346,19 @@ static int lp_gpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, lg); io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!io_rc) { dev_err(dev, "missing IO resources\n"); return -EINVAL; } - lg->reg_base = io_rc->start; - reg_len = resource_size(io_rc); - - if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) { - dev_err(dev, "failed requesting IO region %pR\n", &io_rc); + regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); + if (!regs) { + dev_err(dev, "failed mapping IO region %pR\n", &io_rc); return -EBUSY; } + lg->regs = regs; + raw_spin_lock_init(&lg->lock); gc = &lg->chip; @@ -377,6 +376,7 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->parent = dev; /* set up interrupts */ + irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (irq_rc && irq_rc->start) { struct gpio_irq_chip *girq; @@ -419,14 +419,14 @@ static int lp_gpio_runtime_resume(struct device *dev) static int lp_gpio_resume(struct device *dev) { struct lp_gpio *lg = dev_get_drvdata(dev); - unsigned long reg; + void __iomem *reg; int i; /* on some hardware suspend clears input sensing, re-enable it here */ for (i = 0; i < lg->chip.ngpio; i++) { if (gpiochip_is_requested(&lg->chip, i) != NULL) { reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); - outl(inl(reg) & ~GPINDIS_BIT, reg); + iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); } } return 0; From c35f463a966221f3d6c6bc48fbea27a8d68aafc3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 26 Sep 2018 17:50:27 +0300 Subject: [PATCH 35/99] pinctrl: lynxpoint: Convert unsigned to unsigned int Simple type conversion with no functional change implied. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 4ed2d4daea19..3c8241ed8bc2 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -82,7 +82,7 @@ struct lp_gpio { * LP94_CONFIG2 (gpio 94) ... */ -static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned offset, +static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, int reg) { struct lp_gpio *lg = gpiochip_get_data(chip); @@ -98,7 +98,7 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned offset, return lg->regs + reg + reg_offset; } -static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) +static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); @@ -131,7 +131,7 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) return 0; } -static void lp_gpio_free(struct gpio_chip *chip, unsigned offset) +static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); @@ -142,7 +142,7 @@ static void lp_gpio_free(struct gpio_chip *chip, unsigned offset) pm_runtime_put(lg->dev); } -static int lp_irq_type(struct irq_data *d, unsigned type) +static int lp_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct lp_gpio *lg = gpiochip_get_data(gc); @@ -185,13 +185,13 @@ static int lp_irq_type(struct irq_data *d, unsigned type) return 0; } -static int lp_gpio_get(struct gpio_chip *chip, unsigned offset) +static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) { void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); return !!(ioread32(reg) & IN_LVL_BIT); } -static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); @@ -207,7 +207,7 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) raw_spin_unlock_irqrestore(&lg->lock, flags); } -static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); @@ -220,8 +220,8 @@ static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) return 0; } -static int lp_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) +static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, + int value) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); @@ -255,7 +255,7 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) pending = ioread32(reg) & ioread32(ena); for_each_set_bit(pin, &pending, 32) { - unsigned irq; + unsigned int irq; /* Clear before handling so we don't lose an edge */ iowrite32(BIT(pin), reg); @@ -315,7 +315,7 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *reg; - unsigned base; + unsigned int base; for (base = 0; base < lg->chip.ngpio; base += 32) { /* disable gpio pin interrupts */ @@ -390,7 +390,7 @@ static int lp_gpio_probe(struct platform_device *pdev) GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned)irq_rc->start; + girq->parents[0] = (unsigned int)irq_rc->start; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } From 21a06495d0e757b8a52774ce62e9cfdf07838971 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 19:27:34 +0200 Subject: [PATCH 36/99] pinctrl: lynxpoint: Extract lp_gpio_acpi_use() for future use We may need this function for other features in the pin control driver. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 3c8241ed8bc2..d40360728140 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -98,18 +98,28 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, return lg->regs + reg + reg_offset; } +static bool lp_gpio_acpi_use(struct lp_gpio *lg, unsigned int pin) +{ + void __iomem *acpi_use; + + acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); + if (!acpi_use) + return true; + + return !(ioread32(acpi_use) & BIT(pin % 32)); +} + static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct lp_gpio *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); - void __iomem *acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); u32 value; pm_runtime_get(lg->dev); /* should we put if failed */ /* Fail if BIOS reserved pin for ACPI use */ - if (!(ioread32(acpi_use) & BIT(offset % 32))) { + if (lp_gpio_acpi_use(lg, offset)) { dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset); return -EBUSY; } From d0f2df4070b59662b7d03bbcb22dccbfbd717158 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 25 Oct 2019 20:53:58 +0300 Subject: [PATCH 37/99] pinctrl: lynxpoint: Move ->remove closer to ->probe() Consolidate ->remove and ->probe() callbacks for better maintenance. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index d40360728140..83b5b2590778 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -416,6 +416,12 @@ static int lp_gpio_probe(struct platform_device *pdev) return 0; } +static int lp_gpio_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + return 0; +} + static int lp_gpio_runtime_suspend(struct device *dev) { return 0; @@ -455,12 +461,6 @@ static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { }; MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); -static int lp_gpio_remove(struct platform_device *pdev) -{ - pm_runtime_disable(&pdev->dev); - return 0; -} - static struct platform_driver lp_gpio_driver = { .probe = lp_gpio_probe, .remove = lp_gpio_remove, From 095f2a67cdaf0aba6868504e963dda2e4d09a3f8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 18 Nov 2019 20:08:57 +0200 Subject: [PATCH 38/99] pinctrl: lynxpoint: Move lp_irq_type() closer to IRQ related routines Consolidate IRQ routines for better maintenance. While here, rename lp_irq_type() to lp_irq_set_type() to be in align with a callback name. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 88 +++++++++++------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 83b5b2590778..19e8f8f1f7aa 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -152,49 +152,6 @@ static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) pm_runtime_put(lg->dev); } -static int lp_irq_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct lp_gpio *lg = gpiochip_get_data(gc); - u32 hwirq = irqd_to_hwirq(d); - void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); - unsigned long flags; - u32 value; - - if (hwirq >= lg->chip.ngpio) - return -EINVAL; - - raw_spin_lock_irqsave(&lg->lock, flags); - value = ioread32(reg); - - /* set both TRIG_SEL and INV bits to 0 for rising edge */ - if (type & IRQ_TYPE_EDGE_RISING) - value &= ~(TRIG_SEL_BIT | INT_INV_BIT); - - /* TRIG_SEL bit 0, INV bit 1 for falling edge */ - if (type & IRQ_TYPE_EDGE_FALLING) - value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; - - /* TRIG_SEL bit 1, INV bit 0 for level low */ - if (type & IRQ_TYPE_LEVEL_LOW) - value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; - - /* TRIG_SEL bit 1, INV bit 1 for level high */ - if (type & IRQ_TYPE_LEVEL_HIGH) - value |= TRIG_SEL_BIT | INT_INV_BIT; - - iowrite32(value, reg); - - if (type & IRQ_TYPE_EDGE_BOTH) - irq_set_handler_locked(d, handle_edge_irq); - else if (type & IRQ_TYPE_LEVEL_MASK) - irq_set_handler_locked(d, handle_level_irq); - - raw_spin_unlock_irqrestore(&lg->lock, flags); - - return 0; -} - static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) { void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); @@ -311,13 +268,56 @@ static void lp_irq_disable(struct irq_data *d) raw_spin_unlock_irqrestore(&lg->lock, flags); } +static int lp_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct lp_gpio *lg = gpiochip_get_data(gc); + u32 hwirq = irqd_to_hwirq(d); + void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); + unsigned long flags; + u32 value; + + if (hwirq >= lg->chip.ngpio) + return -EINVAL; + + raw_spin_lock_irqsave(&lg->lock, flags); + value = ioread32(reg); + + /* set both TRIG_SEL and INV bits to 0 for rising edge */ + if (type & IRQ_TYPE_EDGE_RISING) + value &= ~(TRIG_SEL_BIT | INT_INV_BIT); + + /* TRIG_SEL bit 0, INV bit 1 for falling edge */ + if (type & IRQ_TYPE_EDGE_FALLING) + value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; + + /* TRIG_SEL bit 1, INV bit 0 for level low */ + if (type & IRQ_TYPE_LEVEL_LOW) + value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; + + /* TRIG_SEL bit 1, INV bit 1 for level high */ + if (type & IRQ_TYPE_LEVEL_HIGH) + value |= TRIG_SEL_BIT | INT_INV_BIT; + + iowrite32(value, reg); + + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_unlock_irqrestore(&lg->lock, flags); + + return 0; +} + static struct irq_chip lp_irqchip = { .name = "LP-GPIO", .irq_mask = lp_irq_mask, .irq_unmask = lp_irq_unmask, .irq_enable = lp_irq_enable, .irq_disable = lp_irq_disable, - .irq_set_type = lp_irq_type, + .irq_set_type = lp_irq_set_type, .flags = IRQCHIP_SKIP_SET_WAKE, }; From 540bff18daf4aa3d67004e8bb02a0ea5b3818451 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 19:28:14 +0200 Subject: [PATCH 39/99] pinctrl: lynxpoint: Move ownership check to IRQ chip There is nothing wrong with requesting pin that owned by ACPI. The only difference is how interrupt status will be reflected. It means that in ACPI mode we may not use pin as GPIO-backed IRQ. Taking above into consideration, move the check from GPIO to IRQ chip callback. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 19e8f8f1f7aa..ddb201e5d78f 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -118,12 +118,6 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) pm_runtime_get(lg->dev); /* should we put if failed */ - /* Fail if BIOS reserved pin for ACPI use */ - if (lp_gpio_acpi_use(lg, offset)) { - dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset); - return -EBUSY; - } - /* * Reconfigure pin to GPIO mode if needed and issue a warning, * since we expect firmware to configure it properly. @@ -280,6 +274,12 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type) if (hwirq >= lg->chip.ngpio) return -EINVAL; + /* Fail if BIOS reserved pin for ACPI use */ + if (lp_gpio_acpi_use(lg, hwirq)) { + dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); + return -EBUSY; + } + raw_spin_lock_irqsave(&lg->lock, flags); value = ioread32(reg); From 5931e6edfdd01c97b4cf8354e68f74df97580e49 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 22 Nov 2019 16:50:05 +0200 Subject: [PATCH 40/99] pinctrl: lynxpoint: Implement ->irq_ack() callback Instead of playing tricks with registers in the interrupt handler, utilize the IRQ chip core for ACKing interrupts properly. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index ddb201e5d78f..3b0dfe9a51ba 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -218,9 +218,6 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(pin, &pending, 32) { unsigned int irq; - /* Clear before handling so we don't lose an edge */ - iowrite32(BIT(pin), reg); - irq = irq_find_mapping(lg->chip.irq.domain, base + pin); generic_handle_irq(irq); } @@ -228,6 +225,19 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) chip->irq_eoi(data); } +static void lp_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct lp_gpio *lg = gpiochip_get_data(gc); + u32 hwirq = irqd_to_hwirq(d); + void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); + unsigned long flags; + + raw_spin_lock_irqsave(&lg->lock, flags); + iowrite32(BIT(hwirq % 32), reg); + raw_spin_unlock_irqrestore(&lg->lock, flags); +} + static void lp_irq_unmask(struct irq_data *d) { } @@ -313,6 +323,7 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type) static struct irq_chip lp_irqchip = { .name = "LP-GPIO", + .irq_ack = lp_irq_ack, .irq_mask = lp_irq_mask, .irq_unmask = lp_irq_unmask, .irq_enable = lp_irq_enable, From 54d371cf73d9029a6adade3ec9423653d7790ef0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 19 Nov 2019 17:36:48 +0200 Subject: [PATCH 41/99] pinctrl: lynxpoint: Implement intel_gpio_get_direction callback Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 3b0dfe9a51ba..3c1b71204bbe 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -197,6 +197,16 @@ static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, return 0; } +static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); + + if (ioread32(reg) & DIR_BIT) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + static void lp_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); @@ -391,6 +401,7 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->direction_output = lp_gpio_direction_output; gc->get = lp_gpio_get; gc->set = lp_gpio_set; + gc->get_direction = lp_gpio_get_direction; gc->base = -1; gc->ngpio = LP_NUM_GPIO; gc->can_sleep = false; From cecddda7ca4e7e94256e3be972bd7f14960bd64c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 25 Oct 2019 21:26:21 +0300 Subject: [PATCH 42/99] pinctrl: lynxpoint: Add pin control data structures In order to implement pin control for Intel Lynxpoint, we need data structures in which to store and pass along pin, community and SoC data information. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 126 +++++++++++++++++++++- 1 file changed, 124 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 3c1b71204bbe..ea46bd64226d 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -18,6 +18,128 @@ #include #include +#include +#include +#include +#include + +#include "pinctrl-intel.h" + +#define COMMUNITY(p, n) \ + { \ + .pin_base = (p), \ + .npins = (n), \ + } + +static const struct pinctrl_pin_desc lptlp_pins[] = { + PINCTRL_PIN(0, "GP0_UART1_RXD"), + PINCTRL_PIN(1, "GP1_UART1_TXD"), + PINCTRL_PIN(2, "GP2_UART1_RTSB"), + PINCTRL_PIN(3, "GP3_UART1_CTSB"), + PINCTRL_PIN(4, "GP4_I2C0_SDA"), + PINCTRL_PIN(5, "GP5_I2C0_SCL"), + PINCTRL_PIN(6, "GP6_I2C1_SDA"), + PINCTRL_PIN(7, "GP7_I2C1_SCL"), + PINCTRL_PIN(8, "GP8"), + PINCTRL_PIN(9, "GP9"), + PINCTRL_PIN(10, "GP10"), + PINCTRL_PIN(11, "GP11_SMBALERTB"), + PINCTRL_PIN(12, "GP12_LANPHYPC"), + PINCTRL_PIN(13, "GP13"), + PINCTRL_PIN(14, "GP14"), + PINCTRL_PIN(15, "GP15"), + PINCTRL_PIN(16, "GP16_MGPIO9"), + PINCTRL_PIN(17, "GP17_MGPIO10"), + PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), + PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), + PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), + PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), + PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), + PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), + PINCTRL_PIN(24, "GP24_MGPIO0"), + PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), + PINCTRL_PIN(26, "GP26_MGPIO5"), + PINCTRL_PIN(27, "GP27_MGPIO6"), + PINCTRL_PIN(28, "GP28_MGPIO7"), + PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), + PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), + PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), + PINCTRL_PIN(32, "GP32_CLKRUNB"), + PINCTRL_PIN(33, "GP33_DEVSLP0"), + PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), + PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), + PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), + PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), + PINCTRL_PIN(38, "GP38_DEVSLP1"), + PINCTRL_PIN(39, "GP39_DEVSLP2"), + PINCTRL_PIN(40, "GP40_OC0B"), + PINCTRL_PIN(41, "GP41_OC1B"), + PINCTRL_PIN(42, "GP42_OC2B"), + PINCTRL_PIN(43, "GP43_OC3B"), + PINCTRL_PIN(44, "GP44"), + PINCTRL_PIN(45, "GP45_TMS2"), + PINCTRL_PIN(46, "GP46_TDO2"), + PINCTRL_PIN(47, "GP47"), + PINCTRL_PIN(48, "GP48"), + PINCTRL_PIN(49, "GP49"), + PINCTRL_PIN(50, "GP50"), + PINCTRL_PIN(51, "GP51_GSXDOUT"), + PINCTRL_PIN(52, "GP52_GSXSLOAD"), + PINCTRL_PIN(53, "GP53_GSXDIN"), + PINCTRL_PIN(54, "GP54_GSXSRESETB"), + PINCTRL_PIN(55, "GP55_GSXCLK"), + PINCTRL_PIN(56, "GP56"), + PINCTRL_PIN(57, "GP57"), + PINCTRL_PIN(58, "GP58"), + PINCTRL_PIN(59, "GP59"), + PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), + PINCTRL_PIN(61, "GP61_SUS_STATB"), + PINCTRL_PIN(62, "GP62_SUSCLK"), + PINCTRL_PIN(63, "GP63_SLP_S5B"), + PINCTRL_PIN(64, "GP64_SDIO_CLK"), + PINCTRL_PIN(65, "GP65_SDIO_CMD"), + PINCTRL_PIN(66, "GP66_SDIO_D0"), + PINCTRL_PIN(67, "GP67_SDIO_D1"), + PINCTRL_PIN(68, "GP68_SDIO_D2"), + PINCTRL_PIN(69, "GP69_SDIO_D3"), + PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), + PINCTRL_PIN(71, "GP71_MPHYPC"), + PINCTRL_PIN(72, "GP72_BATLOWB"), + PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), + PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), + PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), + PINCTRL_PIN(76, "GP76_BMBUSYB"), + PINCTRL_PIN(77, "GP77_PIRQAB"), + PINCTRL_PIN(78, "GP78_PIRQBB"), + PINCTRL_PIN(79, "GP79_PIRQCB"), + PINCTRL_PIN(80, "GP80_PIRQDB"), + PINCTRL_PIN(81, "GP81_SPKR"), + PINCTRL_PIN(82, "GP82_RCINB"), + PINCTRL_PIN(83, "GP83_GSPI0_CSB"), + PINCTRL_PIN(84, "GP84_GSPI0_CLK"), + PINCTRL_PIN(85, "GP85_GSPI0_MISO"), + PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), + PINCTRL_PIN(87, "GP87_GSPI1_CSB"), + PINCTRL_PIN(88, "GP88_GSPI1_CLK"), + PINCTRL_PIN(89, "GP89_GSPI1_MISO"), + PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), + PINCTRL_PIN(91, "GP91_UART0_RXD"), + PINCTRL_PIN(92, "GP92_UART0_TXD"), + PINCTRL_PIN(93, "GP93_UART0_RTSB"), + PINCTRL_PIN(94, "GP94_UART0_CTSB"), +}; + +static const struct intel_community lptlp_communities[] = { + COMMUNITY(0, 95), +}; + +static const struct intel_pinctrl_soc_data lptlp_soc_data = { + .pins = lptlp_pins, + .npins = ARRAY_SIZE(lptlp_pins), + .communities = lptlp_communities, + .ncommunities = ARRAY_SIZE(lptlp_communities), +}; + /* LynxPoint chipset has support for 95 GPIO pins */ #define LP_NUM_GPIO 95 @@ -477,8 +599,8 @@ static const struct dev_pm_ops lp_gpio_pm_ops = { }; static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { - { "INT33C7", 0 }, - { "INT3437", 0 }, + { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, + { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); From 18213ad4187d44f2b58e96529f169c3ae4898b51 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 20:49:44 +0200 Subject: [PATCH 43/99] pinctrl: lynxpoint: Reuse struct intel_pinctrl in the driver We may use now available struct intel_pinctrl in the driver. No functional change implied. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 84 ++++++++++++++++------- 1 file changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index ea46bd64226d..5a8c77c8306b 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -168,13 +168,6 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = { #define GPINDIS_BIT BIT(2) /* disable input sensing */ #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */ -struct lp_gpio { - struct gpio_chip chip; - struct device *dev; - raw_spinlock_t lock; - void __iomem *regs; -}; - /* * Lynxpoint gpios are controlled through both bitmapped registers and * per gpio specific registers. The bitmapped registers are in chunks of @@ -204,12 +197,34 @@ struct lp_gpio { * LP94_CONFIG2 (gpio 94) ... */ +static struct intel_community *lp_get_community(struct intel_pinctrl *lg, + unsigned int pin) +{ + struct intel_community *comm; + int i; + + for (i = 0; i < lg->ncommunities; i++) { + comm = &lg->communities[i]; + if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) + return comm; + } + + return NULL; +} + static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, int reg) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); + struct intel_community *comm; int reg_offset; + comm = lp_get_community(lg, offset); + if (!comm) + return NULL; + + offset -= comm->pin_base; + if (reg == LP_CONFIG1 || reg == LP_CONFIG2) /* per gpio specific config registers */ reg_offset = offset * 8; @@ -217,10 +232,10 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, /* bitmapped registers */ reg_offset = (offset / 32) * 4; - return lg->regs + reg + reg_offset; + return comm->regs + reg_offset + reg; } -static bool lp_gpio_acpi_use(struct lp_gpio *lg, unsigned int pin) +static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) { void __iomem *acpi_use; @@ -233,7 +248,7 @@ static bool lp_gpio_acpi_use(struct lp_gpio *lg, unsigned int pin) static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); u32 value; @@ -259,7 +274,7 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); /* disable input sensing */ @@ -276,7 +291,7 @@ static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; @@ -292,7 +307,7 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; @@ -306,7 +321,7 @@ static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); unsigned long flags; @@ -333,7 +348,7 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct lp_gpio *lg = gpiochip_get_data(gc); + struct intel_pinctrl *lg = gpiochip_get_data(gc); struct irq_chip *chip = irq_data_get_irq_chip(data); void __iomem *reg, *ena; unsigned long pending; @@ -360,7 +375,7 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) static void lp_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct lp_gpio *lg = gpiochip_get_data(gc); + struct intel_pinctrl *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); unsigned long flags; @@ -381,7 +396,7 @@ static void lp_irq_mask(struct irq_data *d) static void lp_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct lp_gpio *lg = gpiochip_get_data(gc); + struct intel_pinctrl *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; @@ -394,7 +409,7 @@ static void lp_irq_enable(struct irq_data *d) static void lp_irq_disable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct lp_gpio *lg = gpiochip_get_data(gc); + struct intel_pinctrl *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; @@ -407,7 +422,7 @@ static void lp_irq_disable(struct irq_data *d) static int lp_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct lp_gpio *lg = gpiochip_get_data(gc); + struct intel_pinctrl *lg = gpiochip_get_data(gc); u32 hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); unsigned long flags; @@ -466,7 +481,7 @@ static struct irq_chip lp_irqchip = { static int lp_gpio_irq_init_hw(struct gpio_chip *chip) { - struct lp_gpio *lg = gpiochip_get_data(chip); + struct intel_pinctrl *lg = gpiochip_get_data(chip); void __iomem *reg; unsigned int base; @@ -484,18 +499,32 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip) static int lp_gpio_probe(struct platform_device *pdev) { - struct lp_gpio *lg; + const struct intel_pinctrl_soc_data *soc; + struct intel_pinctrl *lg; struct gpio_chip *gc; struct resource *io_rc, *irq_rc; struct device *dev = &pdev->dev; void __iomem *regs; + unsigned int i; int ret; + soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); + if (!soc) + return -ENODEV; + lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); if (!lg) return -ENOMEM; lg->dev = dev; + lg->soc = soc; + + lg->ncommunities = lg->soc->ncommunities; + lg->communities = devm_kcalloc(dev, lg->ncommunities, + sizeof(*lg->communities), GFP_KERNEL); + if (!lg->communities) + return -ENOMEM; + platform_set_drvdata(pdev, lg); io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); @@ -510,7 +539,14 @@ static int lp_gpio_probe(struct platform_device *pdev) return -EBUSY; } - lg->regs = regs; + for (i = 0; i < lg->soc->ncommunities; i++) { + struct intel_community *comm = &lg->communities[i]; + + *comm = lg->soc->communities[i]; + + comm->regs = regs; + comm->pad_regs = regs + 0x100; + } raw_spin_lock_init(&lg->lock); @@ -578,7 +614,7 @@ static int lp_gpio_runtime_resume(struct device *dev) static int lp_gpio_resume(struct device *dev) { - struct lp_gpio *lg = dev_get_drvdata(dev); + struct intel_pinctrl *lg = dev_get_drvdata(dev); void __iomem *reg; int i; From 7f32d37009974c52323335cf8d118384fbce3572 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 20 Nov 2019 21:31:11 +0200 Subject: [PATCH 44/99] pinctrl: lynxpoint: Add pin control operations Add implementation for: - pin control, group information retrieval: count, name and pins - pin muxing: - function information (count, name and groups) - mux setting - GPIO control (enable, disable, set direction) - pin configuration: - pull disable, up and down - any other option is treated as not supported. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 315 +++++++++++++++++++++- 1 file changed, 314 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 5a8c77c8306b..c209deff9efb 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -146,6 +146,7 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = { /* Bitmapped register offsets */ #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ +#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ #define LP_INT_STAT 0x80 #define LP_INT_ENABLE 0x90 @@ -166,7 +167,10 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = { /* LP_CONFIG2 reg bits */ #define GPINDIS_BIT BIT(2) /* disable input sensing */ -#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */ +#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ +#define GPIWP_NONE 0 /* none */ +#define GPIWP_DOWN 1 /* weak pull down */ +#define GPIWP_UP 2 /* weak pull up */ /* * Lynxpoint gpios are controlled through both bitmapped registers and @@ -195,6 +199,8 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = { * ... * LP94_CONFIG1 (gpio 94) ... * LP94_CONFIG2 (gpio 94) ... + * + * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. */ static struct intel_community *lp_get_community(struct intel_pinctrl *lg, @@ -246,6 +252,308 @@ static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) return !(ioread32(acpi_use) & BIT(pin % 32)); } +static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) +{ + void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); + u32 value; + + value = ioread32(ioxapic_use); + + if (offset >= 8 && offset <= 10) + return !!(value & BIT(offset - 8 + 0)); + if (offset >= 13 && offset <= 14) + return !!(value & BIT(offset - 13 + 3)); + if (offset >= 45 && offset <= 55) + return !!(value & BIT(offset - 45 + 5)); + + return false; +} + +static int lp_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + + return lg->soc->ngroups; +} + +static const char *lp_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + + return lg->soc->groups[selector].name; +} + +static int lp_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + + *pins = lg->soc->groups[selector].pins; + *num_pins = lg->soc->groups[selector].npins; + + return 0; +} + +static const struct pinctrl_ops lptlp_pinctrl_ops = { + .get_groups_count = lp_get_groups_count, + .get_group_name = lp_get_group_name, + .get_group_pins = lp_get_group_pins, +}; + +static int lp_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + + return lg->soc->nfunctions; +} + +static const char *lp_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + + return lg->soc->functions[selector].name; +} + +static int lp_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int *num_groups) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + + *groups = lg->soc->functions[selector].groups; + *num_groups = lg->soc->functions[selector].ngroups; + + return 0; +} + +static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + const struct intel_pingroup *grp = &lg->soc->groups[group]; + unsigned long flags; + int i; + + raw_spin_lock_irqsave(&lg->lock, flags); + + /* Now enable the mux setting for each pin in the group */ + for (i = 0; i < grp->npins; i++) { + void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1); + u32 value; + + value = ioread32(reg); + + value &= ~USE_SEL_MASK; + if (grp->modes) + value |= grp->modes[i]; + else + value |= grp->mode; + + iowrite32(value, reg); + } + + raw_spin_unlock_irqrestore(&lg->lock, flags); + + return 0; +} + +static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); + void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); + unsigned long flags; + u32 value; + + pm_runtime_get(lg->dev); + + raw_spin_lock_irqsave(&lg->lock, flags); + + /* + * Reconfigure pin to GPIO mode if needed and issue a warning, + * since we expect firmware to configure it properly. + */ + value = ioread32(reg); + if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { + iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); + dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); + } + + /* Enable input sensing */ + iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); + + raw_spin_unlock_irqrestore(&lg->lock, flags); + + return 0; +} + +static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); + unsigned long flags; + + raw_spin_lock_irqsave(&lg->lock, flags); + + /* Disable input sensing */ + iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); + + raw_spin_unlock_irqrestore(&lg->lock, flags); + + pm_runtime_put(lg->dev); +} + +static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&lg->lock, flags); + + value = ioread32(reg); + value &= ~DIR_BIT; + if (input) { + value |= DIR_BIT; + } else { + /* + * Before making any direction modifications, do a check if GPIO + * is set for direct IRQ. On Lynxpoint, setting GPIO to output + * does not make sense, so let's at least warn the caller before + * they shoot themselves in the foot. + */ + WARN(lp_gpio_ioxapic_use(&lg->chip, pin), + "Potential Error: Setting GPIO to output with IOxAPIC redirection"); + } + iowrite32(value, reg); + + raw_spin_unlock_irqrestore(&lg->lock, flags); + + return 0; +} + +static const struct pinmux_ops lptlp_pinmux_ops = { + .get_functions_count = lp_get_functions_count, + .get_function_name = lp_get_function_name, + .get_function_groups = lp_get_function_groups, + .set_mux = lp_pinmux_set_mux, + .gpio_request_enable = lp_gpio_request_enable, + .gpio_disable_free = lp_gpio_disable_free, + .gpio_set_direction = lp_gpio_set_direction, +}; + +static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + u32 value, pull; + u16 arg = 0; + + raw_spin_lock_irqsave(&lg->lock, flags); + value = ioread32(conf2); + raw_spin_unlock_irqrestore(&lg->lock, flags); + + pull = value & GPIWP_MASK; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pull != GPIWP_DOWN) + return -EINVAL; + + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull != GPIWP_UP) + return -EINVAL; + + arg = 1; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); + enum pin_config_param param; + unsigned long flags; + int i, ret = 0; + u32 value; + + raw_spin_lock_irqsave(&lg->lock, flags); + + value = ioread32(conf2); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + value &= ~GPIWP_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value &= ~GPIWP_MASK; + value |= GPIWP_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + value &= ~GPIWP_MASK; + value |= GPIWP_UP; + break; + default: + ret = -ENOTSUPP; + } + + if (ret) + break; + } + + if (!ret) + iowrite32(value, conf2); + + raw_spin_unlock_irqrestore(&lg->lock, flags); + + return ret; +} + +static const struct pinconf_ops lptlp_pinconf_ops = { + .is_generic = true, + .pin_config_get = lp_pin_config_get, + .pin_config_set = lp_pin_config_set, +}; + +static const struct pinctrl_desc lptlp_pinctrl_desc = { + .pctlops = &lptlp_pinctrl_ops, + .pmxops = &lptlp_pinmux_ops, + .confops = &lptlp_pinconf_ops, + .owner = THIS_MODULE, +}; + static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct intel_pinctrl *lg = gpiochip_get_data(chip); @@ -525,6 +833,11 @@ static int lp_gpio_probe(struct platform_device *pdev) if (!lg->communities) return -ENOMEM; + lg->pctldesc = lptlp_pinctrl_desc; + lg->pctldesc.name = dev_name(dev); + lg->pctldesc.pins = lg->soc->pins; + lg->pctldesc.npins = lg->soc->npins; + platform_set_drvdata(pdev, lg); io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); From 03d9eca7d40608197bb20c584a6da97b3399559b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 20:14:03 +0200 Subject: [PATCH 45/99] pinctrl: lynxpoint: Implement ->pin_dbg_show() The introduced callback ->pin_dbg_show() is useful for debugging. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index c209deff9efb..bfdd283d2c20 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -297,10 +297,33 @@ static int lp_get_group_pins(struct pinctrl_dev *pctldev, return 0; } +static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int pin) +{ + struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); + void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); + void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); + u32 value, mode; + + value = ioread32(reg); + + mode = value & USE_SEL_MASK; + if (mode == USE_SEL_GPIO) + seq_puts(s, "GPIO "); + else + seq_printf(s, "mode %d ", mode); + + seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); + + if (lp_gpio_acpi_use(lg, pin)) + seq_puts(s, " [ACPI]"); +} + static const struct pinctrl_ops lptlp_pinctrl_ops = { .get_groups_count = lp_get_groups_count, .get_group_name = lp_get_group_name, .get_group_pins = lp_get_group_pins, + .pin_dbg_show = lp_pin_dbg_show, }; static int lp_get_functions_count(struct pinctrl_dev *pctldev) From 3683509c3910cb377913dcd430447ad48f676b31 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 4 Nov 2019 19:07:30 +0200 Subject: [PATCH 46/99] pinctrl: lynxpoint: Add GPIO <-> pin mapping ranges via callback When IRQ chip is instantiated via GPIO library flow, the few functions, in particular the ACPI event registration mechanism, on some of ACPI based platforms expect that the pin ranges are initialized to that point. Add GPIO <-> pin mapping ranges via callback in the GPIO library flow. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index bfdd283d2c20..795a9c7054ca 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -828,6 +828,19 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip) return 0; } +static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct intel_pinctrl *lg = gpiochip_get_data(chip); + struct device *dev = lg->dev; + int ret; + + ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); + if (ret) + dev_err(dev, "failed to add GPIO pin range\n"); + + return ret; +} + static int lp_gpio_probe(struct platform_device *pdev) { const struct intel_pinctrl_soc_data *soc; @@ -899,6 +912,7 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->base = -1; gc->ngpio = LP_NUM_GPIO; gc->can_sleep = false; + gc->add_pin_ranges = lp_gpio_add_pin_ranges; gc->parent = dev; /* set up interrupts */ From 64e14e90646cafa9940cead9f7ba336c55671bf9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 19:30:57 +0200 Subject: [PATCH 47/99] pinctrl: lynxpoint: Switch to pin control API When all preparations are done, we may switch to pin control API. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 3 + drivers/pinctrl/intel/pinctrl-lynxpoint.c | 67 ++++------------------- 2 files changed, 13 insertions(+), 57 deletions(-) diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index c2e6bc9e3e04..ee440ec4c94c 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -34,6 +34,9 @@ config PINCTRL_CHERRYVIEW config PINCTRL_LYNXPOINT tristate "Intel Lynxpoint pinctrl and GPIO driver" depends on ACPI + select PINMUX + select PINCONF + select GENERIC_PINCONF select GPIOLIB select GPIOLIB_IRQCHIP help diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 795a9c7054ca..774b226f3a4d 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -577,43 +577,6 @@ static const struct pinctrl_desc lptlp_pinctrl_desc = { .owner = THIS_MODULE, }; -static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) -{ - struct intel_pinctrl *lg = gpiochip_get_data(chip); - void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); - void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); - u32 value; - - pm_runtime_get(lg->dev); /* should we put if failed */ - - /* - * Reconfigure pin to GPIO mode if needed and issue a warning, - * since we expect firmware to configure it properly. - */ - value = ioread32(reg); - if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { - iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); - dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); - } - - /* enable input sensing */ - iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); - - - return 0; -} - -static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) -{ - struct intel_pinctrl *lg = gpiochip_get_data(chip); - void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); - - /* disable input sensing */ - iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); - - pm_runtime_put(lg->dev); -} - static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) { void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); @@ -638,31 +601,15 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { - struct intel_pinctrl *lg = gpiochip_get_data(chip); - void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); - unsigned long flags; - - raw_spin_lock_irqsave(&lg->lock, flags); - iowrite32(ioread32(reg) | DIR_BIT, reg); - raw_spin_unlock_irqrestore(&lg->lock, flags); - - return 0; + return pinctrl_gpio_direction_input(chip->base + offset); } static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - struct intel_pinctrl *lg = gpiochip_get_data(chip); - void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); - unsigned long flags; - lp_gpio_set(chip, offset, value); - raw_spin_lock_irqsave(&lg->lock, flags); - iowrite32(ioread32(reg) & ~DIR_BIT, reg); - raw_spin_unlock_irqrestore(&lg->lock, flags); - - return 0; + return pinctrl_gpio_direction_output(chip->base + offset); } static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) @@ -874,6 +821,12 @@ static int lp_gpio_probe(struct platform_device *pdev) lg->pctldesc.pins = lg->soc->pins; lg->pctldesc.npins = lg->soc->npins; + lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); + if (IS_ERR(lg->pctldev)) { + dev_err(dev, "failed to register pinctrl driver\n"); + return PTR_ERR(lg->pctldev); + } + platform_set_drvdata(pdev, lg); io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); @@ -902,8 +855,8 @@ static int lp_gpio_probe(struct platform_device *pdev) gc = &lg->chip; gc->label = dev_name(dev); gc->owner = THIS_MODULE; - gc->request = lp_gpio_request; - gc->free = lp_gpio_free; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; gc->direction_input = lp_gpio_direction_input; gc->direction_output = lp_gpio_direction_output; gc->get = lp_gpio_get; From 3a67fe38e76a590d2c8ce4731cd64fbd477e5f79 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 25 Nov 2019 17:45:45 +0200 Subject: [PATCH 48/99] pinctrl: lynxpoint: Update summary in the driver Reflect in the driver that it is now a pin control one. While here, update copyright years and authors. Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 774b226f3a4d..e928742c7181 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 /* - * GPIO controller driver for Intel Lynxpoint PCH chipset> - * Copyright (c) 2012, Intel Corporation. + * Intel Lynxpoint PCH pinctrl/GPIO driver * - * Author: Mathias Nyman + * Copyright (c) 2012, 2019, Intel Corporation + * Authors: Mathias Nyman + * Andy Shevchenko */ #include @@ -968,6 +969,7 @@ subsys_initcall(lp_gpio_init); module_exit(lp_gpio_exit); MODULE_AUTHOR("Mathias Nyman (Intel)"); -MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint"); +MODULE_AUTHOR("Andy Shevchenko (Intel)"); +MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:lp_gpio"); From 225a2ec19aac426ef29f0e4accfc890c87d38bdc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 13 Dec 2019 08:24:33 +0100 Subject: [PATCH 49/99] pinctrl: samsung: Fix missing OF and GPIOLIB dependency on S3C24xx and S3C64xx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All Samsung pinctrl drivers select common part - PINCTRL_SAMSUNG which uses both OF and GPIOLIB inside. However only Exynos drivers depend on these, therefore after enabling COMPILE_TEST, on x86_64 build of S3C64xx driver failed: drivers/pinctrl/samsung/pinctrl-samsung.c: In function ‘samsung_gpiolib_register’: drivers/pinctrl/samsung/pinctrl-samsung.c:969:5: error: ‘struct gpio_chip’ has no member named ‘of_node’ gc->of_node = bank->of_node; ^ Rework the dependencies so all Samsung drivers and common PINCTRL_SAMSUNG part depend on OF_GPIO (which is default yes if GPIOLIB and OF are enabled). Reported-by: Chen Zhou Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index 779c0e9eca3f..dfd805e76862 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -4,12 +4,13 @@ # config PINCTRL_SAMSUNG bool + depends on OF_GPIO select PINMUX select PINCONF config PINCTRL_EXYNOS bool "Pinctrl common driver part for Samsung Exynos SoCs" - depends on OF && GPIOLIB + depends on OF_GPIO depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST select PINCTRL_SAMSUNG select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210) @@ -25,11 +26,12 @@ config PINCTRL_EXYNOS_ARM64 config PINCTRL_S3C24XX bool "Samsung S3C24XX SoC pinctrl driver" - depends on OF + depends on OF_GPIO depends on ARCH_S3C24XX || COMPILE_TEST select PINCTRL_SAMSUNG config PINCTRL_S3C64XX bool "Samsung S3C64XX SoC pinctrl driver" + depends on OF_GPIO depends on ARCH_S3C64XX || COMPILE_TEST select PINCTRL_SAMSUNG From 6ece6d15c0b0bac5b0ff7c107d1d11d3fcb9a0c7 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 30 Oct 2019 12:36:17 +0530 Subject: [PATCH 50/99] pinctrl: qcom: sc7180: Add GPIO wakeup interrupt map GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Provide the interrupt map of the GPIO to its wakeup capable interrupt parent. Signed-off-by: Maulik Shah Link: https://lore.kernel.org/r/1572419178-5750-2-git-send-email-mkshah@codeaurora.org Reviewed-by: Lina Iyer Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-sc7180.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index d6cfad7417b1..1d3a6807cf1e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -1099,6 +1099,22 @@ static const struct msm_pingroup sc7180_groups[] = { [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0), }; +static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = { + {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35}, + {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21}, + {24, 61}, {26, 52}, {28, 36}, {30, 100}, {31, 33}, {32, 81}, + {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72}, + {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17}, + {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83}, + {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93}, + {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64}, + {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39}, + {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49}, + {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104}, + {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121}, + {117, 114}, {118, 119}, +}; + static const struct msm_pinctrl_soc_data sc7180_pinctrl = { .pins = sc7180_pins, .npins = ARRAY_SIZE(sc7180_pins), @@ -1109,6 +1125,8 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { .ngpios = 120, .tiles = sc7180_tiles, .ntiles = ARRAY_SIZE(sc7180_tiles), + .wakeirq_map = sc7180_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc7180_pdc_map), }; static int sc7180_pinctrl_probe(struct platform_device *pdev) From 22440461b19e773fe75b41fc6e3388d2319ff3be Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 11 Dec 2019 05:24:24 +0000 Subject: [PATCH 51/99] dt-bindings: pinctrl: qcom: Add new qup functions for sc7180 Add new qup functions for qup02/04/11 and qup13 wherein multiple functions (for i2c and uart) share the same pin. This allows users to identify which specific qup function for the instance one needs to use for the pin. Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/0101016ef36a5c54-2907cf32-2269-4a8c-9447-b086e7c86d98-000000@us-west-2.amazonses.com Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt index b5767ee82ee6..6ffeac9801df 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt @@ -125,8 +125,9 @@ to specify in a pin configuration subnode: mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs, - qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, - qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb, + qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03, + qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, + qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, From f4a73f5e26330d1e220f2905d604de1a5a079411 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 11 Dec 2019 05:24:37 +0000 Subject: [PATCH 52/99] pinctrl: qcom: sc7180: Add new qup functions on sc7180 we have cases where multiple functions from the same qup instance share the same pin. This is true for qup02/04/11 and qup13. Add new function names to distinguish which qup function to use. The device tree files for this platform haven't landed in mainline yet, so there aren't any users upstream who should break with this change in function names, however, anyone using the devicetree files that were posted on the lists and using these specific function names will need to update their changes. Reported-by: Stephen Boyd Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/0101016ef36a9118-f2919277-effa-4cd5-adf8-bbc8016f31df-000000@us-west-2.amazonses.com Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-sc7180.c | 60 ++++++++++++++++++--------- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index 1d3a6807cf1e..1b6465a882f2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -456,14 +456,18 @@ enum sc7180_functions { msm_mux_qspi_data, msm_mux_qup00, msm_mux_qup01, - msm_mux_qup02, + msm_mux_qup02_i2c, + msm_mux_qup02_uart, msm_mux_qup03, - msm_mux_qup04, + msm_mux_qup04_i2c, + msm_mux_qup04_uart, msm_mux_qup05, msm_mux_qup10, - msm_mux_qup11, + msm_mux_qup11_i2c, + msm_mux_qup11_uart, msm_mux_qup12, - msm_mux_qup13, + msm_mux_qup13_i2c, + msm_mux_qup13_uart, msm_mux_qup14, msm_mux_qup15, msm_mux_sdc1_tb, @@ -543,7 +547,10 @@ static const char * const sdc1_tb_groups[] = { static const char * const sdc2_tb_groups[] = { "gpio5", }; -static const char * const qup11_groups[] = { +static const char * const qup11_i2c_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qup11_uart_groups[] = { "gpio6", "gpio7", }; static const char * const ddr_bist_groups[] = { @@ -593,7 +600,10 @@ static const char * const qdss_groups[] = { static const char * const pll_reset_groups[] = { "gpio14", }; -static const char * const qup02_groups[] = { +static const char * const qup02_i2c_groups[] = { + "gpio15", "gpio16", +}; +static const char * const qup02_uart_groups[] = { "gpio15", "gpio16", }; static const char * const cci_i2c_groups[] = { @@ -698,7 +708,10 @@ static const char * const wlan1_adc1_groups[] = { static const char * const atest_usb13_groups[] = { "gpio44", }; -static const char * const qup13_groups[] = { +static const char * const qup13_i2c_groups[] = { + "gpio46", "gpio47", +}; +static const char * const qup13_uart_groups[] = { "gpio46", "gpio47", }; static const char * const gcc_gp1_groups[] = { @@ -848,7 +861,10 @@ static const char * const usb_phy_groups[] = { static const char * const mss_lte_groups[] = { "gpio108", "gpio109", }; -static const char * const qup04_groups[] = { +static const char * const qup04_i2c_groups[] = { + "gpio115", "gpio116", +}; +static const char * const qup04_uart_groups[] = { "gpio115", "gpio116", }; @@ -929,14 +945,18 @@ static const struct msm_function sc7180_functions[] = { FUNCTION(qspi_data), FUNCTION(qup00), FUNCTION(qup01), - FUNCTION(qup02), + FUNCTION(qup02_i2c), + FUNCTION(qup02_uart), FUNCTION(qup03), - FUNCTION(qup04), + FUNCTION(qup04_i2c), + FUNCTION(qup04_uart), FUNCTION(qup05), FUNCTION(qup10), - FUNCTION(qup11), + FUNCTION(qup11_i2c), + FUNCTION(qup11_uart), FUNCTION(qup12), - FUNCTION(qup13), + FUNCTION(qup13_i2c), + FUNCTION(qup13_uart), FUNCTION(qup14), FUNCTION(qup15), FUNCTION(sdc1_tb), @@ -976,8 +996,8 @@ static const struct msm_pingroup sc7180_groups[] = { [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _), [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _), [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _), - [6] = PINGROUP(6, NORTH, qup11, qup11, _, _, _, _, _, _, _), - [7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup11_i2c, qup11_uart, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup11_i2c, qup11_uart, ddr_bist, _, _, _, _, _, _), [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _), [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _), [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _), @@ -985,8 +1005,8 @@ static const struct msm_pingroup sc7180_groups[] = { [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _), [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _), [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), - [15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _), - [16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _), + [15] = PINGROUP(15, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _), + [16] = PINGROUP(16, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _), [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char), [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _), [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _), @@ -1016,8 +1036,8 @@ static const struct msm_pingroup sc7180_groups[] = { [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _), [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), - [46] = PINGROUP(46, NORTH, qup13, qup13, _, _, _, _, _, _, _), - [47] = PINGROUP(47, NORTH, qup13, qup13, _, _, _, _, _, _, _), + [46] = PINGROUP(46, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _), + [47] = PINGROUP(47, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _), [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _), [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _), [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _), @@ -1085,8 +1105,8 @@ static const struct msm_pingroup sc7180_groups[] = { [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _), [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _), [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), - [115] = PINGROUP(115, WEST, qup04, qup04, _, _, _, _, _, _, _), - [116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _), + [115] = PINGROUP(115, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _), + [116] = PINGROUP(116, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _), [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _), [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _), [119] = UFS_RESET(ufs_reset, 0x7f000), From 534ad35798aff40a93acac4c6d204ff8867701aa Mon Sep 17 00:00:00 2001 From: Hamish Martin Date: Mon, 16 Dec 2019 10:05:03 +1300 Subject: [PATCH 53/99] pinctrl: iproc: Set irq handler based on trig type Rather than always using handle_simple_irq() as the gpio_irq_chip handler, set a more appropriate handler based on the IRQ trigger type requested. This is important for level triggered interrupts which need to be masked during handling. Signed-off-by: Hamish Martin Link: https://lore.kernel.org/r/20191215210503.15488-2-hamish.martin@alliedtelesis.co.nz Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 831a9318c384..aa9b5ba1bf38 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -286,6 +286,12 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, rising_or_high); + + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + raw_spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, @@ -868,7 +874,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) return -ENOMEM; girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_simple_irq; + girq->handler = handle_bad_irq; } ret = gpiochip_add_data(gc, chip); From a34cd9dfd03fa9ec380405969f1d638bc63b8d63 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 13 Nov 2019 11:16:53 +0100 Subject: [PATCH 54/99] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control R-Car Gen3 Hardware Manual Errata for Rev. 2.00 of October 24, 2019 changed the configuration bits for drive and bias control for the DU_DOTCLKIN3 pin on R-Car M3-N, to match the same pin on R-Car H3. Update the driver to reflect this. After this, the handling of drive and bias control for the various DU_DOTCLKINx pins is consistent across all of the R-Car H3, M3-W, M3-W+, and M3-N SoCs. Fixes: 86c045c2e4201e94 ("pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191113101653.28428-1-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index 8bdf33c807f6..6616f5210b9d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -5998,7 +5998,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ { PIN_TMS, 4, 2 }, /* TMS */ } }, @@ -6254,8 +6254,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ - [ 1] = SH_PFC_PIN_NONE, + [ 0] = SH_PFC_PIN_NONE, + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ [ 2] = PIN_FSCLKST, /* FSCLKST */ [ 3] = PIN_EXTALR, /* EXTALR*/ [ 4] = PIN_TRST_N, /* TRST# */ From 6d5375a31295143ef4bab7cfc352747e93dedc99 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 12 Dec 2019 08:53:01 -0500 Subject: [PATCH 55/99] pinctrl: rza1: Reduce printed messages Since this message is printed for each port, it creates a lot of output during boot and would serve better only during debugging. Signed-off-by: Chris Brandt Acked-by: Jacopo Mondi Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20191212135301.17915-1-chris.brandt@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/pinctrl-rza1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index 215db220d795..617585be6a7d 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -1229,8 +1229,8 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, pinctrl_add_gpio_range(rza1_pctl->pctl, range); - dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", - chip->label, chip->ngpio); + dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", + chip->label, chip->ngpio); return 0; } From c72bed23b9e45accdeab626cf2cb2bd08d846f3e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 16 Dec 2019 21:51:18 +0100 Subject: [PATCH 56/99] pinctrl: Allow modules to use pinctrl_[un]register_mappings Currently only the drivers/pinctrl/devicetree.c code allows registering pinctrl-mappings which may later be unregistered, all other mappings are assumed to be permanent. Non-dt platforms may also want to register pinctrl mappings from code which is build as a module, which requires being able to unregister the mapping when the module is unloaded to avoid dangling pointers. To allow unregistering the mappings the devicetree code uses 2 internal functions: pinctrl_register_map and pinctrl_unregister_map. pinctrl_register_map allows the devicetree code to tell the core to not memdup the mappings as it retains ownership of them and pinctrl_unregister_map does the unregistering, note this only works when the mappings where not memdupped. The only code relying on the memdup/shallow-copy done by pinctrl_register_mappings is arch/arm/mach-u300/core.c this commit replaces the __initdata with const, so that the shallow-copy is no longer necessary. After that we can get rid of the internal pinctrl_unregister_map function and just use pinctrl_register_mappings directly everywhere. This commit also renames pinctrl_unregister_map to pinctrl_unregister_mappings so that its naming matches its pinctrl_register_mappings counter-part and exports it. Together these 2 changes will allow non-dt platform code to register pinctrl-mappings from modules without breaking things on module unload (as they can now unregister the mapping on unload). Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20191216205122.1850923-2-hdegoede@redhat.com Signed-off-by: Linus Walleij --- arch/arm/mach-u300/core.c | 2 +- drivers/pinctrl/core.c | 43 +++++++++++++-------------------- drivers/pinctrl/core.h | 4 --- drivers/pinctrl/devicetree.c | 4 +-- include/linux/pinctrl/machine.h | 5 ++++ 5 files changed, 25 insertions(+), 33 deletions(-) diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index a79fa3b0c8ed..a1694d977ec9 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -201,7 +201,7 @@ static unsigned long pin_highz_conf[] = { }; /* Pin control settings */ -static struct pinctrl_map __initdata u300_pinmux_map[] = { +static const struct pinctrl_map u300_pinmux_map[] = { /* anonymous maps for chip power and EMIFs */ PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"), PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"), diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 2bbd8ee93507..b0eea728455d 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1376,8 +1376,15 @@ void devm_pinctrl_put(struct pinctrl *p) } EXPORT_SYMBOL_GPL(devm_pinctrl_put); -int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, - bool dup) +/** + * pinctrl_register_mappings() - register a set of pin controller mappings + * @maps: the pincontrol mappings table to register. Note the pinctrl-core + * keeps a reference to the passed in maps, so they should _not_ be + * marked with __initdata. + * @num_maps: the number of maps in the mapping table + */ +int pinctrl_register_mappings(const struct pinctrl_map *maps, + unsigned num_maps) { int i, ret; struct pinctrl_maps *maps_node; @@ -1430,17 +1437,8 @@ int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, if (!maps_node) return -ENOMEM; + maps_node->maps = maps; maps_node->num_maps = num_maps; - if (dup) { - maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, - GFP_KERNEL); - if (!maps_node->maps) { - kfree(maps_node); - return -ENOMEM; - } - } else { - maps_node->maps = maps; - } mutex_lock(&pinctrl_maps_mutex); list_add_tail(&maps_node->node, &pinctrl_maps); @@ -1448,22 +1446,14 @@ int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, return 0; } - -/** - * pinctrl_register_mappings() - register a set of pin controller mappings - * @maps: the pincontrol mappings table to register. This should probably be - * marked with __initdata so it can be discarded after boot. This - * function will perform a shallow copy for the mapping entries. - * @num_maps: the number of maps in the mapping table - */ -int pinctrl_register_mappings(const struct pinctrl_map *maps, - unsigned num_maps) -{ - return pinctrl_register_map(maps, num_maps, true); -} EXPORT_SYMBOL_GPL(pinctrl_register_mappings); -void pinctrl_unregister_map(const struct pinctrl_map *map) +/** + * pinctrl_unregister_mappings() - unregister a set of pin controller mappings + * @maps: the pincontrol mappings table passed to pinctrl_register_mappings() + * when registering the mappings. + */ +void pinctrl_unregister_mappings(const struct pinctrl_map *map) { struct pinctrl_maps *maps_node; @@ -1478,6 +1468,7 @@ void pinctrl_unregister_map(const struct pinctrl_map *map) } mutex_unlock(&pinctrl_maps_mutex); } +EXPORT_SYMBOL_GPL(pinctrl_unregister_mappings); /** * pinctrl_force_sleep() - turn a given controller device into sleep state diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 7f34167a0405..840103c40c14 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -236,10 +236,6 @@ extern struct pinctrl_gpio_range * pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev, unsigned int pin); -int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, - bool dup); -void pinctrl_unregister_map(const struct pinctrl_map *map); - extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev); extern int pinctrl_force_default(struct pinctrl_dev *pctldev); diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 674920daac26..9357f7c46cf3 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -51,7 +51,7 @@ void pinctrl_dt_free_maps(struct pinctrl *p) struct pinctrl_dt_map *dt_map, *n1; list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) { - pinctrl_unregister_map(dt_map->map); + pinctrl_unregister_mappings(dt_map->map); list_del(&dt_map->node); dt_free_map(dt_map->pctldev, dt_map->map, dt_map->num_maps); @@ -92,7 +92,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, dt_map->num_maps = num_maps; list_add_tail(&dt_map->node, &p->dt_maps); - return pinctrl_register_map(map, num_maps, false); + return pinctrl_register_mappings(map, num_maps); err_free_map: dt_free_map(pctldev, map, num_maps); diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h index ddd1b2773431..e987dc9fd2af 100644 --- a/include/linux/pinctrl/machine.h +++ b/include/linux/pinctrl/machine.h @@ -153,6 +153,7 @@ struct pinctrl_map { extern int pinctrl_register_mappings(const struct pinctrl_map *map, unsigned num_maps); +extern void pinctrl_unregister_mappings(const struct pinctrl_map *map); extern void pinctrl_provide_dummies(void); #else @@ -162,6 +163,10 @@ static inline int pinctrl_register_mappings(const struct pinctrl_map *map, return 0; } +static inline void pinctrl_unregister_mappings(const struct pinctrl_map *map) +{ +} + static inline void pinctrl_provide_dummies(void) { } From 805f635703b2562b5ddd822c62fc9124087e5dd5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Dec 2019 20:48:07 +0100 Subject: [PATCH 57/99] pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B The FN_SDSELF_B and FN_SD1_CLK_B enum IDs are used twice, which means one set of users must be wrong. Replace them by the correct enum IDs. Fixes: 87f8c988636db0d4 ("sh-pfc: Add r8a7778 pinmux support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191218194812.12741-2-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 24866a5958ae..a9875038ed9b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -2305,7 +2305,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ATAG0_A, 0, FN_REMOCON_B, 0, /* IP0_11_8 [4] */ FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, - FN_ATADIR0_A, 0, FN_SDSELF_B, 0, + FN_ATADIR0_A, 0, FN_SDSELF_A, 0, FN_PWM4_B, 0, 0, 0, 0, 0, 0, 0, /* IP0_7_5 [3] */ @@ -2349,7 +2349,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDAT0_A, 0, 0, 0, 0, 0, 0, 0, /* IP1_10_8 [3] */ - FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, + FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24, FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, /* IP1_7_5 [3] */ FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, From 2a069a92811fb35b57aaa1bfbe406afcc723f490 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Dec 2019 20:48:08 +0100 Subject: [PATCH 58/99] pinctrl: sh-pfc: sh7264: Fix Port K I/O Register 0 definition The register definition block for the Port K I/O Register is accidentally using the defines for Port J. Replace them by the proper Port K defines. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191218194812.12741-3-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 4a95867deb8a..4117bd8c0f41 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -2020,18 +2020,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, - PJ11_IN, PJ11_OUT, - PJ10_IN, PJ10_OUT, - PJ9_IN, PJ9_OUT, - PJ8_IN, PJ8_OUT, - PJ7_IN, PJ7_OUT, - PJ6_IN, PJ6_OUT, - PJ5_IN, PJ5_OUT, - PJ4_IN, PJ4_OUT, - PJ3_IN, PJ3_OUT, - PJ2_IN, PJ2_OUT, - PJ1_IN, PJ1_OUT, - PJ0_IN, PJ0_OUT )) + PK11_IN, PK11_OUT, + PK10_IN, PK10_OUT, + PK9_IN, PK9_OUT, + PK8_IN, PK8_OUT, + PK7_IN, PK7_OUT, + PK6_IN, PK6_OUT, + PK5_IN, PK5_OUT, + PK4_IN, PK4_OUT, + PK3_IN, PK3_OUT, + PK2_IN, PK2_OUT, + PK1_IN, PK1_OUT, + PK0_IN, PK0_OUT )) }, {} }; From 55b1cb1f03ad5eea39897d0c74035e02deddcff2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Dec 2019 20:48:09 +0100 Subject: [PATCH 59/99] pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the two CAN outputs. Fix this by: - Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010 configures the combined "CTX0&CTX1" output signal, - Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures the shared "CRX0/CRX1" input signal, which is fed to both CAN inputs, - Adding the missing function GPIO definition for "CTX0&CTX1" to pinmux_func_gpios[], - Moving all CAN enums next to each other. See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00: [1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte Version), [2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte Version, [3] Table 1.4 List of Pins, [4] Figure 20.29 Connection Example when Using This Module as 1-Channel Module (64 Mailboxes x 1 Channel), [5] Table 32.10 Multiplexed Pins (Port J), [6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0). Note that the last 2 disagree about PJ2MD[2:0], which is probably the root cause of this bug. But considering [4], "CTx0&CTx1" in [5] must be correct, and "CRx0&CRx1" in [6] must be wrong. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191218194812.12741-4-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 4117bd8c0f41..908837ea487b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -497,17 +497,15 @@ enum { SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, CRX0_MARK, CRX1_MARK, CTX0_MARK, CTX1_MARK, + CRX0_CRX1_MARK, CTX0_CTX1_MARK, PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK, PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK, PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK, PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK, IERXD_MARK, IETXD_MARK, - CRX0_CRX1_MARK, WDTOVF_MARK, - CRX0X1_MARK, - /* DMAC */ TEND0_MARK, DACK0_MARK, DREQ0_MARK, TEND1_MARK, DACK1_MARK, DREQ1_MARK, @@ -995,12 +993,12 @@ static const u16 pinmux_data[] = { PINMUX_DATA(PJ3_DATA, PJ3MD_00), PINMUX_DATA(CRX1_MARK, PJ3MD_01), - PINMUX_DATA(CRX0X1_MARK, PJ3MD_10), + PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10), PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11), PINMUX_DATA(PJ2_DATA, PJ2MD_000), PINMUX_DATA(CTX1_MARK, PJ2MD_001), - PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010), + PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010), PINMUX_DATA(CS2_MARK, PJ2MD_011), PINMUX_DATA(SCK0_MARK, PJ2MD_100), PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101), @@ -1245,6 +1243,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CTX1), GPIO_FN(CRX1), GPIO_FN(CTX0), + GPIO_FN(CTX0_CTX1), GPIO_FN(CRX0), GPIO_FN(CRX0_CRX1), From 02aeb2f21530c98fc3ca51028eda742a3fafbd9f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Dec 2019 20:48:10 +0100 Subject: [PATCH 60/99] pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the first two CAN outputs. A closer look reveals other issues: - Some functionality is available on alternative pins, but the PINMUX_DATA() entries is using the wrong marks, - Several configurations are missing. Fix this by: - Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK, resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the corresponding enum IDs, - Adding all missing enum IDs and marks, - Use the right (*_PJ2x) variants for alternative pins, - Adding all missing configurations to pinmux_data[], - Adding all missing function GPIO definitions to pinmux_func_gpios[]. See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00: [1] Table 1.4 List of Pins [2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel (32 Mailboxes × 1 Channel), [3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as One Channel (96 Mailboxes × 1 Channel), [4] Table 48.3 Multiplexed Pins (Port B), [5] Table 48.4 Multiplexed Pins (Port C), [6] Table 48.10 Multiplexed Pins (Port J), [7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191218194812.12741-5-geert+renesas@glider.be --- arch/sh/include/cpu-sh2a/cpu/sh7269.h | 11 ++++++-- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 39 ++++++++++++++++++--------- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h index d516e5d48818..b887cc402b71 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h @@ -78,8 +78,15 @@ enum { GPIO_FN_WDTOVF, /* CAN */ - GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, - GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2, + GPIO_FN_CTX2, GPIO_FN_CRX2, + GPIO_FN_CTX1, GPIO_FN_CRX1, + GPIO_FN_CTX0, GPIO_FN_CRX0, + GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1, + GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2, + GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20, + GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22, + GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22, + GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20, /* DMAC */ GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 6cbb18ef77dc..d20974a55d93 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -737,13 +737,12 @@ enum { CRX0_MARK, CTX0_MARK, CRX1_MARK, CTX1_MARK, CRX2_MARK, CTX2_MARK, - CRX0_CRX1_MARK, - CRX0_CRX1_CRX2_MARK, - CTX0CTX1CTX2_MARK, + CRX0_CRX1_MARK, CTX0_CTX1_MARK, + CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK, CRX1_PJ22_MARK, CTX1_PJ23_MARK, CRX2_PJ20_MARK, CTX2_PJ21_MARK, - CRX0CRX1_PJ22_MARK, - CRX0CRX1CRX2_PJ20_MARK, + CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK, + CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK, /* VDC */ DV_CLK_MARK, @@ -821,6 +820,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(CS3_MARK, PC8MD_001), PINMUX_DATA(TXD7_MARK, PC8MD_010), PINMUX_DATA(CTX1_MARK, PC8MD_011), + PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100), PINMUX_DATA(PC7_DATA, PC7MD_000), PINMUX_DATA(CKE_MARK, PC7MD_001), @@ -833,11 +833,12 @@ static const u16 pinmux_data[] = { PINMUX_DATA(CAS_MARK, PC6MD_001), PINMUX_DATA(SCK7_MARK, PC6MD_010), PINMUX_DATA(CTX0_MARK, PC6MD_011), + PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100), PINMUX_DATA(PC5_DATA, PC5MD_000), PINMUX_DATA(RAS_MARK, PC5MD_001), PINMUX_DATA(CRX0_MARK, PC5MD_011), - PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100), + PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100), PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101), PINMUX_DATA(PC4_DATA, PC4MD_00), @@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = { PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010), PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011), PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100), - PINMUX_DATA(CTX1_MARK, PJ23MD_101), + PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101), + PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110), PINMUX_DATA(PJ22_DATA, PJ22MD_000), PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001), PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010), PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011), PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100), - PINMUX_DATA(CRX1_MARK, PJ22MD_101), - PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110), + PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101), + PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110), PINMUX_DATA(PJ21_DATA, PJ21MD_000), PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001), PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010), PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011), PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100), - PINMUX_DATA(CTX2_MARK, PJ21MD_101), + PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101), + PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110), PINMUX_DATA(PJ20_DATA, PJ20MD_000), PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001), PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010), PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011), PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100), - PINMUX_DATA(CRX2_MARK, PJ20MD_101), - PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110), + PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101), + PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110), PINMUX_DATA(PJ19_DATA, PJ19MD_000), PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001), @@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(WDTOVF), /* CAN */ + GPIO_FN(CTX2), + GPIO_FN(CRX2), GPIO_FN(CTX1), GPIO_FN(CRX1), GPIO_FN(CTX0), GPIO_FN(CRX0), + GPIO_FN(CTX0_CTX1), GPIO_FN(CRX0_CRX1), + GPIO_FN(CTX0_CTX1_CTX2), GPIO_FN(CRX0_CRX1_CRX2), + GPIO_FN(CTX2_PJ21), + GPIO_FN(CRX2_PJ20), + GPIO_FN(CTX1_PJ23), + GPIO_FN(CRX1_PJ22), + GPIO_FN(CTX0_CTX1_PJ23), + GPIO_FN(CRX0_CRX1_PJ22), + GPIO_FN(CTX0_CTX1_CTX2_PJ21), + GPIO_FN(CRX0_CRX1_CRX2_PJ20), /* DMAC */ GPIO_FN(TEND0), From db9c07272c8245a2d7345336cfbe652af6182203 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Dec 2019 20:48:11 +0100 Subject: [PATCH 61/99] sh: sh7264: Remove bogus SSU GPIO function definitions SH7264 has no Synchronous Serial Communication Unit (SSU). Remove the bogus enum IDs, which caused holes in pinmux_func_gpios[]. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191218194812.12741-6-geert+renesas@glider.be --- arch/sh/include/cpu-sh2a/cpu/sh7264.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7264.h b/arch/sh/include/cpu-sh2a/cpu/sh7264.h index d12c19186845..8a1338aaf10a 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7264.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7264.h @@ -112,12 +112,6 @@ enum { GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, - /* SSU */ - GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, - GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, - GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, - GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, - /* SCIF */ GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3, GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3, From b4fba344a293076947fcf3d60dda51f955e19c77 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Dec 2019 20:48:12 +0100 Subject: [PATCH 62/99] sh: sh7269: Remove bogus SSU GPIO function definitions SH7269 has no Synchronous Serial Communication Unit (SSU). Remove the bogus enum IDs, which caused holes in pinmux_func_gpios[]. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191218194812.12741-7-geert+renesas@glider.be --- arch/sh/include/cpu-sh2a/cpu/sh7269.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h index b887cc402b71..fece521c74b3 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h @@ -126,12 +126,6 @@ enum { GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, - /* SSU */ - GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, - GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, - GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, - GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, - /* SCIF */ GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0, GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1, From b4a9372ad7598c85bd87c510fd6d4844e17ec93d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Mon, 16 Dec 2019 00:21:00 +0800 Subject: [PATCH 63/99] pinctrl: Ingenic: Fix bugs in X1000 and X1500. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Fix the pullup parameter of X1000. 2.X1000 and X1500 have only one set of uart1 hwflow pin mapping, so modify "uart1_hwflow_d" to "uart1_hwflow". 3.X1000 has only one set of mmc1 pin mapping, so modify "mmc1-1bit-e/mmc1-4bit-e" to "mmc1-1bit/mmc1-4bit". 4.X1000 has only one regular externel memory controller that does not support nand flash, so change "nemc_" to "emc_". 5.X1500 has only one set of mmc, so modify "mmc0_" to "mmc_". Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1576426864-35348-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 94 +++++++++++++++---------------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 369e04350e3d..aacd3b88b2ad 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1022,7 +1022,7 @@ static const struct ingenic_chip_info jz4780_chip_info = { }; static const u32 x1000_pull_ups[4] = { - 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff, + 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, }; static const u32 x1000_pull_downs[4] = { @@ -1033,7 +1033,7 @@ static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; -static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; @@ -1041,20 +1041,20 @@ static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; -static int x1000_nemc_8bit_data_pins[] = { +static int x1000_emc_8bit_data_pins[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, }; -static int x1000_nemc_16bit_data_pins[] = { +static int x1000_emc_16bit_data_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, }; -static int x1000_nemc_addr_pins[] = { +static int x1000_emc_addr_pins[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, }; -static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, }; -static int x1000_nemc_wait_pins[] = { 0x34, }; -static int x1000_nemc_cs1_pins[] = { 0x32, }; -static int x1000_nemc_cs2_pins[] = { 0x33, }; +static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; +static int x1000_emc_wait_pins[] = { 0x34, }; +static int x1000_emc_cs1_pins[] = { 0x32, }; +static int x1000_emc_cs2_pins[] = { 0x33, }; static int x1000_i2c0_pins[] = { 0x38, 0x37, }; static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; @@ -1083,7 +1083,7 @@ static int x1000_uart0_data_funcs[] = { 0, 0, }; static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; static int x1000_uart1_data_a_funcs[] = { 2, 2, }; static int x1000_uart1_data_d_funcs[] = { 1, 1, }; -static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; static int x1000_uart2_data_a_funcs[] = { 2, 2, }; static int x1000_uart2_data_d_funcs[] = { 0, 0, }; static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; @@ -1091,15 +1091,15 @@ static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; -static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_nemc_addr_funcs[] = { +static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_emc_addr_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_nemc_rd_we_funcs[] = { 0, 0, }; -static int x1000_nemc_wait_funcs[] = { 0, }; -static int x1000_nemc_cs1_funcs[] = { 0, }; -static int x1000_nemc_cs2_funcs[] = { 0, }; +static int x1000_emc_rd_we_funcs[] = { 0, 0, }; +static int x1000_emc_wait_funcs[] = { 0, }; +static int x1000_emc_cs1_funcs[] = { 0, }; +static int x1000_emc_cs2_funcs[] = { 0, }; static int x1000_i2c0_funcs[] = { 0, 0, }; static int x1000_i2c1_a_funcs[] = { 2, 2, }; static int x1000_i2c1_c_funcs[] = { 0, 0, }; @@ -1121,7 +1121,7 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), - INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), @@ -1129,13 +1129,13 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), - INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data), - INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data), - INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr), - INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we), - INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait), - INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1), - INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2), + INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), + INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), + INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), + INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), + INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), + INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), + INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), @@ -1154,21 +1154,21 @@ static const struct group_desc x1000_groups[] = { static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *x1000_uart1_groups[] = { - "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", + "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; static const char *x1000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; static const char *x1000_mmc1_groups[] = { - "mmc1-1bit-e", "mmc1-4bit-e", + "mmc1-1bit", "mmc1-4bit", }; -static const char *x1000_nemc_groups[] = { - "nemc-8bit-data", "nemc-16bit-data", - "nemc-addr", "nemc-rd-we", "nemc-wait", +static const char *x1000_emc_groups[] = { + "emc-8bit-data", "emc-16bit-data", + "emc-addr", "emc-rd-we", "emc-wait", }; -static const char *x1000_cs1_groups[] = { "nemc-cs1", }; -static const char *x1000_cs2_groups[] = { "nemc-cs2", }; +static const char *x1000_cs1_groups[] = { "emc-cs1", }; +static const char *x1000_cs2_groups[] = { "emc-cs2", }; static const char *x1000_i2c0_groups[] = { "i2c0-data", }; static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; static const char *x1000_i2c2_groups[] = { "i2c2-data", }; @@ -1189,9 +1189,9 @@ static const struct function_desc x1000_functions[] = { { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, - { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), }, - { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, - { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, + { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, + { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, + { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, @@ -1229,11 +1229,11 @@ static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; -static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; -static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; -static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; +static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; +static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; static int x1500_i2c0_pins[] = { 0x38, 0x37, }; static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; @@ -1252,11 +1252,11 @@ static int x1500_uart0_data_funcs[] = { 0, 0, }; static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; static int x1500_uart1_data_a_funcs[] = { 2, 2, }; static int x1500_uart1_data_d_funcs[] = { 1, 1, }; -static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; static int x1500_uart2_data_a_funcs[] = { 2, 2, }; static int x1500_uart2_data_d_funcs[] = { 0, 0, }; -static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, }; -static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, }; +static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; +static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; static int x1500_i2c0_funcs[] = { 0, 0, }; static int x1500_i2c1_a_funcs[] = { 2, 2, }; static int x1500_i2c1_c_funcs[] = { 0, 0, }; @@ -1273,11 +1273,11 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), - INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), - INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit), - INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit), + INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), + INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), @@ -1293,10 +1293,10 @@ static const struct group_desc x1500_groups[] = { static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *x1500_uart1_groups[] = { - "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", + "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; -static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; static const char *x1500_i2c0_groups[] = { "i2c0-data", }; static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; static const char *x1500_i2c2_groups[] = { "i2c2-data", }; @@ -1312,7 +1312,7 @@ static const struct function_desc x1500_functions[] = { { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, - { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), }, + { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, From 3b31e9b0eaaad3240110037a5572c891d11f8f83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Mon, 16 Dec 2019 00:21:01 +0800 Subject: [PATCH 64/99] pinctrl: Ingenic: Add missing parts for X1000 and X1500. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Add pinctrl drivers for the SPI flash controller (SFC) of X1000 and X1500. 2.Add pinctrl driver for the synchronous serial interface (SSI) of X1000. Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1576426864-35348-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index aacd3b88b2ad..e44a5c56c17c 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1036,6 +1036,23 @@ static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; +static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; +static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; +static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; +static int x1000_ssi_dt_d_pins[] = { 0x62, }; +static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; +static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; +static int x1000_ssi_dr_d_pins[] = { 0x63, }; +static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; +static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; +static int x1000_ssi_clk_d_pins[] = { 0x60, }; +static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; +static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; +static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; +static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; +static int x1000_ssi_ce0_d_pins[] = { 0x61, }; +static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; +static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; @@ -1086,6 +1103,23 @@ static int x1000_uart1_data_d_funcs[] = { 1, 1, }; static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; static int x1000_uart2_data_a_funcs[] = { 2, 2, }; static int x1000_uart2_data_d_funcs[] = { 0, 0, }; +static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int x1000_ssi_dt_a_22_funcs[] = { 2, }; +static int x1000_ssi_dt_a_29_funcs[] = { 2, }; +static int x1000_ssi_dt_d_funcs[] = { 0, }; +static int x1000_ssi_dr_a_23_funcs[] = { 2, }; +static int x1000_ssi_dr_a_28_funcs[] = { 2, }; +static int x1000_ssi_dr_d_funcs[] = { 0, }; +static int x1000_ssi_clk_a_24_funcs[] = { 2, }; +static int x1000_ssi_clk_a_26_funcs[] = { 2, }; +static int x1000_ssi_clk_d_funcs[] = { 0, }; +static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; +static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; +static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; +static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; +static int x1000_ssi_ce0_d_funcs[] = { 0, }; +static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; +static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; @@ -1124,6 +1158,23 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), + INGENIC_PIN_GROUP("sfc", x1000_sfc), + INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), + INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), + INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), + INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), + INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), + INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), + INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), + INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), + INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), + INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), + INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), + INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), + INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), + INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), + INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), + INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), @@ -1157,6 +1208,15 @@ static const char *x1000_uart1_groups[] = { "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; +static const char *x1000_sfc_groups[] = { "sfc", }; +static const char *x1000_ssi_groups[] = { + "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", + "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", + "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", + "ssi-gpc-a-20", "ssi-gpc-a-31", + "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", + "ssi-ce1-a-21", "ssi-ce1-a-30", +}; static const char *x1000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; @@ -1187,6 +1247,8 @@ static const struct function_desc x1000_functions[] = { { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, + { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, + { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, @@ -1276,6 +1338,7 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), + INGENIC_PIN_GROUP("sfc", x1000_sfc), INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), @@ -1312,6 +1375,7 @@ static const struct function_desc x1500_functions[] = { { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, + { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, From f742e5ebdd6332d887851cabb55c1b70535be331 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Mon, 16 Dec 2019 00:21:02 +0800 Subject: [PATCH 65/99] pinctrl: Ingenic: Introduce reg_offset and use it instead hard code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce "reg_offset", use it instead hard code "0x100", it will also be used for subsequent X1830 pinctrl driver. Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1576426864-35348-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index e44a5c56c17c..265b591fbd53 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -64,6 +64,7 @@ enum jz_version { struct ingenic_chip_info { unsigned int num_chips; + unsigned int reg_offset; const struct group_desc *groups; unsigned int num_groups; @@ -216,6 +217,7 @@ static const struct function_desc jz4740_functions[] = { static const struct ingenic_chip_info jz4740_chip_info = { .num_chips = 4, + .reg_offset = 0x100, .groups = jz4740_groups, .num_groups = ARRAY_SIZE(jz4740_groups), .functions = jz4740_functions, @@ -339,6 +341,7 @@ static const struct function_desc jz4725b_functions[] = { static const struct ingenic_chip_info jz4725b_chip_info = { .num_chips = 4, + .reg_offset = 0x100, .groups = jz4725b_groups, .num_groups = ARRAY_SIZE(jz4725b_groups), .functions = jz4725b_functions, @@ -592,6 +595,7 @@ static const struct function_desc jz4760_functions[] = { static const struct ingenic_chip_info jz4760_chip_info = { .num_chips = 6, + .reg_offset = 0x100, .groups = jz4760_groups, .num_groups = ARRAY_SIZE(jz4760_groups), .functions = jz4760_functions, @@ -602,6 +606,7 @@ static const struct ingenic_chip_info jz4760_chip_info = { static const struct ingenic_chip_info jz4760b_chip_info = { .num_chips = 6, + .reg_offset = 0x100, .groups = jz4760_groups, .num_groups = ARRAY_SIZE(jz4760_groups), .functions = jz4760_functions, @@ -880,6 +885,7 @@ static const struct function_desc jz4770_functions[] = { static const struct ingenic_chip_info jz4770_chip_info = { .num_chips = 6, + .reg_offset = 0x100, .groups = jz4770_groups, .num_groups = ARRAY_SIZE(jz4770_groups), .functions = jz4770_functions, @@ -1013,6 +1019,7 @@ static const struct function_desc jz4780_functions[] = { static const struct ingenic_chip_info jz4780_chip_info = { .num_chips = 6, + .reg_offset = 0x100, .groups = jz4780_groups, .num_groups = ARRAY_SIZE(jz4780_groups), .functions = jz4780_functions, @@ -1269,6 +1276,7 @@ static const struct function_desc x1000_functions[] = { static const struct ingenic_chip_info x1000_chip_info = { .num_chips = 4, + .reg_offset = 0x100, .groups = x1000_groups, .num_groups = ARRAY_SIZE(x1000_groups), .functions = x1000_functions, @@ -1279,6 +1287,7 @@ static const struct ingenic_chip_info x1000_chip_info = { static const struct ingenic_chip_info x1000e_chip_info = { .num_chips = 4, + .reg_offset = 0x100, .groups = x1000_groups, .num_groups = ARRAY_SIZE(x1000_groups), .functions = x1000_functions, @@ -1391,6 +1400,7 @@ static const struct function_desc x1500_functions[] = { static const struct ingenic_chip_info x1500_chip_info = { .num_chips = 4, + .reg_offset = 0x100, .groups = x1500_groups, .num_groups = ARRAY_SIZE(x1500_groups), .functions = x1500_functions, @@ -1675,7 +1685,7 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int offt = pin / PINS_PER_GPIO_CHIP; - regmap_write(jzpc->map, offt * 0x100 + + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); } @@ -1684,7 +1694,7 @@ static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, { unsigned int idx = pin % PINS_PER_GPIO_CHIP; - regmap_write(jzpc->map, X1000_GPIO_PZ_BASE + + regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); } @@ -1701,7 +1711,7 @@ static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, unsigned int offt = pin / PINS_PER_GPIO_CHIP; unsigned int val; - regmap_read(jzpc->map, offt * 0x100 + reg, &val); + regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); return val & BIT(idx); } @@ -2045,7 +2055,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, return -ENOMEM; jzgc->jzpc = jzpc; - jzgc->reg_base = bank * 0x100; + jzgc->reg_base = bank * jzpc->info->reg_offset; jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); if (!jzgc->gc.label) From 8bc49f4489bb1a4552a10f51bc642286509a9694 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Mon, 16 Dec 2019 00:21:03 +0800 Subject: [PATCH 66/99] dt-bindings: pinctrl: Add bindings for Ingenic X1830. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the pinctrl bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Acked-by: Rob Herring Link: https://lore.kernel.org/r/1576426864-35348-6-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index 0014d9899797..d9b2100c98e8 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO -ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 -contains 6 GPIO ports, PA to PF, for a total of 192 pins. +PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830 +contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the +jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -28,6 +28,7 @@ Required properties: - "ingenic,x1000-pinctrl" - "ingenic,x1000e-pinctrl" - "ingenic,x1500-pinctrl" + - "ingenic,x1830-pinctrl" - reg: Address range of the pinctrl registers. @@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips): - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" - "ingenic,x1000-gpio" + - "ingenic,x1830-gpio" - reg: The GPIO bank number. - interrupt-controller: Marks the device node as an interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. From d7da2a1e4e0840faced2891e1c5b668f9eea18f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Mon, 16 Dec 2019 00:21:04 +0800 Subject: [PATCH 67/99] pinctrl: Ingenic: Add pinctrl driver for X1830. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for probing the pinctrl-ingenic driver on the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1576426864-35348-7-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 280 ++++++++++++++++++++++++++++-- 1 file changed, 265 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 265b591fbd53..4b847906b711 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3,7 +3,7 @@ * Ingenic SoCs pinctrl driver * * Copyright (c) 2017 Paul Cercueil - * Copyright (c) 2019 Zhou Yanjie + * Copyright (c) 2019 周琰杰 (Zhou Yanjie) */ #include @@ -42,12 +42,19 @@ #define JZ4760_GPIO_FLAG 0x50 #define JZ4760_GPIO_PEN 0x70 -#define X1000_GPIO_PZ_BASE 0x700 -#define X1000_GPIO_PZ_GID2LD 0x7f0 +#define X1830_GPIO_PEL 0x110 +#define X1830_GPIO_PEH 0x120 #define REG_SET(x) ((x) + 0x4) #define REG_CLEAR(x) ((x) + 0x8) +#define REG_PZ_BASE(x) ((x) * 7) +#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) + +#define GPIO_PULL_DIS 0 +#define GPIO_PULL_UP 1 +#define GPIO_PULL_DOWN 2 + #define PINS_PER_GPIO_CHIP 32 enum jz_version { @@ -60,6 +67,7 @@ enum jz_version { ID_X1000, ID_X1000E, ID_X1500, + ID_X1830, }; struct ingenic_chip_info { @@ -1409,6 +1417,221 @@ static const struct ingenic_chip_info x1500_chip_info = { .pull_downs = x1000_pull_downs, }; +static const u32 x1830_pull_ups[4] = { + 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, +}; + +static const u32 x1830_pull_downs[4] = { + 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, +}; + +static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; +static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; +static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; +static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; +static int x1830_ssi0_dt_pins[] = { 0x4c, }; +static int x1830_ssi0_dr_pins[] = { 0x4b, }; +static int x1830_ssi0_clk_pins[] = { 0x4f, }; +static int x1830_ssi0_gpc_pins[] = { 0x4d, }; +static int x1830_ssi0_ce0_pins[] = { 0x50, }; +static int x1830_ssi0_ce1_pins[] = { 0x4e, }; +static int x1830_ssi1_dt_c_pins[] = { 0x53, }; +static int x1830_ssi1_dr_c_pins[] = { 0x54, }; +static int x1830_ssi1_clk_c_pins[] = { 0x57, }; +static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; +static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; +static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; +static int x1830_ssi1_dt_d_pins[] = { 0x62, }; +static int x1830_ssi1_dr_d_pins[] = { 0x63, }; +static int x1830_ssi1_clk_d_pins[] = { 0x66, }; +static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; +static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; +static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; +static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; +static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; +static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; +static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; +static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; +static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; +static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; +static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; +static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; +static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; +static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; +static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; +static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; +static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; +static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; +static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; +static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; +static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; +static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; +static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; +static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; +static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; +static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; +static int x1830_mac_pins[] = { + 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, +}; + +static int x1830_uart0_data_funcs[] = { 0, 0, }; +static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; +static int x1830_uart1_data_funcs[] = { 0, 0, }; +static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int x1830_ssi0_dt_funcs[] = { 0, }; +static int x1830_ssi0_dr_funcs[] = { 0, }; +static int x1830_ssi0_clk_funcs[] = { 0, }; +static int x1830_ssi0_gpc_funcs[] = { 0, }; +static int x1830_ssi0_ce0_funcs[] = { 0, }; +static int x1830_ssi0_ce1_funcs[] = { 0, }; +static int x1830_ssi1_dt_c_funcs[] = { 1, }; +static int x1830_ssi1_dr_c_funcs[] = { 1, }; +static int x1830_ssi1_clk_c_funcs[] = { 1, }; +static int x1830_ssi1_gpc_c_funcs[] = { 1, }; +static int x1830_ssi1_ce0_c_funcs[] = { 1, }; +static int x1830_ssi1_ce1_c_funcs[] = { 1, }; +static int x1830_ssi1_dt_d_funcs[] = { 2, }; +static int x1830_ssi1_dr_d_funcs[] = { 2, }; +static int x1830_ssi1_clk_d_funcs[] = { 2, }; +static int x1830_ssi1_gpc_d_funcs[] = { 2, }; +static int x1830_ssi1_ce0_d_funcs[] = { 2, }; +static int x1830_ssi1_ce1_d_funcs[] = { 2, }; +static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; +static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; +static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; +static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; +static int x1830_i2c0_funcs[] = { 1, 1, }; +static int x1830_i2c1_funcs[] = { 0, 0, }; +static int x1830_i2c2_funcs[] = { 1, 1, }; +static int x1830_pwm_pwm0_b_funcs[] = { 0, }; +static int x1830_pwm_pwm0_c_funcs[] = { 1, }; +static int x1830_pwm_pwm1_b_funcs[] = { 0, }; +static int x1830_pwm_pwm1_c_funcs[] = { 1, }; +static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; +static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; +static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; +static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; +static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; +static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; +static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; +static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; +static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; +static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; +static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; +static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; +static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + +static const struct group_desc x1830_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), + INGENIC_PIN_GROUP("sfc", x1830_sfc), + INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), + INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), + INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), + INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), + INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), + INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), + INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), + INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), + INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), + INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), + INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), + INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), + INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), + INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), + INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), + INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), + INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), + INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), + INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), + INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), + INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), + INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), + INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), + INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), + INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), + INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), + INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), + INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), + INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), + INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), + INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), + INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), + INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), + INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), + INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), + INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), + INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), + INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), + INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), + INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), + INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), + INGENIC_PIN_GROUP("mac", x1830_mac), +}; + +static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x1830_uart1_groups[] = { "uart1-data", }; +static const char *x1830_sfc_groups[] = { "sfc", }; +static const char *x1830_ssi0_groups[] = { + "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", +}; +static const char *x1830_ssi1_groups[] = { + "ssi1-dt-c", "ssi1-dt-d", + "ssi1-dr-c", "ssi1-dr-d", + "ssi1-clk-c", "ssi1-clk-d", + "ssi1-gpc-c", "ssi1-gpc-d", + "ssi1-ce0-c", "ssi1-ce0-d", + "ssi1-ce1-c", "ssi1-ce1-d", +}; +static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; +static const char *x1830_i2c0_groups[] = { "i2c0-data", }; +static const char *x1830_i2c1_groups[] = { "i2c1-data", }; +static const char *x1830_i2c2_groups[] = { "i2c2-data", }; +static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; +static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; +static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; +static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; +static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; +static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; +static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; +static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; +static const char *x1830_mac_groups[] = { "mac", }; + +static const struct function_desc x1830_functions[] = { + { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, + { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, + { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, + { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, + { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, + { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, + { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, + { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, + { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, + { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, + { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, + { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, + { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, + { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, + { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, + { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, + { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, + { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, + { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, +}; + +static const struct ingenic_chip_info x1830_chip_info = { + .num_chips = 4, + .reg_offset = 0x1000, + .groups = x1830_groups, + .num_groups = ARRAY_SIZE(x1830_groups), + .functions = x1830_functions, + .num_functions = ARRAY_SIZE(x1830_functions), + .pull_ups = x1830_pull_ups, + .pull_downs = x1830_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -1437,12 +1660,14 @@ static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, else reg = REG_CLEAR(reg); - regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); + regmap_write(jzgc->jzpc->map, REG_PZ_BASE( + jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); } static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) { - regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD, + regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( + jzgc->jzpc->info->reg_offset), jzgc->gc.base / PINS_PER_GPIO_CHIP); } @@ -1701,7 +1926,8 @@ static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, unsigned int pin) { - regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP); + regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), + pin / PINS_PER_GPIO_CHIP); } static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, @@ -1872,12 +2098,31 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, } static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, - unsigned int pin, bool enabled) + unsigned int pin, unsigned int bias) { - if (jzpc->version >= ID_JZ4760) - ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled); - else - ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled); + if (jzpc->version >= ID_X1830) { + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int half = PINS_PER_GPIO_CHIP / 2; + unsigned int idxh = pin % half * 2; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + + if (idx < half) { + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + + REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + + REG_SET(X1830_GPIO_PEL), bias << idxh); + } else { + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + + REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + + REG_SET(X1830_GPIO_PEH), bias << idxh); + } + + } else if (jzpc->version >= ID_JZ4760) { + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); + } else { + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); + } } static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, @@ -1917,7 +2162,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_BIAS_DISABLE: dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 'A' + offt, idx); - ingenic_set_bias(jzpc, pin, false); + ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); break; case PIN_CONFIG_BIAS_PULL_UP: @@ -1925,7 +2170,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 'A' + offt, idx); - ingenic_set_bias(jzpc, pin, true); + ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); break; case PIN_CONFIG_BIAS_PULL_DOWN: @@ -1933,7 +2178,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 'A' + offt, idx); - ingenic_set_bias(jzpc, pin, true); + ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); break; case PIN_CONFIG_OUTPUT: @@ -2023,6 +2268,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 }, + { .compatible = "ingenic,x1830-pinctrl", .data = (void *) ID_X1830 }, {}, }; @@ -2032,6 +2278,7 @@ static const struct of_device_id ingenic_gpio_of_match[] __initconst = { { .compatible = "ingenic,jz4770-gpio", }, { .compatible = "ingenic,jz4780-gpio", }, { .compatible = "ingenic,x1000-gpio", }, + { .compatible = "ingenic,x1830-gpio", }, {}, }; @@ -2153,7 +2400,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) else jzpc->version = (enum jz_version)id->driver_data; - if (jzpc->version >= ID_X1500) + if (jzpc->version >= ID_X1830) + chip_info = &x1830_chip_info; + else if (jzpc->version >= ID_X1500) chip_info = &x1500_chip_info; else if (jzpc->version >= ID_X1000E) chip_info = &x1000e_chip_info; @@ -2250,6 +2499,7 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = { { "x1000-pinctrl", ID_X1000 }, { "x1000e-pinctrl", ID_X1000E }, { "x1500-pinctrl", ID_X1500 }, + { "x1830-pinctrl", ID_X1830 }, {}, }; From 4805746420a96011af78437552f5231deef6f295 Mon Sep 17 00:00:00 2001 From: "Ben Dooks (Codethink)" Date: Wed, 18 Dec 2019 11:04:56 +0000 Subject: [PATCH 68/99] pinctrl: tegra: fix missing __iomem in suspend/resume The functions should have __iomem on the register pointer so add that to silence the following sparse warnings: drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: expected unsigned int [usertype] *regs drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: got void [noderef] * drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: expected void const volatile [noderef] *addr drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: got unsigned int [usertype] * drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: expected unsigned int [usertype] *regs drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: got void [noderef] * drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: expected void volatile [noderef] *addr drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: got unsigned int [usertype] * Signed-off-by: Ben Dooks (Codethink) Link: https://lore.kernel.org/r/20191218110456.2533088-1-ben.dooks@codethink.co.uk Reviewed-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 692d8b3e2a20..cefbbb8d1a68 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -648,7 +648,7 @@ static int tegra_pinctrl_suspend(struct device *dev) { struct tegra_pmx *pmx = dev_get_drvdata(dev); u32 *backup_regs = pmx->backup_regs; - u32 *regs; + u32 __iomem *regs; size_t bank_size; unsigned int i, k; @@ -666,7 +666,7 @@ static int tegra_pinctrl_resume(struct device *dev) { struct tegra_pmx *pmx = dev_get_drvdata(dev); u32 *backup_regs = pmx->backup_regs; - u32 *regs; + u32 __iomem *regs; size_t bank_size; unsigned int i, k; From 0434cd276e7265d6db2bc389a021b795ec16fa69 Mon Sep 17 00:00:00 2001 From: Rahul Tanwar Date: Wed, 18 Dec 2019 14:20:24 +0800 Subject: [PATCH 69/99] dt-bindings: pinctrl: intel: Update to use generic bindings Kernel 5.5 adds generic pin mux & cfg node schema. Update pinctrl bindings for LGM to use these newly added schemas. Also, rename filename to match the compatible string. Signed-off-by: Rahul Tanwar Link: https://lore.kernel.org/r/20191218062024.25475-1-rahul.tanwar@linux.intel.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/intel,lgm-io.yaml | 76 ++++++++++++ .../bindings/pinctrl/intel,lgm-pinctrl.yaml | 116 ------------------ 2 files changed, 76 insertions(+), 116 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml new file mode 100644 index 000000000000..a386fb520510 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-io.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain SoC pinmux & GPIO controller binding + +maintainers: + - Rahul Tanwar + +description: | + Pinmux & GPIO controller controls pin multiplexing & configuration including + GPIO function selection & GPIO attributes configuration. + +allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + +properties: + compatible: + const: intel,lgm-io + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + function: true + group: true + pins: true + pinmux: true + bias-pull-up: true + bias-pull-down: true + drive-strength: true + slew-rate: true + drive-open-drain: true + output-enable: true + + required: + - function + - group + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl: pinctrl@e2880000 { + compatible = "intel,lgm-io"; + reg = <0xe2880000 0x100000>; + + uart0-pins { + pins = <64>, /* UART_RX0 */ + <65>; /* UART_TX0 */ + function = "CONSOLE_UART0"; + pinmux = <1>, + <1>; + groups = "CONSOLE_UART0"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml deleted file mode 100644 index 240d429f773b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml +++ /dev/null @@ -1,116 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel Lightning Mountain SoC pinmux & GPIO controller binding - -maintainers: - - Rahul Tanwar - -description: | - Pinmux & GPIO controller controls pin multiplexing & configuration including - GPIO function selection & GPIO attributes configuration. - - Please refer to [1] for details of the common pinctrl bindings used by the - client devices. - - [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -properties: - compatible: - const: intel,lgm-io - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - '-pins$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - function: - $ref: /schemas/types.yaml#/definitions/string - description: - A string containing the name of the function to mux to the group. - - groups: - $ref: /schemas/types.yaml#/definitions/string-array - description: - An array of strings identifying the list of groups. - - pins: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: - List of pins to select with this function. - - pinmux: - description: The applicable mux group. - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32-array" - - bias-pull-up: - type: boolean - - bias-pull-down: - type: boolean - - drive-strength: - description: | - Selects the drive strength for the specified pins in mA. - 0: 2 mA - 1: 4 mA - 2: 8 mA - 3: 12 mA - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 2, 3] - - slew-rate: - type: boolean - description: | - Sets slew rate for specified pins. - 0: slow slew - 1: fast slew - - drive-open-drain: - type: boolean - - output-enable: - type: boolean - - required: - - function - - groups - - additionalProperties: false - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - pinctrl: pinctrl@e2880000 { - compatible = "intel,lgm-pinctrl"; - reg = <0xe2880000 0x100000>; - - uart0-pins { - pins = <64>, /* UART_RX0 */ - <65>; /* UART_TX0 */ - function = "CONSOLE_UART0"; - pinmux = <1>, - <1>; - groups = "CONSOLE_UART0"; - }; - }; - -... From 4b4e41f35cc700e328e693f0c18b24424ab47ff0 Mon Sep 17 00:00:00 2001 From: "Ben Dooks (Codethink)" Date: Wed, 18 Dec 2019 10:20:13 +0000 Subject: [PATCH 70/99] pinctrl: actions: remove duplicate dsi entry The dsi entry is defined identically twice, so remove the second one to remove the sparse warning: drivers/pinctrl/actions/pinctrl-s700.c:1581:10: warning: Initializer entry defined twice drivers/pinctrl/actions/pinctrl-s700.c:1586:10: also defined here Signed-off-by: Ben Dooks (Codethink) Link: https://lore.kernel.org/r/20191218102013.2465038-1-ben.dooks@codethink.co.uk Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-s700.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/actions/pinctrl-s700.c b/drivers/pinctrl/actions/pinctrl-s700.c index 8b8121e35edb..771d6fd50b45 100644 --- a/drivers/pinctrl/actions/pinctrl-s700.c +++ b/drivers/pinctrl/actions/pinctrl-s700.c @@ -1583,7 +1583,6 @@ static const struct owl_pinmux_func s700_functions[] = { [S700_MUX_USB30] = FUNCTION(usb30), [S700_MUX_CLKO_25M] = FUNCTION(clko_25m), [S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi), - [S700_MUX_DSI] = FUNCTION(dsi), [S700_MUX_NAND] = FUNCTION(nand), [S700_MUX_SPDIF] = FUNCTION(spdif), [S700_MUX_SIRQ0] = FUNCTION(sirq0), From f314f20b70356d9bb2bf1c854fae49922b626f6b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 18 Dec 2019 12:43:56 +0000 Subject: [PATCH 71/99] pinctrl: sunxi: sun50i-h5 use platform_irq_count platform_irq_count() is the more generic way (independent of device trees) to determine the count of available interrupts. So use this instead. As platform_irq_count() might return an error code (which of_irq_count doesn't) some additional handling is necessary. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/1576672860-14420-2-git-send-email-peng.fan@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c index a78d7b922ef4..31d62bbb7f43 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "pinctrl-sunxi.h" @@ -549,7 +548,17 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) { - switch (of_irq_count(pdev->dev.of_node)) { + int ret; + + ret = platform_irq_count(pdev); + if (ret < 0) { + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Couldn't determine irq count: %pe\n", + ERR_PTR(ret)); + return ret; + } + + switch (ret) { case 2: dev_warn(&pdev->dev, "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n"); From a9a79514c2ba75de8c55e2fcd8a3bbf185caeb41 Mon Sep 17 00:00:00 2001 From: "Ben Dooks (Codethink)" Date: Wed, 18 Dec 2019 10:28:04 +0000 Subject: [PATCH 72/99] pinctrl: qcom: make 'm_voc_groups' static The m_voc_groups is not declared outside of the driver, so make it static to avoid the following sparse wanrning: drivers/pinctrl/qcom/pinctrl-msm8976.c:592:12: warning: symbol 'm_voc_groups' was not declared. Should it be static? Signed-off-by: Ben Dooks (Codethink) Link: https://lore.kernel.org/r/20191218102804.2487374-1-ben.dooks@codethink.co.uk Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm8976.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index e1259ce27396..183f0b2d9f8e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -589,7 +589,7 @@ static const char * const blsp_uart5_groups[] = { static const char * const qdss_traceclk_a_groups[] = { "gpio46", }; -const char * const m_voc_groups[] = { +static const char * const m_voc_groups[] = { "gpio123", "gpio124", }; static const char * const blsp_i2c5_groups[] = { From d5d3594db9f0de02c9073f1b7c7bcd7f805be02a Mon Sep 17 00:00:00 2001 From: Ma Feng Date: Thu, 19 Dec 2019 10:51:05 +0800 Subject: [PATCH 73/99] pinctrl: armada-37xx: Remove unneeded semicolon Fixes coccicheck warning: drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:736:2-3: Unneeded semicolon drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:803:2-3: Unneeded semicolon Fixes: commit 5715092a458c ("pinctrl: armada-37xx: Add gpio support") commit 2f227605394b ("pinctrl: armada-37xx: Add irqchip support") Signed-off-by: Ma Feng Link: https://lore.kernel.org/r/1576723865-111331-1-git-send-email-mafeng.ma@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index aa9dcde0f069..9f0b3d38cc77 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -733,7 +733,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, ret = 0; break; } - }; + } if (ret) { dev_err(dev, "no gpio-controller child node\n"); return ret; @@ -800,7 +800,7 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, ret = 0; break; } - }; + } if (ret) return ret; From a2800cdb4337f9404b7bc74c41a8e890035ce48a Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Wed, 1 Jan 2020 08:43:26 +0100 Subject: [PATCH 74/99] pinctrl: ssbi-mpp: constify copied structure The pm8xxx_pinctrl_desc structure is only copied into another structure, so make it const. The opportunity for this change was found using Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/1577864614-5543-9-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 3d8b1d74fa2f..681d8dcf37e3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -430,7 +430,7 @@ static const struct pinconf_ops pm8xxx_pinconf_ops = { .pin_config_group_set = pm8xxx_pin_config_set, }; -static struct pinctrl_desc pm8xxx_pinctrl_desc = { +static const struct pinctrl_desc pm8xxx_pinctrl_desc = { .name = "pm8xxx_mpp", .pctlops = &pm8xxx_pinctrl_ops, .pmxops = &pm8xxx_pinmux_ops, From 8b1704bde133d216e16027ddb1f24ee8322fcfec Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Wed, 1 Jan 2020 08:43:32 +0100 Subject: [PATCH 75/99] pinctrl: qcom: ssbi-gpio: constify copied structure The pm8xxx_pinctrl_desc structure is only copied into another structure, so make it const. The opportunity for this change was found using Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/1577864614-5543-15-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index dca86886b1f9..c7912135bbfb 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -439,7 +439,7 @@ static const struct pinconf_ops pm8xxx_pinconf_ops = { .pin_config_group_set = pm8xxx_pin_config_set, }; -static struct pinctrl_desc pm8xxx_pinctrl_desc = { +static const struct pinctrl_desc pm8xxx_pinctrl_desc = { .name = "pm8xxx_gpio", .pctlops = &pm8xxx_pinctrl_ops, .pmxops = &pm8xxx_pinmux_ops, From 4611e73f3670cef28027d12c272da80ae06cc86e Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Wed, 1 Jan 2020 08:43:34 +0100 Subject: [PATCH 76/99] pinctrl: nuvoton: npcm7xx: constify copied structure The npcmgpio_irqchip structure is only copied into another structure, so make it const. The opportunity for this change was found using Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/1577864614-5543-17-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 22077cbe6880..a935065cdac4 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -331,7 +331,7 @@ static unsigned int npcmgpio_irq_startup(struct irq_data *d) return 0; } -static struct irq_chip npcmgpio_irqchip = { +static const struct irq_chip npcmgpio_irqchip = { .name = "NPCM7XX-GPIO-IRQ", .irq_ack = npcmgpio_irq_ack, .irq_unmask = npcmgpio_irq_unmask, From 5ab0c8e90191622750e29e5dc413f65ab290519a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 26 Dec 2019 20:14:25 +0100 Subject: [PATCH 77/99] pinctrl: meson: meson8b: add the GPIOH pinmux settings for ETH_RXD{2,3} GPIOH_5 and GPIOH_6 can have two Ethernet related functions: - GPIOH_5 can be ETH_TXD1 or ETH_RXD3 - GPIOH_6 can be ETH_TXD0 or ETH_RXD2 Add the bits for eth_rxd3_h and eth_rxd2_h so the ETH_RXD function can be disabled when using the ETH_TXD function of GPIOH_{5,6}. No problem was observed so far, but in theory this could lead to two different signals being routed to the same pad (which could break Ethernet). These settings were found in the public "Amlogic Ethernet controller user guide": http://openlinux.amlogic.com/@api/deki/files/75/=Amlogic_Ethenet_controller_user_Guide.pdf Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20191226191425.3797490-1-martin.blumenstingl@googlemail.com Reviewed-by: Neil Armstrong Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson8b.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 2d5339edd0b7..6cd4b3ec1b40 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -233,6 +233,8 @@ static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 }; static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 }; static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 }; +static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 }; +static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 }; static const unsigned int clk_24m_out_pins[] = { GPIOH_9 }; static const unsigned int spi_ss1_pins[] = { GPIOH_0 }; @@ -535,6 +537,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = { GROUP(spi_miso_1, 9, 12), GROUP(spi_mosi_1, 9, 11), GROUP(spi_sclk_1, 9, 10), + GROUP(eth_rxd3_h, 6, 15), + GROUP(eth_rxd2_h, 6, 14), GROUP(eth_txd3, 6, 13), GROUP(eth_txd2, 6, 12), GROUP(eth_tx_clk, 6, 11), @@ -746,7 +750,8 @@ static const char * const ethernet_groups[] = { "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1", "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk", - "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2" + "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2", + "eth_rxd3_h", "eth_rxd2_h" }; static const char * const i2c_a_groups[] = { From 5ec008bfac7da212fa0d3dea6d30c372bd7034f2 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 7 Jan 2020 00:27:07 +0100 Subject: [PATCH 78/99] pinctrl: ingenic: Remove platform ID table We enforce devicetree support in the Kconfig and all Ingenic boards without exception probe their drivers from devicetree. The code path to probe the driver from arch code can then be considered as dead code and removed. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200106232711.559727-2-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 26 ++------------------------ 1 file changed, 2 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 4b847906b711..10a94f2f8658 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -2369,9 +2369,6 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) struct ingenic_pinctrl *jzpc; struct pinctrl_desc *pctl_desc; void __iomem *base; - const struct platform_device_id *id = platform_get_device_id(pdev); - const struct of_device_id *of_id = of_match_device( - ingenic_pinctrl_of_match, dev); const struct ingenic_chip_info *chip_info; struct device_node *node; unsigned int i; @@ -2394,11 +2391,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) } jzpc->dev = dev; - - if (of_id) - jzpc->version = (enum jz_version)of_id->data; - else - jzpc->version = (enum jz_version)id->driver_data; + jzpc->version = (enum jz_version)of_device_get_match_data(dev); if (jzpc->version >= ID_X1830) chip_info = &x1830_chip_info; @@ -2489,26 +2482,11 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) return 0; } -static const struct platform_device_id ingenic_pinctrl_ids[] = { - { "jz4740-pinctrl", ID_JZ4740 }, - { "jz4725b-pinctrl", ID_JZ4725B }, - { "jz4760-pinctrl", ID_JZ4760 }, - { "jz4760b-pinctrl", ID_JZ4760B }, - { "jz4770-pinctrl", ID_JZ4770 }, - { "jz4780-pinctrl", ID_JZ4780 }, - { "x1000-pinctrl", ID_X1000 }, - { "x1000e-pinctrl", ID_X1000E }, - { "x1500-pinctrl", ID_X1500 }, - { "x1830-pinctrl", ID_X1830 }, - {}, -}; - static struct platform_driver ingenic_pinctrl_driver = { .driver = { .name = "pinctrl-ingenic", - .of_match_table = of_match_ptr(ingenic_pinctrl_of_match), + .of_match_table = ingenic_pinctrl_of_match, }, - .id_table = ingenic_pinctrl_ids, }; static int __init ingenic_pinctrl_drv_register(void) From baf15647387e82c18933fcf6c9c2dd77e18e950f Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 7 Jan 2020 00:27:08 +0100 Subject: [PATCH 79/99] pinctrl: ingenic: Put ingenic_chip_info pointer in match data Instead of passing a numeric ID as match data, and retrieve a pointer to the ingenic_chip_info structure in an ugly succession of if/else in the probe function, get the pointer to the ingenic_chip_info structure directly from the match data, and store the numeric ID inside the ingenic_chip_info structure. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200106232711.559727-3-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 102 +++++++++++++----------------- 1 file changed, 45 insertions(+), 57 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 10a94f2f8658..7a1d6a720b78 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -73,6 +73,7 @@ enum jz_version { struct ingenic_chip_info { unsigned int num_chips; unsigned int reg_offset; + enum jz_version version; const struct group_desc *groups; unsigned int num_groups; @@ -88,7 +89,6 @@ struct ingenic_pinctrl { struct regmap *map; struct pinctrl_dev *pctl; struct pinctrl_pin_desc *pdesc; - enum jz_version version; const struct ingenic_chip_info *info; }; @@ -226,6 +226,7 @@ static const struct function_desc jz4740_functions[] = { static const struct ingenic_chip_info jz4740_chip_info = { .num_chips = 4, .reg_offset = 0x100, + .version = ID_JZ4740, .groups = jz4740_groups, .num_groups = ARRAY_SIZE(jz4740_groups), .functions = jz4740_functions, @@ -350,6 +351,7 @@ static const struct function_desc jz4725b_functions[] = { static const struct ingenic_chip_info jz4725b_chip_info = { .num_chips = 4, .reg_offset = 0x100, + .version = ID_JZ4725B, .groups = jz4725b_groups, .num_groups = ARRAY_SIZE(jz4725b_groups), .functions = jz4725b_functions, @@ -604,6 +606,7 @@ static const struct function_desc jz4760_functions[] = { static const struct ingenic_chip_info jz4760_chip_info = { .num_chips = 6, .reg_offset = 0x100, + .version = ID_JZ4760, .groups = jz4760_groups, .num_groups = ARRAY_SIZE(jz4760_groups), .functions = jz4760_functions, @@ -615,6 +618,7 @@ static const struct ingenic_chip_info jz4760_chip_info = { static const struct ingenic_chip_info jz4760b_chip_info = { .num_chips = 6, .reg_offset = 0x100, + .version = ID_JZ4760B, .groups = jz4760_groups, .num_groups = ARRAY_SIZE(jz4760_groups), .functions = jz4760_functions, @@ -894,6 +898,7 @@ static const struct function_desc jz4770_functions[] = { static const struct ingenic_chip_info jz4770_chip_info = { .num_chips = 6, .reg_offset = 0x100, + .version = ID_JZ4770, .groups = jz4770_groups, .num_groups = ARRAY_SIZE(jz4770_groups), .functions = jz4770_functions, @@ -1028,6 +1033,7 @@ static const struct function_desc jz4780_functions[] = { static const struct ingenic_chip_info jz4780_chip_info = { .num_chips = 6, .reg_offset = 0x100, + .version = ID_JZ4780, .groups = jz4780_groups, .num_groups = ARRAY_SIZE(jz4780_groups), .functions = jz4780_functions, @@ -1285,6 +1291,7 @@ static const struct function_desc x1000_functions[] = { static const struct ingenic_chip_info x1000_chip_info = { .num_chips = 4, .reg_offset = 0x100, + .version = ID_X1000, .groups = x1000_groups, .num_groups = ARRAY_SIZE(x1000_groups), .functions = x1000_functions, @@ -1296,6 +1303,7 @@ static const struct ingenic_chip_info x1000_chip_info = { static const struct ingenic_chip_info x1000e_chip_info = { .num_chips = 4, .reg_offset = 0x100, + .version = ID_X1000E, .groups = x1000_groups, .num_groups = ARRAY_SIZE(x1000_groups), .functions = x1000_functions, @@ -1409,6 +1417,7 @@ static const struct function_desc x1500_functions[] = { static const struct ingenic_chip_info x1500_chip_info = { .num_chips = 4, .reg_offset = 0x100, + .version = ID_X1500, .groups = x1500_groups, .num_groups = ARRAY_SIZE(x1500_groups), .functions = x1500_functions, @@ -1624,6 +1633,7 @@ static const struct function_desc x1830_functions[] = { static const struct ingenic_chip_info x1830_chip_info = { .num_chips = 4, .reg_offset = 0x1000, + .version = ID_X1830, .groups = x1830_groups, .num_groups = ARRAY_SIZE(x1830_groups), .functions = x1830_functions, @@ -1682,7 +1692,7 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value) { - if (jzgc->jzpc->version >= ID_JZ4760) + if (jzgc->jzpc->info->version >= ID_JZ4760) ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); @@ -1693,7 +1703,7 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, { u8 reg1, reg2; - if (jzgc->jzpc->version >= ID_JZ4760) { + if (jzgc->jzpc->info->version >= ID_JZ4760) { reg1 = JZ4760_GPIO_PAT1; reg2 = JZ4760_GPIO_PAT0; } else { @@ -1703,7 +1713,7 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, switch (type) { case IRQ_TYPE_EDGE_RISING: - if (jzgc->jzpc->version >= ID_X1000) { + if (jzgc->jzpc->info->version >= ID_X1000) { ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); ingenic_gpio_shadow_set_bit_load(jzgc); @@ -1713,7 +1723,7 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, } break; case IRQ_TYPE_EDGE_FALLING: - if (jzgc->jzpc->version >= ID_X1000) { + if (jzgc->jzpc->info->version >= ID_X1000) { ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); ingenic_gpio_shadow_set_bit_load(jzgc); @@ -1723,7 +1733,7 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, } break; case IRQ_TYPE_LEVEL_HIGH: - if (jzgc->jzpc->version >= ID_X1000) { + if (jzgc->jzpc->info->version >= ID_X1000) { ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); ingenic_gpio_shadow_set_bit_load(jzgc); @@ -1734,7 +1744,7 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, break; case IRQ_TYPE_LEVEL_LOW: default: - if (jzgc->jzpc->version >= ID_X1000) { + if (jzgc->jzpc->info->version >= ID_X1000) { ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); ingenic_gpio_shadow_set_bit_load(jzgc); @@ -1768,7 +1778,7 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); int irq = irqd->hwirq; - if (jzgc->jzpc->version >= ID_JZ4760) + if (jzgc->jzpc->info->version >= ID_JZ4760) ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); @@ -1784,7 +1794,7 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) ingenic_gpio_irq_mask(irqd); - if (jzgc->jzpc->version >= ID_JZ4760) + if (jzgc->jzpc->info->version >= ID_JZ4760) ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); @@ -1809,7 +1819,7 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); } - if (jzgc->jzpc->version >= ID_JZ4760) + if (jzgc->jzpc->info->version >= ID_JZ4760) ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); @@ -1866,7 +1876,7 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irq_chip, desc); - if (jzgc->jzpc->version >= ID_JZ4760) + if (jzgc->jzpc->info->version >= ID_JZ4760) flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); else flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); @@ -1948,7 +1958,7 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) struct ingenic_pinctrl *jzpc = jzgc->jzpc; unsigned int pin = gc->base + offset; - if (jzpc->version >= ID_JZ4760) + if (jzpc->info->version >= ID_JZ4760) return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1); if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) @@ -1974,13 +1984,13 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 'A' + offt, idx, func); - if (jzpc->version >= ID_X1000) { + if (jzpc->info->version >= ID_X1000) { ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); ingenic_shadow_config_pin_load(jzpc, pin); - } else if (jzpc->version >= ID_JZ4760) { + } else if (jzpc->info->version >= ID_JZ4760) { ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, false); ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); @@ -2033,12 +2043,12 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 'A' + offt, idx, input ? "in" : "out"); - if (jzpc->version >= ID_X1000) { + if (jzpc->info->version >= ID_X1000) { ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); ingenic_shadow_config_pin_load(jzpc, pin); - } else if (jzpc->version >= ID_JZ4760) { + } else if (jzpc->info->version >= ID_JZ4760) { ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, true); ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); @@ -2068,7 +2078,7 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offt = pin / PINS_PER_GPIO_CHIP; bool pull; - if (jzpc->version >= ID_JZ4760) + if (jzpc->info->version >= ID_JZ4760) pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); else pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); @@ -2100,7 +2110,7 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, unsigned int pin, unsigned int bias) { - if (jzpc->version >= ID_X1830) { + if (jzpc->info->version >= ID_X1830) { unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int half = PINS_PER_GPIO_CHIP / 2; unsigned int idxh = pin % half * 2; @@ -2118,7 +2128,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, REG_SET(X1830_GPIO_PEH), bias << idxh); } - } else if (jzpc->version >= ID_JZ4760) { + } else if (jzpc->info->version >= ID_JZ4760) { ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); } else { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); @@ -2128,7 +2138,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, unsigned int pin, bool high) { - if (jzpc->version >= ID_JZ4760) + if (jzpc->info->version >= ID_JZ4760) ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); else ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); @@ -2258,20 +2268,6 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = { .reg_stride = 4, }; -static const struct of_device_id ingenic_pinctrl_of_match[] = { - { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 }, - { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B }, - { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 }, - { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B }, - { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 }, - { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, - { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, - { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, - { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 }, - { .compatible = "ingenic,x1830-pinctrl", .data = (void *) ID_X1830 }, - {}, -}; - static const struct of_device_id ingenic_gpio_of_match[] __initconst = { { .compatible = "ingenic,jz4740-gpio", }, { .compatible = "ingenic,jz4760-gpio", }, @@ -2391,29 +2387,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) } jzpc->dev = dev; - jzpc->version = (enum jz_version)of_device_get_match_data(dev); - - if (jzpc->version >= ID_X1830) - chip_info = &x1830_chip_info; - else if (jzpc->version >= ID_X1500) - chip_info = &x1500_chip_info; - else if (jzpc->version >= ID_X1000E) - chip_info = &x1000e_chip_info; - else if (jzpc->version >= ID_X1000) - chip_info = &x1000_chip_info; - else if (jzpc->version >= ID_JZ4780) - chip_info = &jz4780_chip_info; - else if (jzpc->version >= ID_JZ4770) - chip_info = &jz4770_chip_info; - else if (jzpc->version >= ID_JZ4760B) - chip_info = &jz4760b_chip_info; - else if (jzpc->version >= ID_JZ4760) - chip_info = &jz4760_chip_info; - else if (jzpc->version >= ID_JZ4725B) - chip_info = &jz4725b_chip_info; - else - chip_info = &jz4740_chip_info; - jzpc->info = chip_info; + jzpc->info = chip_info = of_device_get_match_data(dev); pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); if (!pctl_desc) @@ -2482,6 +2456,20 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) return 0; } +static const struct of_device_id ingenic_pinctrl_of_match[] = { + { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, + { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, + { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, + { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760b_chip_info }, + { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, + { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, + { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, + { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000e_chip_info }, + { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, + { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, + {}, +}; + static struct platform_driver ingenic_pinctrl_driver = { .driver = { .name = "pinctrl-ingenic", From 5ffdbb7ec9facf6d9854c67960f7ba3a4de86f58 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 7 Jan 2020 00:27:09 +0100 Subject: [PATCH 80/99] pinctrl: ingenic: Remove duplicated ingenic_chip_info structures Until there is the need to handle the JZ4760B and X1000E differently there is no reason to use a separate ingenic_chip_info since the data it contains is the same than for the JZ4760 and X1000 respectively. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200106232711.559727-4-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 30 ++---------------------------- 1 file changed, 2 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 7a1d6a720b78..7f73f27cce91 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -61,11 +61,9 @@ enum jz_version { ID_JZ4740, ID_JZ4725B, ID_JZ4760, - ID_JZ4760B, ID_JZ4770, ID_JZ4780, ID_X1000, - ID_X1000E, ID_X1500, ID_X1830, }; @@ -615,18 +613,6 @@ static const struct ingenic_chip_info jz4760_chip_info = { .pull_downs = jz4760_pull_downs, }; -static const struct ingenic_chip_info jz4760b_chip_info = { - .num_chips = 6, - .reg_offset = 0x100, - .version = ID_JZ4760B, - .groups = jz4760_groups, - .num_groups = ARRAY_SIZE(jz4760_groups), - .functions = jz4760_functions, - .num_functions = ARRAY_SIZE(jz4760_functions), - .pull_ups = jz4760_pull_ups, - .pull_downs = jz4760_pull_downs, -}; - static const u32 jz4770_pull_ups[6] = { 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, }; @@ -1300,18 +1286,6 @@ static const struct ingenic_chip_info x1000_chip_info = { .pull_downs = x1000_pull_downs, }; -static const struct ingenic_chip_info x1000e_chip_info = { - .num_chips = 4, - .reg_offset = 0x100, - .version = ID_X1000E, - .groups = x1000_groups, - .num_groups = ARRAY_SIZE(x1000_groups), - .functions = x1000_functions, - .num_functions = ARRAY_SIZE(x1000_functions), - .pull_ups = x1000_pull_ups, - .pull_downs = x1000_pull_downs, -}; - static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; @@ -2460,11 +2434,11 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, - { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760b_chip_info }, + { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info }, { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, - { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000e_chip_info }, + { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info }, { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, {}, From f831f93af676587c938459f7f0833707f3b623c1 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 7 Jan 2020 00:27:10 +0100 Subject: [PATCH 81/99] pinctrl: ingenic: Factorize irq_set_type function Simplify the code of the driver's irq_set_type() function by doing some factorization. The behaviour is unchanged. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200106232711.559727-5-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 68 ++++++++++++------------------- 1 file changed, 26 insertions(+), 42 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 7f73f27cce91..419717fc7793 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1676,6 +1676,25 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, u8 offset, unsigned int type) { u8 reg1, reg2; + bool val1, val2; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val1 = val2 = true; + break; + case IRQ_TYPE_EDGE_FALLING: + val1 = false; + val2 = true; + break; + case IRQ_TYPE_LEVEL_HIGH: + val1 = true; + val2 = false; + break; + case IRQ_TYPE_LEVEL_LOW: + default: + val1 = val2 = false; + break; + } if (jzgc->jzpc->info->version >= ID_JZ4760) { reg1 = JZ4760_GPIO_PAT1; @@ -1685,48 +1704,13 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, reg2 = JZ4740_GPIO_DIR; } - switch (type) { - case IRQ_TYPE_EDGE_RISING: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); - } - break; - case IRQ_TYPE_EDGE_FALLING: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); - } - break; - case IRQ_TYPE_LEVEL_HIGH: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); - } - break; - case IRQ_TYPE_LEVEL_LOW: - default: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); - } - break; + if (jzgc->jzpc->info->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, val1); + ingenic_gpio_set_bit(jzgc, reg1, offset, val2); } } From 94f7a2cb42bf7a2f8400ae461d899c8e5566bfdf Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 7 Jan 2020 00:27:11 +0100 Subject: [PATCH 82/99] pinctrl: ingenic: Use devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() instead of platform_get_resource + devm_ioremap_resource. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200106232711.559727-6-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 419717fc7793..96f04d121ebd 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -2332,8 +2332,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) if (!jzpc) return -ENOMEM; - base = devm_ioremap_resource(dev, - platform_get_resource(pdev, IORESOURCE_MEM, 0)); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); From 9a4c22740291103623c700d7a330c29ac8843dd5 Mon Sep 17 00:00:00 2001 From: "Ben Dooks (Codethink)" Date: Wed, 18 Dec 2019 10:16:02 +0000 Subject: [PATCH 83/99] pinctrl: artpec6: fix __iomem on reg in set The artpec6_pconf_set should have marked reg as __iomem, which ends up making sparse complain about address space conversions. Add the __iomem to silence the following warnings: drivers/pinctrl/pinctrl-artpec6.c:814:13: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:814:13: expected unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:814:13: got void [noderef] * drivers/pinctrl/pinctrl-artpec6.c:825:34: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:825:34: expected void const volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:825:34: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:827:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:827:25: expected void volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:827:25: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:837:34: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:837:34: expected void const volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:837:34: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:840:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:840:25: expected void volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:840:25: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:850:34: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:850:34: expected void const volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:850:34: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:853:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:853:25: expected void volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:853:25: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:864:34: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:864:34: expected void const volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:864:34: got unsigned int *reg drivers/pinctrl/pinctrl-artpec6.c:867:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/pinctrl-artpec6.c:867:25: expected void volatile [noderef] *addr drivers/pinctrl/pinctrl-artpec6.c:867:25: got unsigned int *reg Signed-off-by: Ben Dooks (Codethink) Link: https://lore.kernel.org/r/20191218101602.2442868-1-ben.dooks@codethink.co.uk [Changed unsigned int -> void for the reg pointer] Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-artpec6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c index 986e04ac6b5b..d6c9f9dcff97 100644 --- a/drivers/pinctrl/pinctrl-artpec6.c +++ b/drivers/pinctrl/pinctrl-artpec6.c @@ -798,7 +798,7 @@ static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param; unsigned int arg; unsigned int regval; - unsigned int *reg; + void __iomem *reg; int i; /* Check for valid pin */ From f2bc07562748c23609743ded0630ec965f9e4fec Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 30 Dec 2019 09:31:56 +0100 Subject: [PATCH 84/99] pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers, and with different Pin Function Controller blocks. Reflect this in the pinctrl configuration, by replacing the existing CONFIG_PINCTRL_PFC_R8A7795 symbol by two new config symbols: CONFIG_PINCTRL_PFC_R8A77950 and CONFIG_PINCTRL_PFC_R8A77951. The latter are selected automatically, depending on the soon-to-be-introduced corresponding SoC-specific config options, and on the current common config option, to relax dependencies. Rename the individual pin control driver source files from pfc-r8a7795-es1.c to pfc-r8a77950.c, and from pfc-r8a7795.c to pfc-r8a77951.c, and make them truly independent. As both SoCs share the same compatible value, special care must be taken to match them to the correct pin control driver, if support for it is included in the running kernel. This will allow making support for early R-Car H3 revisions optional, the largest share of which is taken by the pin control driver. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Niklas Söderlund Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20191230083156.19191-1-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/Kconfig | 10 +++- drivers/pinctrl/sh-pfc/Makefile | 4 +- drivers/pinctrl/sh-pfc/core.c | 57 ++++++++++++++----- .../{pfc-r8a7795-es1.c => pfc-r8a77950.c} | 26 ++++----- .../sh-pfc/{pfc-r8a7795.c => pfc-r8a77951.c} | 39 +++++-------- drivers/pinctrl/sh-pfc/sh_pfc.h | 4 +- 6 files changed, 81 insertions(+), 59 deletions(-) rename drivers/pinctrl/sh-pfc/{pfc-r8a7795-es1.c => pfc-r8a77950.c} (99%) rename drivers/pinctrl/sh-pfc/{pfc-r8a7795.c => pfc-r8a77951.c} (99%) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index ecf3b045bf75..cf0e0dc42b84 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -26,7 +26,8 @@ config PINCTRL_SH_PFC select PINCTRL_PFC_R8A7792 if ARCH_R8A7792 select PINCTRL_PFC_R8A7793 if ARCH_R8A7793 select PINCTRL_PFC_R8A7794 if ARCH_R8A7794 - select PINCTRL_PFC_R8A7795 if ARCH_R8A7795 + select PINCTRL_PFC_R8A77950 if ARCH_R8A77950 || ARCH_R8A7795 + select PINCTRL_PFC_R8A77951 if ARCH_R8A77951 || ARCH_R8A7795 select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 select PINCTRL_PFC_R8A77961 if ARCH_R8A77961 select PINCTRL_PFC_R8A77965 if ARCH_R8A77965 @@ -115,8 +116,11 @@ config PINCTRL_PFC_R8A7793 config PINCTRL_PFC_R8A7794 bool "R-Car E2 pin control support" if COMPILE_TEST -config PINCTRL_PFC_R8A7795 - bool "R-Car H3 pin control support" if COMPILE_TEST +config PINCTRL_PFC_R8A77950 + bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST + +config PINCTRL_PFC_R8A77951 + bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77960 bool "R-Car M3-W pin control support" if COMPILE_TEST diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 3bc05666e1a6..9ebe321d24c4 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -18,8 +18,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o -obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o -obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o +obj-$(CONFIG_PINCTRL_PFC_R8A77950) += pfc-r8a77950.o +obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 65e52688f091..82209116955b 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "core.h" @@ -568,18 +569,18 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7794_pinmux_info, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +/* Both r8a7795 entries must be present to make sanity checks work */ +#ifdef CONFIG_PINCTRL_PFC_R8A77950 { .compatible = "renesas,pfc-r8a7795", - .data = &r8a7795_pinmux_info, + .data = &r8a77950_pinmux_info, }, -#ifdef DEBUG +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A77951 { - /* For sanity checks only (nothing matches against this) */ - .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */ - .data = &r8a7795es1_pinmux_info, + .compatible = "renesas,pfc-r8a7795", + .data = &r8a77951_pinmux_info, }, -#endif /* DEBUG */ #endif #ifdef CONFIG_PINCTRL_PFC_R8A77960 { @@ -886,19 +887,49 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} #endif /* !DEBUG */ +#ifdef CONFIG_OF +static const void *sh_pfc_quirk_match(void) +{ +#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \ + defined(CONFIG_PINCTRL_PFC_R8A77951) + const struct soc_device_attribute *match; + static const struct soc_device_attribute quirks[] = { + { + .soc_id = "r8a7795", .revision = "ES1.*", + .data = &r8a77950_pinmux_info, + }, + { + .soc_id = "r8a7795", + .data = &r8a77951_pinmux_info, + }, + + { /* sentinel */ } + }; + + match = soc_device_match(quirks); + if (match) + return match->data ?: ERR_PTR(-ENODEV); +#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */ + + return NULL; +} +#endif /* CONFIG_OF */ + static int sh_pfc_probe(struct platform_device *pdev) { -#ifdef CONFIG_OF - struct device_node *np = pdev->dev.of_node; -#endif const struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; #ifdef CONFIG_OF - if (np) - info = of_device_get_match_data(&pdev->dev); - else + if (pdev->dev.of_node) { + info = sh_pfc_quirk_match(); + if (IS_ERR(info)) + return PTR_ERR(info); + + if (!info) + info = of_device_get_match_data(&pdev->dev); + } else #endif info = (const void *)platform_get_device_id(pdev)->driver_data; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a77950.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c rename to drivers/pinctrl/sh-pfc/pfc-r8a77950.c index ad05da8f6516..04812e62f3a4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77950.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * R8A7795 ES1.x processor support - PFC hardware block. + * R8A77950 processor support - PFC hardware block. * * Copyright (C) 2015-2017 Renesas Electronics Corporation */ @@ -5562,8 +5562,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) { int bit = -EINVAL; @@ -5820,8 +5820,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) +static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) { const struct pinmux_bias_reg *reg; unsigned int bit; @@ -5838,8 +5838,8 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, return PIN_CONFIG_BIAS_PULL_DOWN; } -static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) +static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) { const struct pinmux_bias_reg *reg; u32 enable, updown; @@ -5861,15 +5861,15 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); } -static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = { - .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl, - .get_bias = r8a7795es1_pinmux_get_bias, - .set_bias = r8a7795es1_pinmux_set_bias, +static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { + .pin_to_pocctrl = r8a77950_pin_to_pocctrl, + .get_bias = r8a77950_pinmux_get_bias, + .set_bias = r8a77950_pinmux_set_bias, }; -const struct sh_pfc_soc_info r8a7795es1_pinmux_info = { +const struct sh_pfc_soc_info r8a77950_pinmux_info = { .name = "r8a77950_pfc", - .ops = &r8a7795es1_pinmux_ops, + .ops = &r8a77950_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a7795.c rename to drivers/pinctrl/sh-pfc/pfc-r8a77951.c index d3145aa135d0..256fab4b03d3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * R8A7795 ES2.0+ processor support - PFC hardware block. + * R8A77951 processor support - PFC hardware block. * * Copyright (C) 2015-2019 Renesas Electronics Corporation */ @@ -5915,7 +5915,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, + unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6172,8 +6173,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) +static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) { const struct pinmux_bias_reg *reg; unsigned int bit; @@ -6190,8 +6191,8 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, return PIN_CONFIG_BIAS_PULL_DOWN; } -static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) +static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) { const struct pinmux_bias_reg *reg; u32 enable, updown; @@ -6213,29 +6214,15 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); } -static const struct soc_device_attribute r8a7795es1[] = { - { .soc_id = "r8a7795", .revision = "ES1.*" }, - { /* sentinel */ } +static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { + .pin_to_pocctrl = r8a77951_pin_to_pocctrl, + .get_bias = r8a77951_pinmux_get_bias, + .set_bias = r8a77951_pinmux_set_bias, }; -static int r8a7795_pinmux_init(struct sh_pfc *pfc) -{ - if (soc_device_match(r8a7795es1)) - pfc->info = &r8a7795es1_pinmux_info; - - return 0; -} - -static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { - .init = r8a7795_pinmux_init, - .pin_to_pocctrl = r8a7795_pin_to_pocctrl, - .get_bias = r8a7795_pinmux_get_bias, - .set_bias = r8a7795_pinmux_set_bias, -}; - -const struct sh_pfc_soc_info r8a7795_pinmux_info = { +const struct sh_pfc_soc_info r8a77951_pinmux_info = { .name = "r8a77951_pfc", - .ops = &r8a7795_pinmux_ops, + .ops = &r8a77951_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 640d2a4cb838..d57e633e99c0 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -318,8 +318,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; -extern const struct sh_pfc_soc_info r8a7795_pinmux_info; -extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; +extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak; +extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak; extern const struct sh_pfc_soc_info r8a77960_pinmux_info; extern const struct sh_pfc_soc_info r8a77961_pinmux_info; extern const struct sh_pfc_soc_info r8a77965_pinmux_info; From f0682757230bdfc58118125dc81d805a427766b8 Mon Sep 17 00:00:00 2001 From: Boyan Ding Date: Wed, 1 Jan 2020 12:41:20 -0800 Subject: [PATCH 85/99] pinctrl: sunrisepoint: Add missing Interrupt Status register offset Commit 179e5a6114cc ("pinctrl: intel: Remove default Interrupt Status offset") removes default interrupt status offset of GPIO controllers, with previous commits explicitly providing the previously default offsets. However, the is_offset value in SPTH_COMMUNITY is missing, preventing related irq from being properly detected and handled. Fixes: f702e0b93cdb ("pinctrl: sunrisepoint: Provide Interrupt Status register offset") Link: https://bugzilla.kernel.org/show_bug.cgi?id=205745 Cc: stable@vger.kernel.org Signed-off-by: Boyan Ding Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 44d7f50bbc82..d936e7aa74c4 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -49,6 +49,7 @@ .padown_offset = SPT_PAD_OWN, \ .padcfglock_offset = SPT_PADCFGLOCK, \ .hostown_offset = SPT_HOSTSW_OWN, \ + .is_offset = SPT_GPI_IS, \ .ie_offset = SPT_GPI_IE, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ From a23680594da7a9e2696dbcf4f023e9273e2fa40b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 28 Dec 2019 00:04:47 +0100 Subject: [PATCH 86/99] pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins Suspending Goodix touchscreens requires changing the interrupt pin to output before sending them a power-down command. Followed by wiggling the interrupt pin to wake the device up, after which it is put back in input mode. On Bay Trail devices with a Goodix touchscreen direct-irq mode is used in combination with listing the pin as a normal GpioIo resource. This works fine, until the goodix driver gets rmmod-ed and then insmod-ed again. In this case byt_gpio_disable_free() calls byt_gpio_clear_triggering() which clears the IRQ flags and after that the (direct) IRQ no longer triggers. This commit fixes this by adding a check for the BYT_DIRECT_IRQ_EN flag to byt_gpio_clear_triggering(). Note that byt_gpio_clear_triggering() only gets called from byt_gpio_disable_free() for direct-irq enabled pins, as these are excluded from the irq_valid mask by byt_init_irq_valid_mask(). Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index cb0c04c5269c..394d9cc38cc2 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -742,7 +742,13 @@ static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int off raw_spin_lock_irqsave(&byt_lock, flags); value = readl(reg); - value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + + /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ + if (value & BYT_DIRECT_IRQ_EN) + /* nothing to do */ ; + else + value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + writel(value, reg); raw_spin_unlock_irqrestore(&byt_lock, flags); } From e2b74419e5cc7cfc58f3e785849f73f8fa0af5b3 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 1 Jan 2020 15:52:43 +0100 Subject: [PATCH 87/99] pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output Suspending Goodix touchscreens requires changing the interrupt pin to output before sending them a power-down command. Followed by wiggling the interrupt pin to wake the device up, after which it is put back in input mode. On Cherry Trail device the interrupt pin is listed as a GpioInt ACPI resource so we can do this without problems as long as we release the IRQ before changing the pin to output mode. On Bay Trail devices with a Goodix touchscreen direct-irq mode is used in combination with listing the pin as a normal GpioIo resource. This works fine, but this triggers the WARN in byt_gpio_set_direction-s output path because direct-irq support is enabled on the pin. This commit replaces the WARN call with a dev_info_once call, fixing a bunch of WARN splats in dmesg on each suspend/resume cycle. Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 394d9cc38cc2..b409642f168d 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -817,15 +817,15 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, value &= ~BYT_DIR_MASK; if (input) value |= BYT_OUTPUT_EN; - else + else if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) /* * Before making any direction modifications, do a check if gpio * is set for direct IRQ. On baytrail, setting GPIO to output - * does not make sense, so let's at least warn the caller before + * does not make sense, so let's at least inform the caller before * they shoot themselves in the foot. */ - WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, - "Potential Error: Setting GPIO with direct_irq_en to output"); + dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); + writel(value, val_reg); raw_spin_unlock_irqrestore(&byt_lock, flags); From 6d416b9bb577cc3013301cfccb0d938567af489d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Jan 2020 08:53:28 +0100 Subject: [PATCH 88/99] pinctrl: intel: Add GPIO <-> pin mapping ranges via callback When IRQ chip is instantiated via GPIO library flow, the few functions, in particular the ACPI event registration mechanism, on some of ACPI based platforms expect that the pin ranges are initialized to that point. Add GPIO <-> pin mapping ranges via callback in the GPIO library flow. Cc: Hans de Goede Signed-off-by: Linus Walleij Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 35 +++++++++++++++++---------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 06be75a636ba..2f4629bbb313 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1130,8 +1130,8 @@ static irqreturn_t intel_gpio_irq(int irq, void *data) return ret; } -static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, - const struct intel_community *community) +static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, + const struct intel_community *community) { int ret = 0, i; @@ -1151,6 +1151,24 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, return ret; } +static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) +{ + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); + int ret, i; + + for (i = 0; i < pctrl->ncommunities; i++) { + struct intel_community *community = &pctrl->communities[i]; + + ret = intel_gpio_add_community_ranges(pctrl, community); + if (ret) { + dev_err(pctrl->dev, "failed to add GPIO pin range\n"); + return ret; + } + } + + return 0; +} + static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) { const struct intel_community *community; @@ -1175,7 +1193,7 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) { - int ret, i; + int ret; pctrl->chip = intel_gpio_chip; @@ -1184,6 +1202,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.parent = pctrl->dev; pctrl->chip.base = -1; + pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; pctrl->irq = irq; /* Setup IRQ chip */ @@ -1201,16 +1220,6 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) return ret; } - for (i = 0; i < pctrl->ncommunities; i++) { - struct intel_community *community = &pctrl->communities[i]; - - ret = intel_gpio_add_pin_ranges(pctrl, community); - if (ret) { - dev_err(pctrl->dev, "failed to add GPIO pin range\n"); - return ret; - } - } - /* * We need to request the interrupt here (instead of providing chip * to the irq directly) because on some platforms several GPIO From af0c5330916a1ffd6cc0ffd6bea50688d99bf444 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Jan 2020 08:53:29 +0100 Subject: [PATCH 89/99] pinctrl: intel: Pass irqchip when adding gpiochip We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Hans de Goede Signed-off-by: Linus Walleij Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 2f4629bbb313..74fdfd2b9ff5 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1194,6 +1194,7 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) { int ret; + struct gpio_irq_chip *girq; pctrl->chip = intel_gpio_chip; @@ -1214,16 +1215,9 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake; pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; - ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); - if (ret) { - dev_err(pctrl->dev, "failed to register gpiochip\n"); - return ret; - } - /* - * We need to request the interrupt here (instead of providing chip - * to the irq directly) because on some platforms several GPIO - * controllers share the same interrupt line. + * On some platforms several GPIO controllers share the same interrupt + * line. */ ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED | IRQF_NO_THREAD, @@ -1233,14 +1227,20 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) return ret; } - ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0, - handle_bad_irq, IRQ_TYPE_NONE); + girq = &pctrl->chip.irq; + girq->chip = &pctrl->irqchip; + /* This will let us handle the IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); if (ret) { - dev_err(pctrl->dev, "failed to add irqchip\n"); + dev_err(pctrl->dev, "failed to register gpiochip\n"); return ret; } - gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL); return 0; } From 4784adc69a80188d842624ab1519e056a67cc0bd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 13 Jan 2020 22:26:29 +0100 Subject: [PATCH 90/99] pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema This fixes some problems that caused build errors in the lgm-io schema file: - No "bindings" infix in the schema id - Move the allOf inclusion for pinconf and pinmux nodes into the patternProperties for the -pins node - We want "groups" not "group" to be compulsory for a pinmux node blended with a pin config node. - Fix the generic pinmux-schema to list "groups" rather than "group" for a pinmux node, this might have led to some confusion. This is a first user of the generic schema so a bit of a bumpy road. Cc: Rob Herring Cc: Rahul Tanwar Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/intel,lgm-io.yaml | 13 ++++++------- .../devicetree/bindings/pinctrl/pinmux-node.yaml | 2 +- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml index a386fb520510..cd2b436350ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-io.yaml# +$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel Lightning Mountain SoC pinmux & GPIO controller binding @@ -13,10 +13,6 @@ description: | Pinmux & GPIO controller controls pin multiplexing & configuration including GPIO function selection & GPIO attributes configuration. -allOf: - - $ref: pincfg-node.yaml# - - $ref: pinmux-node.yaml# - properties: compatible: const: intel,lgm-io @@ -28,13 +24,16 @@ properties: patternProperties: '-pins$': type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. properties: function: true - group: true + groups: true pins: true pinmux: true bias-pull-up: true @@ -46,7 +45,7 @@ patternProperties: required: - function - - group + - groups additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml b/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml index 777623a57fd5..732d9075560b 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml @@ -114,7 +114,7 @@ properties: specific binding for the hardware defines whether the entries are integers or strings, and their meaning. - group: + groups: $ref: /schemas/types.yaml#/definitions/string-array description: the group to apply the properties to, if the driver supports From 783e998653b430a159f83552fa263f57bf8e2055 Mon Sep 17 00:00:00 2001 From: Rayagonda Kokatanur Date: Fri, 10 Jan 2020 09:25:24 +0530 Subject: [PATCH 91/99] pinctrl: iproc: Use platform_get_irq_optional() to avoid error message Use platform_get_irq_optional() instead of platform_get_irq() to avoid below error message during probe: [ 0.589121] iproc-gpio 66424800.gpio: IRQ index 0 not found Signed-off-by: Rayagonda Kokatanur Link: https://lore.kernel.org/r/20200110035524.23511-1-rayagonda.kokatanur@broadcom.com Reviewed-by: Chris Packham Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index aa9b5ba1bf38..25166217c3e0 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -849,7 +849,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) "gpio-ranges"); /* optional GPIO interrupt support */ - irq = platform_get_irq(pdev, 0); + irq = platform_get_irq_optional(pdev, 0); if (irq > 0) { struct irq_chip *irqc; struct gpio_irq_chip *girq; From 899b7e3374b253888b048dd06338e043e4b7637c Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 16 Jan 2020 13:09:51 +0200 Subject: [PATCH 92/99] pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID Intel Coffee Lake-S PCH has the same GPIO hardware than Sunrisepoint-H PCH but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Signed-off-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index d936e7aa74c4..330c8f077b73 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -589,6 +589,7 @@ static const struct intel_pinctrl_soc_data spth_soc_data = { static const struct acpi_device_id spt_pinctrl_acpi_match[] = { { "INT344B", (kernel_ulong_t)&sptlp_soc_data }, + { "INT3451", (kernel_ulong_t)&spth_soc_data }, { "INT345D", (kernel_ulong_t)&spth_soc_data }, { } }; From cd0a32371db73d0b50536a7ca4f036abddff0d1d Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 16 Jan 2020 14:09:02 +0300 Subject: [PATCH 93/99] pinctrl: tigerlake: Tiger Lake uses _HID enumeration Turns out that Tiger Lake GPIO will be enumerated using _HID method where there is only a single ACPI device and multiple BARs so rework the driver to support that scheme instead. Fixes: c9ccf71fc807 ("pinctrl: intel: Add Intel Tiger Lake pin controller support") Signed-off-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 561 ++++++++++------------ 1 file changed, 257 insertions(+), 304 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 58572b15b3ce..08a86f6fdea6 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -2,7 +2,7 @@ /* * Intel Tiger Lake PCH pinctrl/GPIO driver * - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2019 - 2020, Intel Corporation * Authors: Andy Shevchenko * Mika Westerberg */ @@ -21,15 +21,19 @@ #define TGL_GPI_IS 0x100 #define TGL_GPI_IE 0x120 -#define TGL_GPP(r, s, e) \ +#define TGL_NO_GPIO -1 + +#define TGL_GPP(r, s, e, g) \ { \ .reg_num = (r), \ .base = (s), \ .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ } -#define TGL_COMMUNITY(s, e, g) \ +#define TGL_COMMUNITY(b, s, e, g) \ { \ + .barno = (b), \ .padown_offset = TGL_PAD_OWN, \ .padcfglock_offset = TGL_PADCFGLOCK, \ .hostown_offset = TGL_HOSTSW_OWN, \ @@ -42,7 +46,7 @@ } /* Tiger Lake-LP */ -static const struct pinctrl_pin_desc tgllp_community0_pins[] = { +static const struct pinctrl_pin_desc tgllp_pins[] = { /* GPP_B */ PINCTRL_PIN(0, "CORE_VID_0"), PINCTRL_PIN(1, "CORE_VID_1"), @@ -113,324 +117,273 @@ static const struct pinctrl_pin_desc tgllp_community0_pins[] = { PINCTRL_PIN(64, "GPPC_A_22"), PINCTRL_PIN(65, "I2S1_SCLK"), PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(67, "SNDW0_CLK"), + PINCTRL_PIN(68, "SNDW0_DATA"), + PINCTRL_PIN(69, "SNDW1_CLK"), + PINCTRL_PIN(70, "SNDW1_DATA"), + PINCTRL_PIN(71, "SNDW2_CLK"), + PINCTRL_PIN(72, "SNDW2_DATA"), + PINCTRL_PIN(73, "SNDW3_CLK"), + PINCTRL_PIN(74, "SNDW3_DATA"), + /* GPP_H */ + PINCTRL_PIN(75, "GPPC_H_0"), + PINCTRL_PIN(76, "GPPC_H_1"), + PINCTRL_PIN(77, "GPPC_H_2"), + PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(79, "I2C2_SDA"), + PINCTRL_PIN(80, "I2C2_SCL"), + PINCTRL_PIN(81, "I2C3_SDA"), + PINCTRL_PIN(82, "I2C3_SCL"), + PINCTRL_PIN(83, "I2C4_SDA"), + PINCTRL_PIN(84, "I2C4_SCL"), + PINCTRL_PIN(85, "SRCCLKREQB_4"), + PINCTRL_PIN(86, "SRCCLKREQB_5"), + PINCTRL_PIN(87, "M2_SKT2_CFG_0"), + PINCTRL_PIN(88, "M2_SKT2_CFG_1"), + PINCTRL_PIN(89, "M2_SKT2_CFG_2"), + PINCTRL_PIN(90, "M2_SKT2_CFG_3"), + PINCTRL_PIN(91, "DDPB_CTRLCLK"), + PINCTRL_PIN(92, "DDPB_CTRLDATA"), + PINCTRL_PIN(93, "CPU_C10_GATEB"), + PINCTRL_PIN(94, "TIME_SYNC_0"), + PINCTRL_PIN(95, "IMGCLKOUT_1"), + PINCTRL_PIN(96, "IMGCLKOUT_2"), + PINCTRL_PIN(97, "IMGCLKOUT_3"), + PINCTRL_PIN(98, "IMGCLKOUT_4"), + /* GPP_D */ + PINCTRL_PIN(99, "ISH_GP_0"), + PINCTRL_PIN(100, "ISH_GP_1"), + PINCTRL_PIN(101, "ISH_GP_2"), + PINCTRL_PIN(102, "ISH_GP_3"), + PINCTRL_PIN(103, "IMGCLKOUT_0"), + PINCTRL_PIN(104, "SRCCLKREQB_0"), + PINCTRL_PIN(105, "SRCCLKREQB_1"), + PINCTRL_PIN(106, "SRCCLKREQB_2"), + PINCTRL_PIN(107, "SRCCLKREQB_3"), + PINCTRL_PIN(108, "ISH_SPI_CSB"), + PINCTRL_PIN(109, "ISH_SPI_CLK"), + PINCTRL_PIN(110, "ISH_SPI_MISO"), + PINCTRL_PIN(111, "ISH_SPI_MOSI"), + PINCTRL_PIN(112, "ISH_UART0_RXD"), + PINCTRL_PIN(113, "ISH_UART0_TXD"), + PINCTRL_PIN(114, "ISH_UART0_RTSB"), + PINCTRL_PIN(115, "ISH_UART0_CTSB"), + PINCTRL_PIN(116, "ISH_GP_4"), + PINCTRL_PIN(117, "ISH_GP_5"), + PINCTRL_PIN(118, "I2S_MCLK1_OUT"), + PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"), + /* GPP_U */ + PINCTRL_PIN(120, "UART3_RXD"), + PINCTRL_PIN(121, "UART3_TXD"), + PINCTRL_PIN(122, "UART3_RTSB"), + PINCTRL_PIN(123, "UART3_CTSB"), + PINCTRL_PIN(124, "GSPI3_CS0B"), + PINCTRL_PIN(125, "GSPI3_CLK"), + PINCTRL_PIN(126, "GSPI3_MISO"), + PINCTRL_PIN(127, "GSPI3_MOSI"), + PINCTRL_PIN(128, "GSPI4_CS0B"), + PINCTRL_PIN(129, "GSPI4_CLK"), + PINCTRL_PIN(130, "GSPI4_MISO"), + PINCTRL_PIN(131, "GSPI4_MOSI"), + PINCTRL_PIN(132, "GSPI5_CS0B"), + PINCTRL_PIN(133, "GSPI5_CLK"), + PINCTRL_PIN(134, "GSPI5_MISO"), + PINCTRL_PIN(135, "GSPI5_MOSI"), + PINCTRL_PIN(136, "GSPI6_CS0B"), + PINCTRL_PIN(137, "GSPI6_CLK"), + PINCTRL_PIN(138, "GSPI6_MISO"), + PINCTRL_PIN(139, "GSPI6_MOSI"), + PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"), + PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"), + PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"), + PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(144, "CNV_BTEN"), + PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(155, "vUART0_TXD"), + PINCTRL_PIN(156, "vUART0_RXD"), + PINCTRL_PIN(157, "vUART0_CTS_B"), + PINCTRL_PIN(158, "vUART0_RTS_B"), + PINCTRL_PIN(159, "vISH_UART0_TXD"), + PINCTRL_PIN(160, "vISH_UART0_RXD"), + PINCTRL_PIN(161, "vISH_UART0_CTS_B"), + PINCTRL_PIN(162, "vISH_UART0_RTS_B"), + PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(167, "vI2S2_SCLK"), + PINCTRL_PIN(168, "vI2S2_SFRM"), + PINCTRL_PIN(169, "vI2S2_TXD"), + PINCTRL_PIN(170, "vI2S2_RXD"), + /* GPP_C */ + PINCTRL_PIN(171, "SMBCLK"), + PINCTRL_PIN(172, "SMBDATA"), + PINCTRL_PIN(173, "SMBALERTB"), + PINCTRL_PIN(174, "SML0CLK"), + PINCTRL_PIN(175, "SML0DATA"), + PINCTRL_PIN(176, "SML0ALERTB"), + PINCTRL_PIN(177, "SML1CLK"), + PINCTRL_PIN(178, "SML1DATA"), + PINCTRL_PIN(179, "UART0_RXD"), + PINCTRL_PIN(180, "UART0_TXD"), + PINCTRL_PIN(181, "UART0_RTSB"), + PINCTRL_PIN(182, "UART0_CTSB"), + PINCTRL_PIN(183, "UART1_RXD"), + PINCTRL_PIN(184, "UART1_TXD"), + PINCTRL_PIN(185, "UART1_RTSB"), + PINCTRL_PIN(186, "UART1_CTSB"), + PINCTRL_PIN(187, "I2C0_SDA"), + PINCTRL_PIN(188, "I2C0_SCL"), + PINCTRL_PIN(189, "I2C1_SDA"), + PINCTRL_PIN(190, "I2C1_SCL"), + PINCTRL_PIN(191, "UART2_RXD"), + PINCTRL_PIN(192, "UART2_TXD"), + PINCTRL_PIN(193, "UART2_RTSB"), + PINCTRL_PIN(194, "UART2_CTSB"), + /* GPP_F */ + PINCTRL_PIN(195, "CNV_BRI_DT"), + PINCTRL_PIN(196, "CNV_BRI_RSP"), + PINCTRL_PIN(197, "CNV_RGI_DT"), + PINCTRL_PIN(198, "CNV_RGI_RSP"), + PINCTRL_PIN(199, "CNV_RF_RESET_B"), + PINCTRL_PIN(200, "GPPC_F_5"), + PINCTRL_PIN(201, "CNV_PA_BLANKING"), + PINCTRL_PIN(202, "GPPC_F_7"), + PINCTRL_PIN(203, "I2S_MCLK2_INOUT"), + PINCTRL_PIN(204, "BOOTMPC"), + PINCTRL_PIN(205, "GPPC_F_10"), + PINCTRL_PIN(206, "GPPC_F_11"), + PINCTRL_PIN(207, "GSXDOUT"), + PINCTRL_PIN(208, "GSXSLOAD"), + PINCTRL_PIN(209, "GSXDIN"), + PINCTRL_PIN(210, "GSXSRESETB"), + PINCTRL_PIN(211, "GSXCLK"), + PINCTRL_PIN(212, "GMII_MDC"), + PINCTRL_PIN(213, "GMII_MDIO"), + PINCTRL_PIN(214, "SRCCLKREQB_6"), + PINCTRL_PIN(215, "EXT_PWR_GATEB"), + PINCTRL_PIN(216, "EXT_PWR_GATE2B"), + PINCTRL_PIN(217, "VNN_CTRL"), + PINCTRL_PIN(218, "V1P05_CTRL"), + PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"), + /* HVCMOS */ + PINCTRL_PIN(220, "L_BKLTEN"), + PINCTRL_PIN(221, "L_BKLTCTL"), + PINCTRL_PIN(222, "L_VDDEN"), + PINCTRL_PIN(223, "SYS_PWROK"), + PINCTRL_PIN(224, "SYS_RESETB"), + PINCTRL_PIN(225, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(226, "SATAXPCIE_0"), + PINCTRL_PIN(227, "SPI1_IO_2"), + PINCTRL_PIN(228, "SPI1_IO_3"), + PINCTRL_PIN(229, "CPU_GP_0"), + PINCTRL_PIN(230, "SATA_DEVSLP_0"), + PINCTRL_PIN(231, "SATA_DEVSLP_1"), + PINCTRL_PIN(232, "GPPC_E_6"), + PINCTRL_PIN(233, "CPU_GP_1"), + PINCTRL_PIN(234, "SPI1_CS1B"), + PINCTRL_PIN(235, "USB2_OCB_0"), + PINCTRL_PIN(236, "SPI1_CSB"), + PINCTRL_PIN(237, "SPI1_CLK"), + PINCTRL_PIN(238, "SPI1_MISO_IO_1"), + PINCTRL_PIN(239, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(240, "DDSP_HPD_A"), + PINCTRL_PIN(241, "ISH_GP_6"), + PINCTRL_PIN(242, "ISH_GP_7"), + PINCTRL_PIN(243, "GPPC_E_17"), + PINCTRL_PIN(244, "DDP1_CTRLCLK"), + PINCTRL_PIN(245, "DDP1_CTRLDATA"), + PINCTRL_PIN(246, "DDP2_CTRLCLK"), + PINCTRL_PIN(247, "DDP2_CTRLDATA"), + PINCTRL_PIN(248, "DDPA_CTRLCLK"), + PINCTRL_PIN(249, "DDPA_CTRLDATA"), + PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"), + /* JTAG */ + PINCTRL_PIN(251, "JTAG_TDO"), + PINCTRL_PIN(252, "JTAGX"), + PINCTRL_PIN(253, "PRDYB"), + PINCTRL_PIN(254, "PREQB"), + PINCTRL_PIN(255, "CPU_TRSTB"), + PINCTRL_PIN(256, "JTAG_TDI"), + PINCTRL_PIN(257, "JTAG_TMS"), + PINCTRL_PIN(258, "JTAG_TCK"), + PINCTRL_PIN(259, "DBG_PMODE"), + /* GPP_R */ + PINCTRL_PIN(260, "HDA_BCLK"), + PINCTRL_PIN(261, "HDA_SYNC"), + PINCTRL_PIN(262, "HDA_SDO"), + PINCTRL_PIN(263, "HDA_SDI_0"), + PINCTRL_PIN(264, "HDA_RSTB"), + PINCTRL_PIN(265, "HDA_SDI_1"), + PINCTRL_PIN(266, "GPP_R_6"), + PINCTRL_PIN(267, "GPP_R_7"), + /* SPI */ + PINCTRL_PIN(268, "SPI0_IO_2"), + PINCTRL_PIN(269, "SPI0_IO_3"), + PINCTRL_PIN(270, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(271, "SPI0_MISO_IO_1"), + PINCTRL_PIN(272, "SPI0_TPM_CSB"), + PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(275, "SPI0_CLK"), + PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), }; static const struct intel_padgroup tgllp_community0_gpps[] = { - TGL_GPP(0, 0, 25), /* GPP_B */ - TGL_GPP(1, 26, 41), /* GPP_T */ - TGL_GPP(2, 42, 66), /* GPP_A */ -}; - -static const struct intel_community tgllp_community0[] = { - TGL_COMMUNITY(0, 66, tgllp_community0_gpps), -}; - -static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = { - .uid = "0", - .pins = tgllp_community0_pins, - .npins = ARRAY_SIZE(tgllp_community0_pins), - .communities = tgllp_community0, - .ncommunities = ARRAY_SIZE(tgllp_community0), -}; - -static const struct pinctrl_pin_desc tgllp_community1_pins[] = { - /* GPP_S */ - PINCTRL_PIN(0, "SNDW0_CLK"), - PINCTRL_PIN(1, "SNDW0_DATA"), - PINCTRL_PIN(2, "SNDW1_CLK"), - PINCTRL_PIN(3, "SNDW1_DATA"), - PINCTRL_PIN(4, "SNDW2_CLK"), - PINCTRL_PIN(5, "SNDW2_DATA"), - PINCTRL_PIN(6, "SNDW3_CLK"), - PINCTRL_PIN(7, "SNDW3_DATA"), - /* GPP_H */ - PINCTRL_PIN(8, "GPPC_H_0"), - PINCTRL_PIN(9, "GPPC_H_1"), - PINCTRL_PIN(10, "GPPC_H_2"), - PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"), - PINCTRL_PIN(12, "I2C2_SDA"), - PINCTRL_PIN(13, "I2C2_SCL"), - PINCTRL_PIN(14, "I2C3_SDA"), - PINCTRL_PIN(15, "I2C3_SCL"), - PINCTRL_PIN(16, "I2C4_SDA"), - PINCTRL_PIN(17, "I2C4_SCL"), - PINCTRL_PIN(18, "SRCCLKREQB_4"), - PINCTRL_PIN(19, "SRCCLKREQB_5"), - PINCTRL_PIN(20, "M2_SKT2_CFG_0"), - PINCTRL_PIN(21, "M2_SKT2_CFG_1"), - PINCTRL_PIN(22, "M2_SKT2_CFG_2"), - PINCTRL_PIN(23, "M2_SKT2_CFG_3"), - PINCTRL_PIN(24, "DDPB_CTRLCLK"), - PINCTRL_PIN(25, "DDPB_CTRLDATA"), - PINCTRL_PIN(26, "CPU_C10_GATEB"), - PINCTRL_PIN(27, "TIME_SYNC_0"), - PINCTRL_PIN(28, "IMGCLKOUT_1"), - PINCTRL_PIN(29, "IMGCLKOUT_2"), - PINCTRL_PIN(30, "IMGCLKOUT_3"), - PINCTRL_PIN(31, "IMGCLKOUT_4"), - /* GPP_D */ - PINCTRL_PIN(32, "ISH_GP_0"), - PINCTRL_PIN(33, "ISH_GP_1"), - PINCTRL_PIN(34, "ISH_GP_2"), - PINCTRL_PIN(35, "ISH_GP_3"), - PINCTRL_PIN(36, "IMGCLKOUT_0"), - PINCTRL_PIN(37, "SRCCLKREQB_0"), - PINCTRL_PIN(38, "SRCCLKREQB_1"), - PINCTRL_PIN(39, "SRCCLKREQB_2"), - PINCTRL_PIN(40, "SRCCLKREQB_3"), - PINCTRL_PIN(41, "ISH_SPI_CSB"), - PINCTRL_PIN(42, "ISH_SPI_CLK"), - PINCTRL_PIN(43, "ISH_SPI_MISO"), - PINCTRL_PIN(44, "ISH_SPI_MOSI"), - PINCTRL_PIN(45, "ISH_UART0_RXD"), - PINCTRL_PIN(46, "ISH_UART0_TXD"), - PINCTRL_PIN(47, "ISH_UART0_RTSB"), - PINCTRL_PIN(48, "ISH_UART0_CTSB"), - PINCTRL_PIN(49, "ISH_GP_4"), - PINCTRL_PIN(50, "ISH_GP_5"), - PINCTRL_PIN(51, "I2S_MCLK1_OUT"), - PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"), - /* GPP_U */ - PINCTRL_PIN(53, "UART3_RXD"), - PINCTRL_PIN(54, "UART3_TXD"), - PINCTRL_PIN(55, "UART3_RTSB"), - PINCTRL_PIN(56, "UART3_CTSB"), - PINCTRL_PIN(57, "GSPI3_CS0B"), - PINCTRL_PIN(58, "GSPI3_CLK"), - PINCTRL_PIN(59, "GSPI3_MISO"), - PINCTRL_PIN(60, "GSPI3_MOSI"), - PINCTRL_PIN(61, "GSPI4_CS0B"), - PINCTRL_PIN(62, "GSPI4_CLK"), - PINCTRL_PIN(63, "GSPI4_MISO"), - PINCTRL_PIN(64, "GSPI4_MOSI"), - PINCTRL_PIN(65, "GSPI5_CS0B"), - PINCTRL_PIN(66, "GSPI5_CLK"), - PINCTRL_PIN(67, "GSPI5_MISO"), - PINCTRL_PIN(68, "GSPI5_MOSI"), - PINCTRL_PIN(69, "GSPI6_CS0B"), - PINCTRL_PIN(70, "GSPI6_CLK"), - PINCTRL_PIN(71, "GSPI6_MISO"), - PINCTRL_PIN(72, "GSPI6_MOSI"), - PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"), - PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"), - PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"), - PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"), - /* vGPIO */ - PINCTRL_PIN(77, "CNV_BTEN"), - PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"), - PINCTRL_PIN(79, "CNV_BT_IF_SELECT"), - PINCTRL_PIN(80, "vCNV_BT_UART_TXD"), - PINCTRL_PIN(81, "vCNV_BT_UART_RXD"), - PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"), - PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"), - PINCTRL_PIN(84, "vCNV_MFUART1_TXD"), - PINCTRL_PIN(85, "vCNV_MFUART1_RXD"), - PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"), - PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"), - PINCTRL_PIN(88, "vUART0_TXD"), - PINCTRL_PIN(89, "vUART0_RXD"), - PINCTRL_PIN(90, "vUART0_CTS_B"), - PINCTRL_PIN(91, "vUART0_RTS_B"), - PINCTRL_PIN(92, "vISH_UART0_TXD"), - PINCTRL_PIN(93, "vISH_UART0_RXD"), - PINCTRL_PIN(94, "vISH_UART0_CTS_B"), - PINCTRL_PIN(95, "vISH_UART0_RTS_B"), - PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"), - PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"), - PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"), - PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"), - PINCTRL_PIN(100, "vI2S2_SCLK"), - PINCTRL_PIN(101, "vI2S2_SFRM"), - PINCTRL_PIN(102, "vI2S2_TXD"), - PINCTRL_PIN(103, "vI2S2_RXD"), + TGL_GPP(0, 0, 25, 0), /* GPP_B */ + TGL_GPP(1, 26, 41, 32), /* GPP_T */ + TGL_GPP(2, 42, 66, 64), /* GPP_A */ }; static const struct intel_padgroup tgllp_community1_gpps[] = { - TGL_GPP(0, 0, 7), /* GPP_S */ - TGL_GPP(1, 8, 31), /* GPP_H */ - TGL_GPP(2, 32, 52), /* GPP_D */ - TGL_GPP(3, 53, 76), /* GPP_U */ - TGL_GPP(4, 77, 103), /* vGPIO */ -}; - -static const struct intel_community tgllp_community1[] = { - TGL_COMMUNITY(0, 103, tgllp_community1_gpps), -}; - -static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = { - .uid = "1", - .pins = tgllp_community1_pins, - .npins = ARRAY_SIZE(tgllp_community1_pins), - .communities = tgllp_community1, - .ncommunities = ARRAY_SIZE(tgllp_community1), -}; - -static const struct pinctrl_pin_desc tgllp_community4_pins[] = { - /* GPP_C */ - PINCTRL_PIN(0, "SMBCLK"), - PINCTRL_PIN(1, "SMBDATA"), - PINCTRL_PIN(2, "SMBALERTB"), - PINCTRL_PIN(3, "SML0CLK"), - PINCTRL_PIN(4, "SML0DATA"), - PINCTRL_PIN(5, "SML0ALERTB"), - PINCTRL_PIN(6, "SML1CLK"), - PINCTRL_PIN(7, "SML1DATA"), - PINCTRL_PIN(8, "UART0_RXD"), - PINCTRL_PIN(9, "UART0_TXD"), - PINCTRL_PIN(10, "UART0_RTSB"), - PINCTRL_PIN(11, "UART0_CTSB"), - PINCTRL_PIN(12, "UART1_RXD"), - PINCTRL_PIN(13, "UART1_TXD"), - PINCTRL_PIN(14, "UART1_RTSB"), - PINCTRL_PIN(15, "UART1_CTSB"), - PINCTRL_PIN(16, "I2C0_SDA"), - PINCTRL_PIN(17, "I2C0_SCL"), - PINCTRL_PIN(18, "I2C1_SDA"), - PINCTRL_PIN(19, "I2C1_SCL"), - PINCTRL_PIN(20, "UART2_RXD"), - PINCTRL_PIN(21, "UART2_TXD"), - PINCTRL_PIN(22, "UART2_RTSB"), - PINCTRL_PIN(23, "UART2_CTSB"), - /* GPP_F */ - PINCTRL_PIN(24, "CNV_BRI_DT"), - PINCTRL_PIN(25, "CNV_BRI_RSP"), - PINCTRL_PIN(26, "CNV_RGI_DT"), - PINCTRL_PIN(27, "CNV_RGI_RSP"), - PINCTRL_PIN(28, "CNV_RF_RESET_B"), - PINCTRL_PIN(29, "GPPC_F_5"), - PINCTRL_PIN(30, "CNV_PA_BLANKING"), - PINCTRL_PIN(31, "GPPC_F_7"), - PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), - PINCTRL_PIN(33, "BOOTMPC"), - PINCTRL_PIN(34, "GPPC_F_10"), - PINCTRL_PIN(35, "GPPC_F_11"), - PINCTRL_PIN(36, "GSXDOUT"), - PINCTRL_PIN(37, "GSXSLOAD"), - PINCTRL_PIN(38, "GSXDIN"), - PINCTRL_PIN(39, "GSXSRESETB"), - PINCTRL_PIN(40, "GSXCLK"), - PINCTRL_PIN(41, "GMII_MDC"), - PINCTRL_PIN(42, "GMII_MDIO"), - PINCTRL_PIN(43, "SRCCLKREQB_6"), - PINCTRL_PIN(44, "EXT_PWR_GATEB"), - PINCTRL_PIN(45, "EXT_PWR_GATE2B"), - PINCTRL_PIN(46, "VNN_CTRL"), - PINCTRL_PIN(47, "V1P05_CTRL"), - PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), - /* HVCMOS */ - PINCTRL_PIN(49, "L_BKLTEN"), - PINCTRL_PIN(50, "L_BKLTCTL"), - PINCTRL_PIN(51, "L_VDDEN"), - PINCTRL_PIN(52, "SYS_PWROK"), - PINCTRL_PIN(53, "SYS_RESETB"), - PINCTRL_PIN(54, "MLK_RSTB"), - /* GPP_E */ - PINCTRL_PIN(55, "SATAXPCIE_0"), - PINCTRL_PIN(56, "SPI1_IO_2"), - PINCTRL_PIN(57, "SPI1_IO_3"), - PINCTRL_PIN(58, "CPU_GP_0"), - PINCTRL_PIN(59, "SATA_DEVSLP_0"), - PINCTRL_PIN(60, "SATA_DEVSLP_1"), - PINCTRL_PIN(61, "GPPC_E_6"), - PINCTRL_PIN(62, "CPU_GP_1"), - PINCTRL_PIN(63, "SPI1_CS1B"), - PINCTRL_PIN(64, "USB2_OCB_0"), - PINCTRL_PIN(65, "SPI1_CSB"), - PINCTRL_PIN(66, "SPI1_CLK"), - PINCTRL_PIN(67, "SPI1_MISO_IO_1"), - PINCTRL_PIN(68, "SPI1_MOSI_IO_0"), - PINCTRL_PIN(69, "DDSP_HPD_A"), - PINCTRL_PIN(70, "ISH_GP_6"), - PINCTRL_PIN(71, "ISH_GP_7"), - PINCTRL_PIN(72, "GPPC_E_17"), - PINCTRL_PIN(73, "DDP1_CTRLCLK"), - PINCTRL_PIN(74, "DDP1_CTRLDATA"), - PINCTRL_PIN(75, "DDP2_CTRLCLK"), - PINCTRL_PIN(76, "DDP2_CTRLDATA"), - PINCTRL_PIN(77, "DDPA_CTRLCLK"), - PINCTRL_PIN(78, "DDPA_CTRLDATA"), - PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), - /* JTAG */ - PINCTRL_PIN(80, "JTAG_TDO"), - PINCTRL_PIN(81, "JTAGX"), - PINCTRL_PIN(82, "PRDYB"), - PINCTRL_PIN(83, "PREQB"), - PINCTRL_PIN(84, "CPU_TRSTB"), - PINCTRL_PIN(85, "JTAG_TDI"), - PINCTRL_PIN(86, "JTAG_TMS"), - PINCTRL_PIN(87, "JTAG_TCK"), - PINCTRL_PIN(88, "DBG_PMODE"), + TGL_GPP(0, 67, 74, 96), /* GPP_S */ + TGL_GPP(1, 75, 98, 128), /* GPP_H */ + TGL_GPP(2, 99, 119, 160), /* GPP_D */ + TGL_GPP(3, 120, 143, 192), /* GPP_U */ + TGL_GPP(4, 144, 170, 224), /* vGPIO */ }; static const struct intel_padgroup tgllp_community4_gpps[] = { - TGL_GPP(0, 0, 23), /* GPP_C */ - TGL_GPP(1, 24, 48), /* GPP_F */ - TGL_GPP(2, 49, 54), /* HVCMOS */ - TGL_GPP(3, 55, 79), /* GPP_E */ - TGL_GPP(4, 80, 88), /* JTAG */ -}; - -static const struct intel_community tgllp_community4[] = { - TGL_COMMUNITY(0, 88, tgllp_community4_gpps), -}; - -static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = { - .uid = "4", - .pins = tgllp_community4_pins, - .npins = ARRAY_SIZE(tgllp_community4_pins), - .communities = tgllp_community4, - .ncommunities = ARRAY_SIZE(tgllp_community4), -}; - -static const struct pinctrl_pin_desc tgllp_community5_pins[] = { - /* GPP_R */ - PINCTRL_PIN(0, "HDA_BCLK"), - PINCTRL_PIN(1, "HDA_SYNC"), - PINCTRL_PIN(2, "HDA_SDO"), - PINCTRL_PIN(3, "HDA_SDI_0"), - PINCTRL_PIN(4, "HDA_RSTB"), - PINCTRL_PIN(5, "HDA_SDI_1"), - PINCTRL_PIN(6, "GPP_R_6"), - PINCTRL_PIN(7, "GPP_R_7"), - /* SPI */ - PINCTRL_PIN(8, "SPI0_IO_2"), - PINCTRL_PIN(9, "SPI0_IO_3"), - PINCTRL_PIN(10, "SPI0_MOSI_IO_0"), - PINCTRL_PIN(11, "SPI0_MISO_IO_1"), - PINCTRL_PIN(12, "SPI0_TPM_CSB"), - PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"), - PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"), - PINCTRL_PIN(15, "SPI0_CLK"), - PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"), + TGL_GPP(0, 171, 194, 256), /* GPP_C */ + TGL_GPP(1, 195, 219, 288), /* GPP_F */ + TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */ + TGL_GPP(3, 226, 250, 320), /* GPP_E */ + TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */ }; static const struct intel_padgroup tgllp_community5_gpps[] = { - TGL_GPP(0, 0, 7), /* GPP_R */ - TGL_GPP(1, 8, 16), /* SPI */ + TGL_GPP(0, 260, 267, 352), /* GPP_R */ + TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */ }; -static const struct intel_community tgllp_community5[] = { - TGL_COMMUNITY(0, 16, tgllp_community5_gpps), +static const struct intel_community tgllp_communities[] = { + TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps), + TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps), + TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps), + TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps), }; -static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = { - .uid = "5", - .pins = tgllp_community5_pins, - .npins = ARRAY_SIZE(tgllp_community5_pins), - .communities = tgllp_community5, - .ncommunities = ARRAY_SIZE(tgllp_community5), -}; - -static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = { - &tgllp_community0_soc_data, - &tgllp_community1_soc_data, - &tgllp_community4_soc_data, - &tgllp_community5_soc_data, - NULL +static const struct intel_pinctrl_soc_data tgllp_soc_data = { + .pins = tgllp_pins, + .npins = ARRAY_SIZE(tgllp_pins), + .communities = tgllp_communities, + .ncommunities = ARRAY_SIZE(tgllp_communities), }; static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { - { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array }, + { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); @@ -438,7 +391,7 @@ MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops); static struct platform_driver tgl_pinctrl_driver = { - .probe = intel_pinctrl_probe_by_uid, + .probe = intel_pinctrl_probe_by_hid, .driver = { .name = "tigerlake-pinctrl", .acpi_match_table = tgl_pinctrl_acpi_match, From 364efd0db7c336c6defc885e077e73e83daca999 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 15 Jan 2020 09:39:06 +0800 Subject: [PATCH 94/99] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Add binding doc for i.MX8MP pinctrl driver. Signed-off-by: Anson Huang Reviewed-by: Abel Vesa Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1579052348-32167-1-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx8mp-pinctrl.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml new file mode 100644 index 000000000000..2e31e120395e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MP IOMUX Controller + +maintainers: + - Anson Huang + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8mp-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart2: uart2grp { + fsl,pins = < + 0x228 0x488 0x5F0 0x0 0x6 0x49 + 0x228 0x488 0x000 0x0 0x0 0x49 + >; + }; + }; + +... From eec6d97d6da400226529f4748fb8998bb69a5bbf Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 15 Jan 2020 09:39:07 +0800 Subject: [PATCH 95/99] pinctrl: freescale: Add i.MX8MP pinctrl driver support Add the pinctrl driver support for i.MX8MP. Signed-off-by: Anson Huang Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/1579052348-32167-2-git-send-email-Anson.Huang@nxp.com Reviewed-by: Fabio Estevam Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx8mp.c | 345 +++++++++++++++++++++ 3 files changed, 353 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mp.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 3ea9ce3e0cd9..de775a85a51e 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -137,6 +137,13 @@ config PINCTRL_IMX8MN help Say Y here to enable the imx8mn pinctrl driver +config PINCTRL_IMX8MP + bool "IMX8MP pinctrl driver" + depends on ARCH_MXC && ARM64 + select PINCTRL_IMX + help + Say Y here to enable the imx8mp pinctrl driver + config PINCTRL_IMX8MQ bool "IMX8MQ pinctrl driver" depends on ARCH_MXC && ARM64 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 78e9140c13e3..0ebd3af21e4d 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o +obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mp.c b/drivers/pinctrl/freescale/pinctrl-imx8mp.c new file mode 100644 index 000000000000..e3f644c2ec13 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8mp.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx8mp_pads { + MX8MP_IOMUXC_RESERVE0 = 0, + MX8MP_IOMUXC_RESERVE1 = 1, + MX8MP_IOMUXC_RESERVE2 = 2, + MX8MP_IOMUXC_RESERVE3 = 3, + MX8MP_IOMUXC_RESERVE4 = 4, + MX8MP_IOMUXC_GPIO1_IO00 = 5, + MX8MP_IOMUXC_GPIO1_IO01 = 6, + MX8MP_IOMUXC_GPIO1_IO02 = 7, + MX8MP_IOMUXC_GPIO1_IO03 = 8, + MX8MP_IOMUXC_GPIO1_IO04 = 9, + MX8MP_IOMUXC_GPIO1_IO05 = 10, + MX8MP_IOMUXC_GPIO1_IO06 = 11, + MX8MP_IOMUXC_GPIO1_IO07 = 12, + MX8MP_IOMUXC_GPIO1_IO08 = 13, + MX8MP_IOMUXC_GPIO1_IO09 = 14, + MX8MP_IOMUXC_GPIO1_IO10 = 15, + MX8MP_IOMUXC_GPIO1_IO11 = 16, + MX8MP_IOMUXC_GPIO1_IO12 = 17, + MX8MP_IOMUXC_GPIO1_IO13 = 18, + MX8MP_IOMUXC_GPIO1_IO14 = 19, + MX8MP_IOMUXC_GPIO1_IO15 = 20, + MX8MP_IOMUXC_ENET_MDC = 21, + MX8MP_IOMUXC_ENET_MDIO = 22, + MX8MP_IOMUXC_ENET_TD3 = 23, + MX8MP_IOMUXC_ENET_TD2 = 24, + MX8MP_IOMUXC_ENET_TD1 = 25, + MX8MP_IOMUXC_ENET_TD0 = 26, + MX8MP_IOMUXC_ENET_TX_CTL = 27, + MX8MP_IOMUXC_ENET_TXC = 28, + MX8MP_IOMUXC_ENET_RX_CTL = 29, + MX8MP_IOMUXC_ENET_RXC = 30, + MX8MP_IOMUXC_ENET_RD0 = 31, + MX8MP_IOMUXC_ENET_RD1 = 32, + MX8MP_IOMUXC_ENET_RD2 = 33, + MX8MP_IOMUXC_ENET_RD3 = 34, + MX8MP_IOMUXC_SD1_CLK = 35, + MX8MP_IOMUXC_SD1_CMD = 36, + MX8MP_IOMUXC_SD1_DATA0 = 37, + MX8MP_IOMUXC_SD1_DATA1 = 38, + MX8MP_IOMUXC_SD1_DATA2 = 39, + MX8MP_IOMUXC_SD1_DATA3 = 40, + MX8MP_IOMUXC_SD1_DATA4 = 41, + MX8MP_IOMUXC_SD1_DATA5 = 42, + MX8MP_IOMUXC_SD1_DATA6 = 43, + MX8MP_IOMUXC_SD1_DATA7 = 44, + MX8MP_IOMUXC_SD1_RESET_B = 45, + MX8MP_IOMUXC_SD1_STROBE = 46, + MX8MP_IOMUXC_SD2_CD_B = 47, + MX8MP_IOMUXC_SD2_CLK = 48, + MX8MP_IOMUXC_SD2_CMD = 49, + MX8MP_IOMUXC_SD2_DATA0 = 50, + MX8MP_IOMUXC_SD2_DATA1 = 51, + MX8MP_IOMUXC_SD2_DATA2 = 52, + MX8MP_IOMUXC_SD2_DATA3 = 53, + MX8MP_IOMUXC_SD2_RESET_B = 54, + MX8MP_IOMUXC_SD2_WP = 55, + MX8MP_IOMUXC_NAND_ALE = 56, + MX8MP_IOMUXC_NAND_CE0_B = 57, + MX8MP_IOMUXC_NAND_CE1_B = 58, + MX8MP_IOMUXC_NAND_CE2_B = 59, + MX8MP_IOMUXC_NAND_CE3_B = 60, + MX8MP_IOMUXC_NAND_CLE = 61, + MX8MP_IOMUXC_NAND_DATA00 = 62, + MX8MP_IOMUXC_NAND_DATA01 = 63, + MX8MP_IOMUXC_NAND_DATA02 = 64, + MX8MP_IOMUXC_NAND_DATA03 = 65, + MX8MP_IOMUXC_NAND_DATA04 = 66, + MX8MP_IOMUXC_NAND_DATA05 = 67, + MX8MP_IOMUXC_NAND_DATA06 = 68, + MX8MP_IOMUXC_NAND_DATA07 = 69, + MX8MP_IOMUXC_NAND_DQS = 70, + MX8MP_IOMUXC_NAND_RE_B = 71, + MX8MP_IOMUXC_NAND_READY_B = 72, + MX8MP_IOMUXC_NAND_WE_B = 73, + MX8MP_IOMUXC_NAND_WP_B = 74, + MX8MP_IOMUXC_SAI5_RXFS = 75, + MX8MP_IOMUXC_SAI5_RXC = 76, + MX8MP_IOMUXC_SAI5_RXD0 = 77, + MX8MP_IOMUXC_SAI5_RXD1 = 78, + MX8MP_IOMUXC_SAI5_RXD2 = 79, + MX8MP_IOMUXC_SAI5_RXD3 = 80, + MX8MP_IOMUXC_SAI5_MCLK = 81, + MX8MP_IOMUXC_SAI1_RXFS = 82, + MX8MP_IOMUXC_SAI1_RXC = 83, + MX8MP_IOMUXC_SAI1_RXD0 = 84, + MX8MP_IOMUXC_SAI1_RXD1 = 85, + MX8MP_IOMUXC_SAI1_RXD2 = 86, + MX8MP_IOMUXC_SAI1_RXD3 = 87, + MX8MP_IOMUXC_SAI1_RXD4 = 88, + MX8MP_IOMUXC_SAI1_RXD5 = 89, + MX8MP_IOMUXC_SAI1_RXD6 = 90, + MX8MP_IOMUXC_SAI1_RXD7 = 91, + MX8MP_IOMUXC_SAI1_TXFS = 92, + MX8MP_IOMUXC_SAI1_TXC = 93, + MX8MP_IOMUXC_SAI1_TXD0 = 94, + MX8MP_IOMUXC_SAI1_TXD1 = 95, + MX8MP_IOMUXC_SAI1_TXD2 = 96, + MX8MP_IOMUXC_SAI1_TXD3 = 97, + MX8MP_IOMUXC_SAI1_TXD4 = 98, + MX8MP_IOMUXC_SAI1_TXD5 = 99, + MX8MP_IOMUXC_SAI1_TXD6 = 100, + MX8MP_IOMUXC_SAI1_TXD7 = 101, + MX8MP_IOMUXC_SAI1_MCLK = 102, + MX8MP_IOMUXC_SAI2_RXFS = 103, + MX8MP_IOMUXC_SAI2_RXC = 104, + MX8MP_IOMUXC_SAI2_RXD0 = 105, + MX8MP_IOMUXC_SAI2_TXFS = 106, + MX8MP_IOMUXC_SAI2_TXC = 107, + MX8MP_IOMUXC_SAI2_TXD0 = 108, + MX8MP_IOMUXC_SAI2_MCLK = 109, + MX8MP_IOMUXC_SAI3_RXFS = 110, + MX8MP_IOMUXC_SAI3_RXC = 111, + MX8MP_IOMUXC_SAI3_RXD = 112, + MX8MP_IOMUXC_SAI3_TXFS = 113, + MX8MP_IOMUXC_SAI3_TXC = 114, + MX8MP_IOMUXC_SAI3_TXD = 115, + MX8MP_IOMUXC_SAI3_MCLK = 116, + MX8MP_IOMUXC_SPDIF_TX = 117, + MX8MP_IOMUXC_SPDIF_RX = 118, + MX8MP_IOMUXC_SPDIF_EXT_CLK = 119, + MX8MP_IOMUXC_ECSPI1_SCLK = 120, + MX8MP_IOMUXC_ECSPI1_MOSI = 121, + MX8MP_IOMUXC_ECSPI1_MISO = 122, + MX8MP_IOMUXC_ECSPI1_SS0 = 123, + MX8MP_IOMUXC_ECSPI2_SCLK = 124, + MX8MP_IOMUXC_ECSPI2_MOSI = 125, + MX8MP_IOMUXC_ECSPI2_MISO = 126, + MX8MP_IOMUXC_ECSPI2_SS0 = 127, + MX8MP_IOMUXC_I2C1_SCL = 128, + MX8MP_IOMUXC_I2C1_SDA = 129, + MX8MP_IOMUXC_I2C2_SCL = 130, + MX8MP_IOMUXC_I2C2_SDA = 131, + MX8MP_IOMUXC_I2C3_SCL = 132, + MX8MP_IOMUXC_I2C3_SDA = 133, + MX8MP_IOMUXC_I2C4_SCL = 134, + MX8MP_IOMUXC_I2C4_SDA = 135, + MX8MP_IOMUXC_UART1_RXD = 136, + MX8MP_IOMUXC_UART1_TXD = 137, + MX8MP_IOMUXC_UART2_RXD = 138, + MX8MP_IOMUXC_UART2_TXD = 139, + MX8MP_IOMUXC_UART3_RXD = 140, + MX8MP_IOMUXC_UART3_TXD = 141, + MX8MP_IOMUXC_UART4_RXD = 142, + MX8MP_IOMUXC_UART4_TXD = 143, + MX8MP_IOMUXC_HDMI_DDC_SCL = 144, + MX8MP_IOMUXC_HDMI_DDC_SDA = 145, + MX8MP_IOMUXC_HDMI_CEC = 146, + MX8MP_IOMUXC_HDMI_HPD = 147, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx8mp_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO00), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO01), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO02), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO03), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO04), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO05), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO06), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO07), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO08), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO09), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO10), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO11), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO12), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO13), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO14), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO15), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDIO), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TX_CTL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RX_CTL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_RESET_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_WP), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_ALE), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE0_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE1_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE2_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE3_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CLE), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA00), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA01), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA02), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA03), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA04), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA05), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA06), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA07), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DQS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_RE_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_READY_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WE_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WP_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD5), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD6), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD7), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD5), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD6), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD7), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_TX), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_RX), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_CEC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_HPD), +}; + +static const struct imx_pinctrl_soc_info imx8mp_pinctrl_info = { + .pins = imx8mp_pinctrl_pads, + .npins = ARRAY_SIZE(imx8mp_pinctrl_pads), + .gpr_compatible = "fsl,imx8mp-iomuxc-gpr", +}; + +static const struct of_device_id imx8mp_pinctrl_of_match[] = { + { .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, }, + { /* sentinel */ } +}; + +static int imx8mp_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx8mp_pinctrl_info); +} + +static struct platform_driver imx8mp_pinctrl_driver = { + .driver = { + .name = "imx8mp-pinctrl", + .of_match_table = of_match_ptr(imx8mp_pinctrl_of_match), + }, + .probe = imx8mp_pinctrl_probe, +}; + +static int __init imx8mp_pinctrl_init(void) +{ + return platform_driver_register(&imx8mp_pinctrl_driver); +} +arch_initcall(imx8mp_pinctrl_init); From 72780ce5f1a4189f3c8dcfb1c596c65146452668 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 13 Jan 2020 23:08:00 +0100 Subject: [PATCH 96/99] gpio: Drop the chained IRQ handler assign function gpiochip_set_chained_irqchip() would assign a chained handler to a GPIO chip. We now populate struct gpio_irq_chip for all chained GPIO irqchips so drop this function. Cc: Andy Shevchenko Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20200113220800.77817-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- Documentation/driver-api/gpio/driver.rst | 5 ----- drivers/gpio/gpio-mt7621.c | 3 +-- drivers/gpio/gpio-xgs-iproc.c | 3 +-- drivers/gpio/gpiolib.c | 25 +----------------------- include/linux/gpio/driver.h | 5 ----- 5 files changed, 3 insertions(+), 38 deletions(-) diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst index 2ff743105927..871922529332 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -507,11 +507,6 @@ available but we try to move away from this: cascaded irq has to be handled by a threaded interrupt handler. Apart from that it works exactly like the chained irqchip. -- DEPRECATED: gpiochip_set_chained_irqchip(): sets up a chained cascaded irq - handler for a gpio_chip from a parent IRQ and passes the struct gpio_chip* - as handler data. Notice that we pass is as the handler data, since the - irqchip data is likely used by the parent irqchip. - - gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a gpio_chip from a parent IRQ. As the parent IRQ has usually been explicitly requested by the driver, this does very little more than diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c index d1d785f983a7..b992321bb852 100644 --- a/drivers/gpio/gpio-mt7621.c +++ b/drivers/gpio/gpio-mt7621.c @@ -253,8 +253,7 @@ mediatek_gpio_bank_probe(struct device *dev, /* * Directly request the irq here instead of passing - * a flow-handler to gpiochip_set_chained_irqchip, - * because the irq is shared. + * a flow-handler because the irq is shared. */ ret = devm_request_irq(dev, mtk->gpio_irq, mediatek_gpio_irq_handler, IRQF_SHARED, diff --git a/drivers/gpio/gpio-xgs-iproc.c b/drivers/gpio/gpio-xgs-iproc.c index 773e5c24309e..55af83629cfc 100644 --- a/drivers/gpio/gpio-xgs-iproc.c +++ b/drivers/gpio/gpio-xgs-iproc.c @@ -251,8 +251,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) /* * Directly request the irq here instead of passing - * a flow-handler to gpiochip_set_chained_irqchip, - * because the irq is shared. + * a flow-handler because the irq is shared. */ ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler, IRQF_SHARED, chip->gc.label, &chip->gc); diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 9913886ede90..ea19ce5fbac5 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1805,7 +1805,7 @@ EXPORT_SYMBOL_GPL(gpiochip_irqchip_irq_valid); * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip * @gc: the gpiochip to set the irqchip chain to * @parent_irq: the irq number corresponding to the parent IRQ for this - * chained irqchip + * cascaded irqchip * @parent_handler: the parent interrupt handler for the accumulated IRQ * coming out of the gpiochip. If the interrupt is nested rather than * cascaded, pass NULL in this handler argument @@ -1847,29 +1847,6 @@ static void gpiochip_set_cascaded_irqchip(struct gpio_chip *gc, } } -/** - * gpiochip_set_chained_irqchip() - connects a chained irqchip to a gpiochip - * @gpiochip: the gpiochip to set the irqchip chain to - * @irqchip: the irqchip to chain to the gpiochip - * @parent_irq: the irq number corresponding to the parent IRQ for this - * chained irqchip - * @parent_handler: the parent interrupt handler for the accumulated IRQ - * coming out of the gpiochip. - */ -void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, - struct irq_chip *irqchip, - unsigned int parent_irq, - irq_flow_handler_t parent_handler) -{ - if (gpiochip->irq.threaded) { - chip_err(gpiochip, "tried to chain a threaded gpiochip\n"); - return; - } - - gpiochip_set_cascaded_irqchip(gpiochip, parent_irq, parent_handler); -} -EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip); - /** * gpiochip_set_nested_irqchip() - connects a nested irqchip to a gpiochip * @gpiochip: the gpiochip to set the irqchip nested handler to diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index e2480ef94c55..7067bc70a473 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -585,11 +585,6 @@ int gpiochip_irq_domain_activate(struct irq_domain *domain, void gpiochip_irq_domain_deactivate(struct irq_domain *domain, struct irq_data *data); -void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, - struct irq_chip *irqchip, - unsigned int parent_irq, - irq_flow_handler_t parent_handler); - void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip, struct irq_chip *irqchip, unsigned int parent_irq); From 06e26b75f5e613b400116fdb7ff6206a681ab271 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 18 Dec 2019 12:43:53 +0000 Subject: [PATCH 97/99] pinctrl: mvebu: armada-37xx: use use platform api platform_irq_count() and platform_get_irq() is the more generic way (independent of device trees) to determine the count of available interrupts. So use this instead. As platform_irq_count() might return an error code (which of_irq_count doesn't) some additional handling is necessary. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/1576672860-14420-1-git-send-email-peng.fan@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 9f0b3d38cc77..243fba254175 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -739,7 +738,14 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, return ret; } - nr_irq_parent = of_irq_count(np); + nr_irq_parent = platform_irq_count(pdev); + if (nr_irq_parent < 0) { + if (nr_irq_parent != -EPROBE_DEFER) + dev_err(dev, "Couldn't determine irq count: %pe\n", + ERR_PTR(nr_irq_parent)); + return nr_irq_parent; + } + spin_lock_init(&info->irq_lock); if (!nr_irq_parent) { @@ -776,7 +782,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, if (!girq->parents) return -ENOMEM; for (i = 0; i < nr_irq_parent; i++) { - int irq = irq_of_parse_and_map(np, i); + int irq = platform_get_irq(pdev, i); if (irq < 0) continue; From 1d44616e7549d0154c1224a3eee3c407029294dc Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 21 Jan 2020 10:09:50 -0800 Subject: [PATCH 98/99] pinctrl: qcom: Don't lock around irq_set_irq_wake() We don't need to hold the local pinctrl lock here to set irq wake on the summary irq line. Doing so only leads to lockdep warnings instead of protecting us from anything. Remove the locking. WARNING: possible circular locking dependency detected 5.4.11 #2 Tainted: G W ------------------------------------------------------ cat/3083 is trying to acquire lock: ffffff81f4fa58c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 but task is already holding lock: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&pctrl->lock){-.-.}: _raw_spin_lock_irqsave+0x64/0x80 msm_gpio_irq_ack+0x68/0xf4 __irq_do_set_handler+0xe0/0x180 __irq_set_handler+0x60/0x9c irq_domain_set_info+0x90/0xb4 gpiochip_hierarchy_irq_domain_alloc+0x110/0x200 __irq_domain_alloc_irqs+0x130/0x29c irq_create_fwspec_mapping+0x1f0/0x300 irq_create_of_mapping+0x70/0x98 of_irq_get+0xa4/0xd4 spi_drv_probe+0x4c/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 __device_attach_driver+0x9c/0x110 bus_for_each_drv+0x88/0xd0 __device_attach+0xb0/0x160 device_initial_probe+0x20/0x2c bus_probe_device+0x34/0x94 device_add+0x35c/0x3f0 spi_add_device+0xbc/0x194 of_register_spi_devices+0x2c8/0x408 spi_register_controller+0x57c/0x6fc spi_geni_probe+0x260/0x328 platform_drv_probe+0x90/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 device_driver_attach+0x4c/0x6c __driver_attach+0xcc/0x154 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0x108/0x1fc driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 spi_geni_driver_init+0x1c/0x24 do_one_initcall+0x1a4/0x3e8 do_initcall_level+0xb4/0xcc do_basic_setup+0x30/0x48 kernel_init_freeable+0x124/0x1a8 kernel_init+0x14/0x100 ret_from_fork+0x10/0x18 -> #0 (&irq_desc_lock_class){-.-.}: __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pctrl->lock); lock(&irq_desc_lock_class); lock(&pctrl->lock); lock(&irq_desc_lock_class); *** DEADLOCK *** 7 locks held by cat/3083: #0: ffffff81f06d1420 (sb_writers#7){.+.+}, at: vfs_write+0xd0/0x1a4 #1: ffffff81c8935680 (&of->mutex){+.+.}, at: kernfs_fop_write+0x12c/0x1fc #2: ffffff81f4c322f0 (kn->count#337){.+.+}, at: kernfs_fop_write+0x134/0x1fc #3: ffffffe89a641d60 (system_transition_mutex){+.+.}, at: pm_suspend+0x108/0x348 #4: ffffff81f190e970 (&dev->mutex){....}, at: __device_suspend+0x168/0x41c #5: ffffff81f183d8c0 (lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 #6: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c stack backtrace: CPU: 4 PID: 3083 Comm: cat Tainted: G W 5.4.11 #2 Hardware name: Google Cheza (rev3+) (DT) Call trace: dump_backtrace+0x0/0x174 show_stack+0x20/0x2c dump_stack+0xc8/0x124 print_circular_bug+0x2ac/0x2c4 check_noncircular+0x1a0/0x1a8 __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc Fixes: 6aced33f4974 ("pinctrl: msm: drop wake_irqs bitmap") Cc: Douglas Anderson Cc: Brian Masney Cc: Lina Iyer Cc: Maulik Shah Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20200121180950.36959-1-swboyd@chromium.org Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 5d6f9f61ce02..9a8daa256a32 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -960,7 +960,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl = gpiochip_get_data(gc); - unsigned long flags; /* * While they may not wake up when the TLMM is powered off, @@ -971,12 +970,8 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) if (d->parent_data) irq_chip_set_wake_parent(d, on); - raw_spin_lock_irqsave(&pctrl->lock, flags); - irq_set_irq_wake(pctrl->irq, on); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); - return 0; } From 122ce22cb37b087e7e28ebb16044a622b0a22233 Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Wed, 22 Jan 2020 11:11:50 +0000 Subject: [PATCH 99/99] pinctrl: madera: Remove extra blank line Signed-off-by: Charles Keepax Link: https://lore.kernel.org/r/20200122111150.11033-1-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij --- drivers/pinctrl/cirrus/pinctrl-madera-core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index e2f72dcce4c9..7b6409ef553c 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -560,7 +560,6 @@ static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev, seq_puts(s, " SCHMITT"); } - static const struct pinctrl_ops madera_pin_group_ops = { .get_groups_count = madera_get_groups_count, .get_group_name = madera_get_group_name,