mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-10 15:19:51 +00:00
pinctrl: spear: plgpio: Convert to regmap
Resources need to be shared between pinmux and plgpio. Use regmap (syscon) to access resources to allow an easy way to share resources. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20211202095255.165797-3-herve.codina@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Herve Codina
Linus Walleij
parent
d11db044a3
commit
7151cef59e
@ -14,11 +14,13 @@
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#define MAX_GPIO_PER_REG 32
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@ -64,7 +66,7 @@ struct plgpio_regs {
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*/
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struct plgpio {
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spinlock_t lock;
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void __iomem *base;
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struct regmap *regmap;
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struct clk *clk;
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struct gpio_chip chip;
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int (*p2o)(int pin); /* pin_to_offset */
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@ -77,33 +79,38 @@ struct plgpio {
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};
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/* register manipulation inline functions */
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static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
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static inline u32 is_plgpio_set(struct regmap *regmap, u32 pin, u32 reg)
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{
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u32 offset = PIN_OFFSET(pin);
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void __iomem *reg_off = REG_OFFSET(base, reg, pin);
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u32 val = readl_relaxed(reg_off);
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u32 reg_off = REG_OFFSET(0, reg, pin);
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u32 val;
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regmap_read(regmap, reg_off, &val);
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return !!(val & (1 << offset));
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}
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static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
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static inline void plgpio_reg_set(struct regmap *regmap, u32 pin, u32 reg)
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{
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u32 offset = PIN_OFFSET(pin);
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void __iomem *reg_off = REG_OFFSET(base, reg, pin);
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u32 val = readl_relaxed(reg_off);
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u32 reg_off = REG_OFFSET(0, reg, pin);
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u32 mask;
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writel_relaxed(val | (1 << offset), reg_off);
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mask = 1 << offset;
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regmap_update_bits(regmap, reg_off, mask, mask);
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}
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static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
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static inline void plgpio_reg_reset(struct regmap *regmap, u32 pin, u32 reg)
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{
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u32 offset = PIN_OFFSET(pin);
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void __iomem *reg_off = REG_OFFSET(base, reg, pin);
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u32 val = readl_relaxed(reg_off);
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u32 reg_off = REG_OFFSET(0, reg, pin);
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u32 mask;
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writel_relaxed(val & ~(1 << offset), reg_off);
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mask = 1 << offset;
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regmap_update_bits(regmap, reg_off, mask, 0);
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}
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/* gpio framework specific routines */
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static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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@ -118,7 +125,7 @@ static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
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plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.dir);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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return 0;
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@ -145,13 +152,13 @@ static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
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spin_lock_irqsave(&plgpio->lock, flags);
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if (value)
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plgpio_reg_set(plgpio->base, wdata_offset,
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plgpio_reg_set(plgpio->regmap, wdata_offset,
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plgpio->regs.wdata);
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else
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plgpio_reg_reset(plgpio->base, wdata_offset,
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plgpio_reg_reset(plgpio->regmap, wdata_offset,
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plgpio->regs.wdata);
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plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
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plgpio_reg_reset(plgpio->regmap, dir_offset, plgpio->regs.dir);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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return 0;
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@ -171,7 +178,7 @@ static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
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return -EINVAL;
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}
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return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
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return is_plgpio_set(plgpio->regmap, offset, plgpio->regs.rdata);
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}
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static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
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@ -189,9 +196,9 @@ static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
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}
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if (value)
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
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plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.wdata);
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else
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
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plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.wdata);
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}
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static int plgpio_request(struct gpio_chip *chip, unsigned offset)
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@ -234,7 +241,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset)
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
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plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.enb);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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return 0;
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@ -266,7 +273,7 @@ static void plgpio_free(struct gpio_chip *chip, unsigned offset)
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
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plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.enb);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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disable_clk:
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@ -292,7 +299,7 @@ static void plgpio_irq_disable(struct irq_data *d)
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
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plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.ie);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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}
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@ -311,7 +318,7 @@ static void plgpio_irq_enable(struct irq_data *d)
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
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plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.ie);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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}
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@ -320,7 +327,7 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct plgpio *plgpio = gpiochip_get_data(gc);
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int offset = d->hwirq;
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void __iomem *reg_off;
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u32 reg_off;
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unsigned int supported_type = 0, val;
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if (offset >= plgpio->chip.ngpio)
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@ -337,14 +344,14 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
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if (plgpio->regs.eit == -1)
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return 0;
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reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
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val = readl_relaxed(reg_off);
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reg_off = REG_OFFSET(0, plgpio->regs.eit, offset);
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regmap_read(plgpio->regmap, reg_off, &val);
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offset = PIN_OFFSET(offset);
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if (trigger & IRQ_TYPE_EDGE_RISING)
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writel_relaxed(val | (1 << offset), reg_off);
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regmap_write(plgpio->regmap, reg_off, val | (1 << offset));
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else
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writel_relaxed(val & ~(1 << offset), reg_off);
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regmap_write(plgpio->regmap, reg_off, val & ~(1 << offset));
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return 0;
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}
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@ -362,7 +369,8 @@ static void plgpio_irq_handler(struct irq_desc *desc)
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struct plgpio *plgpio = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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int regs_count, count, pin, offset, i = 0;
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unsigned long pending;
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u32 pending;
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unsigned long pendingl;
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count = plgpio->chip.ngpio;
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regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
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@ -370,14 +378,14 @@ static void plgpio_irq_handler(struct irq_desc *desc)
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chained_irq_enter(irqchip, desc);
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/* check all plgpio MIS registers for a possible interrupt */
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for (; i < regs_count; i++) {
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pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
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i * sizeof(int *));
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regmap_read(plgpio->regmap, plgpio->regs.mis +
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i * sizeof(int *), &pending);
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if (!pending)
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continue;
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/* clear interrupts */
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writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
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i * sizeof(int *));
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regmap_write(plgpio->regmap, plgpio->regs.mis +
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i * sizeof(int *), ~pending);
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/*
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* clear extra bits in last register having gpios < MAX/REG
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* ex: Suppose there are max 102 plgpios. then last register
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@ -389,7 +397,8 @@ static void plgpio_irq_handler(struct irq_desc *desc)
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if (count < MAX_GPIO_PER_REG)
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pending &= (1 << count) - 1;
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for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
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pendingl = pending;
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for_each_set_bit(offset, &pendingl, MAX_GPIO_PER_REG) {
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/* get correct pin for "offset" */
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if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
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pin = plgpio->o2p(offset);
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@ -511,6 +520,7 @@ static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
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end:
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return ret;
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}
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static int plgpio_probe(struct platform_device *pdev)
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{
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struct plgpio *plgpio;
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@ -520,9 +530,12 @@ static int plgpio_probe(struct platform_device *pdev)
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if (!plgpio)
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return -ENOMEM;
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plgpio->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(plgpio->base))
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return PTR_ERR(plgpio->base);
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plgpio->regmap = device_node_to_regmap(pdev->dev.of_node);
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if (IS_ERR(plgpio->regmap)) {
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dev_err(&pdev->dev, "Init regmap failed (%pe)\n",
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plgpio->regmap);
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return PTR_ERR(plgpio->regmap);
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}
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ret = plgpio_probe_dt(pdev, plgpio);
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if (ret) {
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@ -607,22 +620,23 @@ static int plgpio_suspend(struct device *dev)
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{
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struct plgpio *plgpio = dev_get_drvdata(dev);
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int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
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void __iomem *off;
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u32 off;
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for (i = 0; i < reg_count; i++) {
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off = plgpio->base + i * sizeof(int *);
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off = i * sizeof(int *);
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if (plgpio->regs.enb != -1)
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plgpio->csave_regs[i].enb =
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readl_relaxed(plgpio->regs.enb + off);
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regmap_read(plgpio->regmap, plgpio->regs.enb + off,
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&plgpio->csave_regs[i].enb);
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if (plgpio->regs.eit != -1)
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plgpio->csave_regs[i].eit =
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readl_relaxed(plgpio->regs.eit + off);
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plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
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off);
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plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
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off);
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plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
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regmap_read(plgpio->regmap, plgpio->regs.eit + off,
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&plgpio->csave_regs[i].eit);
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regmap_read(plgpio->regmap, plgpio->regs.wdata + off,
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&plgpio->csave_regs[i].wdata);
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regmap_read(plgpio->regmap, plgpio->regs.dir + off,
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&plgpio->csave_regs[i].dir);
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regmap_read(plgpio->regmap, plgpio->regs.ie + off,
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&plgpio->csave_regs[i].ie);
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}
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return 0;
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@ -636,7 +650,7 @@ static int plgpio_suspend(struct device *dev)
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*/
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#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
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{ \
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_tmp = readl_relaxed(plgpio->regs.__reg + _off); \
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regmap_read(plgpio->regmap, plgpio->regs.__reg + _off, &_tmp); \
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_tmp &= ~_mask; \
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plgpio->csave_regs[i].__reg = \
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_tmp | (plgpio->csave_regs[i].__reg & _mask); \
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@ -646,11 +660,11 @@ static int plgpio_resume(struct device *dev)
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{
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struct plgpio *plgpio = dev_get_drvdata(dev);
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int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
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void __iomem *off;
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u32 off;
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u32 mask, tmp;
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for (i = 0; i < reg_count; i++) {
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off = plgpio->base + i * sizeof(int *);
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off = i * sizeof(int *);
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if (i == reg_count - 1) {
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mask = (1 << (plgpio->chip.ngpio - i *
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@ -667,20 +681,22 @@ static int plgpio_resume(struct device *dev)
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plgpio_prepare_reg(ie, off, mask, tmp);
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}
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writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
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off);
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writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
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off);
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regmap_write(plgpio->regmap, plgpio->regs.wdata + off,
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plgpio->csave_regs[i].wdata);
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regmap_write(plgpio->regmap, plgpio->regs.dir + off,
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plgpio->csave_regs[i].dir);
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if (plgpio->regs.eit != -1)
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writel_relaxed(plgpio->csave_regs[i].eit,
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plgpio->regs.eit + off);
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regmap_write(plgpio->regmap, plgpio->regs.eit + off,
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plgpio->csave_regs[i].eit);
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writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
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regmap_write(plgpio->regmap, plgpio->regs.ie + off,
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plgpio->csave_regs[i].ie);
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if (plgpio->regs.enb != -1)
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writel_relaxed(plgpio->csave_regs[i].enb,
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plgpio->regs.enb + off);
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regmap_write(plgpio->regmap, plgpio->regs.enb + off,
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plgpio->csave_regs[i].enb);
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}
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return 0;
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