mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2024-12-28 16:53:49 +00:00
PCI: Use resource_set_{range,size}() helpers
Convert open-coded resource size calculations to use resource_set_{range,size}() helpers. While at it, use SZ_* for size parameter where appropriate which makes the intent of code more obvious. Also, cast sizes to resource_size_t, not u64. Link: https://lore.kernel.org/r/20240614100606.15830-3-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
parent
9fb6fef0fb
commit
783602c920
@ -1460,7 +1460,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
|
||||
pcie->cs = *res;
|
||||
|
||||
/* constrain configuration space to 4 KiB */
|
||||
pcie->cs.end = pcie->cs.start + SZ_4K - 1;
|
||||
resource_set_size(&pcie->cs, SZ_4K);
|
||||
|
||||
pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
|
||||
if (IS_ERR(pcie->cfg)) {
|
||||
|
@ -400,9 +400,9 @@ static int thunder_pem_acpi_init(struct pci_config_window *cfg)
|
||||
* Reserve 64K size PEM specific resources. The full 16M range
|
||||
* size is required for thunder_pem_init() call.
|
||||
*/
|
||||
res_pem->end = res_pem->start + SZ_64K - 1;
|
||||
resource_set_size(res_pem, SZ_64K);
|
||||
thunder_pem_reserve_range(dev, root->segment, res_pem);
|
||||
res_pem->end = res_pem->start + SZ_16M - 1;
|
||||
resource_set_size(res_pem, SZ_16M);
|
||||
|
||||
/* Reserve PCI configuration space as well. */
|
||||
thunder_pem_reserve_range(dev, root->segment, &cfg->res);
|
||||
|
@ -55,7 +55,7 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
|
||||
bus_range_max = resource_size(cfgres) >> bus_shift;
|
||||
if (bus_range > bus_range_max) {
|
||||
bus_range = bus_range_max;
|
||||
cfg->busr.end = busr->start + bus_range - 1;
|
||||
resource_set_size(&cfg->busr, bus_range);
|
||||
dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
|
||||
cfgres, &cfg->busr, busr);
|
||||
}
|
||||
|
@ -327,8 +327,8 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id)
|
||||
virtfn->resource[i].name = pci_name(virtfn);
|
||||
virtfn->resource[i].flags = res->flags;
|
||||
size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
|
||||
virtfn->resource[i].start = res->start + size * id;
|
||||
virtfn->resource[i].end = virtfn->resource[i].start + size - 1;
|
||||
resource_set_range(&virtfn->resource[i],
|
||||
res->start + size * id, size);
|
||||
rc = request_resource(res, &virtfn->resource[i]);
|
||||
BUG_ON(rc);
|
||||
}
|
||||
@ -804,7 +804,7 @@ static int sriov_init(struct pci_dev *dev, int pos)
|
||||
goto failed;
|
||||
}
|
||||
iov->barsz[i] = resource_size(res);
|
||||
res->end = res->start + resource_size(res) * total - 1;
|
||||
resource_set_size(res, resource_size(res) * total);
|
||||
pci_info(dev, "%s %pR: contains BAR %d for %d VFs\n",
|
||||
res_name, res, i, total);
|
||||
i += bar64;
|
||||
|
@ -6649,8 +6649,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
|
||||
} else {
|
||||
r->flags &= ~IORESOURCE_SIZEALIGN;
|
||||
r->flags |= IORESOURCE_STARTALIGN;
|
||||
r->start = align;
|
||||
r->end = r->start + size - 1;
|
||||
resource_set_range(r, align, size);
|
||||
}
|
||||
r->flags |= IORESOURCE_UNSET;
|
||||
}
|
||||
|
@ -29,6 +29,7 @@
|
||||
#include <linux/nvme.h>
|
||||
#include <linux/platform_data/x86/apple.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/switchtec.h>
|
||||
#include "pci.h"
|
||||
@ -586,8 +587,7 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev)
|
||||
const char *r_name = pci_resource_name(dev, i);
|
||||
|
||||
if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
|
||||
r->end = PAGE_SIZE - 1;
|
||||
r->start = 0;
|
||||
resource_set_range(r, 0, PAGE_SIZE);
|
||||
r->flags |= IORESOURCE_UNSET;
|
||||
pci_info(dev, "%s %pR: expanded to page size\n",
|
||||
r_name, r);
|
||||
@ -606,8 +606,7 @@ static void quirk_s3_64M(struct pci_dev *dev)
|
||||
|
||||
if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
|
||||
r->flags |= IORESOURCE_UNSET;
|
||||
r->start = 0;
|
||||
r->end = 0x3ffffff;
|
||||
resource_set_range(r, 0, SZ_64M);
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
|
||||
@ -1342,8 +1341,7 @@ static void quirk_dunord(struct pci_dev *dev)
|
||||
struct resource *r = &dev->resource[1];
|
||||
|
||||
r->flags |= IORESOURCE_UNSET;
|
||||
r->start = 0;
|
||||
r->end = 0xffffff;
|
||||
resource_set_range(r, 0, SZ_16M);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
|
||||
|
||||
@ -2340,8 +2338,7 @@ static void quirk_tc86c001_ide(struct pci_dev *dev)
|
||||
|
||||
if (r->start & 0x8) {
|
||||
r->flags |= IORESOURCE_UNSET;
|
||||
r->start = 0;
|
||||
r->end = 0xf;
|
||||
resource_set_range(r, 0, SZ_16);
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
|
||||
@ -2369,8 +2366,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev)
|
||||
pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
|
||||
bar);
|
||||
r->flags |= IORESOURCE_UNSET;
|
||||
r->start = 0;
|
||||
r->end = 0xff;
|
||||
resource_set_range(r, 0, SZ_256);
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
|
||||
@ -3522,13 +3518,13 @@ static void quirk_intel_ntb(struct pci_dev *dev)
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
|
||||
resource_set_size(&dev->resource[2], (resource_size_t)1 << val);
|
||||
|
||||
rc = pci_read_config_byte(dev, 0x00D1, &val);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
|
||||
resource_set_size(&dev->resource[4], (resource_size_t)1 << val);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
|
||||
|
@ -246,8 +246,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
|
||||
add_size = add_res->add_size;
|
||||
align = add_res->min_align;
|
||||
if (!resource_size(res)) {
|
||||
res->start = align;
|
||||
res->end = res->start + add_size - 1;
|
||||
resource_set_range(res, align, add_size);
|
||||
if (pci_assign_resource(add_res->dev, idx))
|
||||
reset_resource(res);
|
||||
} else {
|
||||
@ -938,8 +937,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
return;
|
||||
}
|
||||
|
||||
b_res->start = min_align;
|
||||
b_res->end = b_res->start + size0 - 1;
|
||||
resource_set_range(b_res, min_align, size0);
|
||||
b_res->flags |= IORESOURCE_STARTALIGN;
|
||||
if (bus->self && size1 > size0 && realloc_head) {
|
||||
add_to_list(realloc_head, bus->self, b_res, size1-size0,
|
||||
@ -1202,8 +1200,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
* Reserve some resources for CardBus. We reserve a fixed amount
|
||||
* of bus space for CardBus bridges.
|
||||
*/
|
||||
b_res->start = pci_cardbus_io_size;
|
||||
b_res->end = b_res->start + pci_cardbus_io_size - 1;
|
||||
resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size);
|
||||
b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res->end -= pci_cardbus_io_size;
|
||||
@ -1215,8 +1212,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
|
||||
if (b_res->parent)
|
||||
goto handle_b_res_2;
|
||||
b_res->start = pci_cardbus_io_size;
|
||||
b_res->end = b_res->start + pci_cardbus_io_size - 1;
|
||||
resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size);
|
||||
b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res->end -= pci_cardbus_io_size;
|
||||
@ -1249,8 +1245,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
* Otherwise, allocate one region of twice the size.
|
||||
*/
|
||||
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
|
||||
b_res->start = pci_cardbus_mem_size;
|
||||
b_res->end = b_res->start + pci_cardbus_mem_size - 1;
|
||||
resource_set_range(b_res, pci_cardbus_mem_size,
|
||||
pci_cardbus_mem_size);
|
||||
b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
|
||||
IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
@ -1267,8 +1263,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
|
||||
if (b_res->parent)
|
||||
goto handle_done;
|
||||
b_res->start = pci_cardbus_mem_size;
|
||||
b_res->end = b_res->start + b_res_3_size - 1;
|
||||
resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size);
|
||||
b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res->end -= b_res_3_size;
|
||||
@ -1847,7 +1842,7 @@ static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
|
||||
return;
|
||||
}
|
||||
|
||||
res->end = res->start + new_size - 1;
|
||||
resource_set_size(res, new_size);
|
||||
|
||||
/* If the resource is part of the add_list, remove it now */
|
||||
if (add_list)
|
||||
@ -2010,8 +2005,8 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
||||
* what is available).
|
||||
*/
|
||||
align = pci_resource_alignment(dev, res);
|
||||
io.end = align ? io.start + ALIGN_DOWN(io_per_b, align) - 1
|
||||
: io.start + io_per_b - 1;
|
||||
resource_set_size(&io, align ? ALIGN_DOWN(io_per_b, align)
|
||||
: io_per_b);
|
||||
|
||||
/*
|
||||
* The x_per_b holds the extra resource space that can be
|
||||
@ -2023,15 +2018,15 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
||||
|
||||
res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
|
||||
align = pci_resource_alignment(dev, res);
|
||||
mmio.end = align ? mmio.start + ALIGN_DOWN(mmio_per_b, align) - 1
|
||||
: mmio.start + mmio_per_b - 1;
|
||||
resource_set_size(&mmio, align ? ALIGN_DOWN(mmio_per_b, align)
|
||||
: mmio_per_b);
|
||||
mmio.start -= resource_size(res);
|
||||
|
||||
res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
|
||||
align = pci_resource_alignment(dev, res);
|
||||
mmio_pref.end = align ? mmio_pref.start +
|
||||
ALIGN_DOWN(mmio_pref_per_b, align) - 1
|
||||
: mmio_pref.start + mmio_pref_per_b - 1;
|
||||
resource_set_size(&mmio_pref,
|
||||
align ? ALIGN_DOWN(mmio_pref_per_b, align)
|
||||
: mmio_pref_per_b);
|
||||
mmio_pref.start -= resource_size(res);
|
||||
|
||||
pci_bus_distribute_available_resources(b, add_list, io, mmio,
|
||||
|
@ -211,8 +211,7 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
|
||||
|
||||
start = res->start;
|
||||
end = res->end;
|
||||
res->start = fw_addr;
|
||||
res->end = res->start + size - 1;
|
||||
resource_set_range(res, fw_addr, size);
|
||||
res->flags &= ~IORESOURCE_UNSET;
|
||||
|
||||
root = pci_find_parent_resource(dev, res);
|
||||
@ -463,7 +462,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno, int size)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
|
||||
resource_set_size(res, pci_rebar_size_to_bytes(size));
|
||||
|
||||
/* Check if the new config works by trying to assign everything. */
|
||||
if (dev->bus->self) {
|
||||
@ -475,7 +474,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno, int size)
|
||||
|
||||
error_resize:
|
||||
pci_rebar_set_size(dev, resno, old);
|
||||
res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
|
||||
resource_set_size(res, pci_rebar_size_to_bytes(old));
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_resize_resource);
|
||||
|
Loading…
Reference in New Issue
Block a user