mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-11 07:39:47 +00:00
OpenRISC updates for 5.17
A few fixups and enhancements for OpenRISC: - Fix to add proper wrapper for clone3 to save callee saved regs - Cleanups for clone, fork and switch - Add support for common clk so OpenRISC and use more drivers -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmHhdC4ACgkQw7McLV5m J+ShYw/+L3hq47BMVf+6m53t4TjY16GOLQUHBmUrcID4NGkbaBZEcEuogFpRj1kK wVORbM/RGkl0ISuqW9b4QYUR7sxDWTMp6aTH4AhIsDA+KhXPbUvK5pu7XCwWYSyc LA+6BtNvF7h2l84cvxXSuBrlfVoW3yl9Iczk/PZB2Z5SNZYze7h6M9q/99q6V03X 03Hz+W+BeY5KsS3vTLmM6PtkSB2NpfHQ+0jtj2/mUSHrTzGxqyKYiS9peNA7Ub2w U1/zs9vGHZG7bQ9BRr8sgiDnviQFJFe+h5DtmY/pYaeBFIvChVpMWIyj7WktDD/R WQDxOyPcGO68E6HqLy7byIwENVCwARDr2/n9zmz3KHwFxItAQd/YaK+vxTMH7QbB gJ2k9mdp/IWKvb1Hv/HprF1YM6/FUlrbt/lbQwWkOCkfgBVrlUCe9rH4SrB3ArJ6 fqeFxp95MMovtXgl6v9Un5OxGz2AkHTKA632hVJA9K/5mTOE7qRuSXupDj1EpQnV WagfJkYboGo7lYuxkq+Mo2LLKPm5ziVRDWa7JjKbfCLApiPIaVqKUYtHnoiDVAC+ 8ECdcJ5aI6wlqB2Dkss+n1TsypbSATo4z6Ai+IJ/6uqj7LiZE+/6+WJbIMaGle7p QP3Y2JmY8Wf6qzXVYNZ9BuYnAKIy9ZgkPui4B9y6PwabzHWz5AI= =i+xH -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://github.com/openrisc/linux Pull OpenRISC updates from Stafford Horne: "A few fixups and enhancements for OpenRISC: - Fix to add proper wrapper for clone3 to save callee saved regs - Cleanups for clone, fork and switch - Add support for common clk so OpenRISC and use more drivers" * tag 'for-linus' of git://github.com/openrisc/linux: openrisc: init: Add support for common clk openrisc: Add clone3 ABI wrapper openrisc: Use delay slot for clone and fork wrappers openrisc: Cleanup switch code and comments
This commit is contained in:
commit
871bfa02d0
@ -10,6 +10,7 @@ config OPENRISC
|
||||
select ARCH_HAS_DMA_SET_UNCACHED
|
||||
select ARCH_HAS_DMA_CLEAR_UNCACHED
|
||||
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
|
||||
select COMMON_CLK
|
||||
select OF
|
||||
select OF_EARLY_FLATTREE
|
||||
select IRQ_DOMAIN
|
||||
|
@ -22,9 +22,11 @@ asmlinkage long sys_or1k_atomic(unsigned long type, unsigned long *v1,
|
||||
|
||||
asmlinkage long __sys_clone(unsigned long clone_flags, unsigned long newsp,
|
||||
void __user *parent_tid, void __user *child_tid, int tls);
|
||||
asmlinkage long __sys_clone3(struct clone_args __user *uargs, size_t size);
|
||||
asmlinkage long __sys_fork(void);
|
||||
|
||||
#define sys_clone __sys_clone
|
||||
#define sys_clone3 __sys_clone3
|
||||
#define sys_fork __sys_fork
|
||||
|
||||
#endif /* __ASM_OPENRISC_SYSCALLS_H */
|
||||
|
@ -1001,11 +1001,10 @@ ENTRY(ret_from_fork)
|
||||
l.lwz r11,PT_GPR11(r1)
|
||||
|
||||
/* The syscall fast path return expects call-saved registers
|
||||
* r12-r28 to be untouched, so we restore them here as they
|
||||
* r14-r28 to be untouched, so we restore them here as they
|
||||
* will have been effectively clobbered when arriving here
|
||||
* via the call to switch()
|
||||
*/
|
||||
l.lwz r12,PT_GPR12(r1)
|
||||
l.lwz r14,PT_GPR14(r1)
|
||||
l.lwz r16,PT_GPR16(r1)
|
||||
l.lwz r18,PT_GPR18(r1)
|
||||
@ -1037,10 +1036,10 @@ ENTRY(ret_from_fork)
|
||||
|
||||
/* _switch MUST never lay on page boundry, cause it runs from
|
||||
* effective addresses and beeing interrupted by iTLB miss would kill it.
|
||||
* dTLB miss seams to never accour in the bad place since data accesses
|
||||
* dTLB miss seems to never accour in the bad place since data accesses
|
||||
* are from task structures which are always page aligned.
|
||||
*
|
||||
* The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
|
||||
* The problem happens in RESTORE_ALL where we first set the EPCR
|
||||
* register, then load the previous register values and only at the end call
|
||||
* the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
|
||||
* garbled and we end up calling l.rfe with the wrong EPCR. (same probably
|
||||
@ -1068,9 +1067,8 @@ ENTRY(_switch)
|
||||
/* No need to store r1/PT_SP as it goes into KSP below */
|
||||
l.sw PT_GPR2(r1),r2
|
||||
l.sw PT_GPR9(r1),r9
|
||||
/* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
|
||||
* and expects r12 to be callee-saved... */
|
||||
l.sw PT_GPR12(r1),r12
|
||||
|
||||
/* Save callee-saved registers to the new pt_regs */
|
||||
l.sw PT_GPR14(r1),r14
|
||||
l.sw PT_GPR16(r1),r16
|
||||
l.sw PT_GPR18(r1),r18
|
||||
@ -1111,9 +1109,7 @@ ENTRY(_switch)
|
||||
/* No need to restore r10 */
|
||||
/* ...and do not restore r11 */
|
||||
|
||||
/* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
|
||||
* and expects r12 to be callee-saved... */
|
||||
l.lwz r12,PT_GPR12(r1)
|
||||
/* Restore callee-saved registers */
|
||||
l.lwz r14,PT_GPR14(r1)
|
||||
l.lwz r16,PT_GPR16(r1)
|
||||
l.lwz r18,PT_GPR18(r1)
|
||||
@ -1166,15 +1162,18 @@ _fork_save_extra_regs_and_call:
|
||||
|
||||
ENTRY(__sys_clone)
|
||||
l.movhi r29,hi(sys_clone)
|
||||
l.ori r29,r29,lo(sys_clone)
|
||||
l.j _fork_save_extra_regs_and_call
|
||||
l.nop
|
||||
l.ori r29,r29,lo(sys_clone)
|
||||
|
||||
ENTRY(__sys_clone3)
|
||||
l.movhi r29,hi(sys_clone3)
|
||||
l.j _fork_save_extra_regs_and_call
|
||||
l.ori r29,r29,lo(sys_clone3)
|
||||
|
||||
ENTRY(__sys_fork)
|
||||
l.movhi r29,hi(sys_fork)
|
||||
l.ori r29,r29,lo(sys_fork)
|
||||
l.j _fork_save_extra_regs_and_call
|
||||
l.nop
|
||||
l.ori r29,r29,lo(sys_fork)
|
||||
|
||||
ENTRY(sys_rt_sigreturn)
|
||||
l.jal _sys_rt_sigreturn
|
||||
|
@ -20,6 +20,7 @@
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_clk.h>
|
||||
|
||||
#include <asm/cpuinfo.h>
|
||||
|
||||
@ -169,4 +170,7 @@ void __init time_init(void)
|
||||
|
||||
openrisc_timer_init();
|
||||
openrisc_clockevent_init();
|
||||
|
||||
of_clk_init(NULL);
|
||||
timer_probe();
|
||||
}
|
||||
|
Loading…
x
Reference in New Issue
Block a user