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clk: clocking-wizard: move dynamic reconfig setup behind flag

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Xilinx clocking wizard IP core's dynamic reconfiguration support is
optionally enabled at build time. Use the new boolean devicetree
property to indicate whether the hardware supports this feature or not.

Signed-off-by: Harry Austen <hpausten@protonmail.com>
Link: https://lore.kernel.org/r/20240913191037.2690-7-hpausten@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Harry Austen 2024-09-13 19:11:42 +00:00 committed by Stephen Boyd
parent 698a3e3c5e
commit 8e742c6e1b
1 changed files with 38 additions and 35 deletions
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73
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
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@ -1146,20 +1146,6 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (IS_ERR(clk_wzrd->base)) if (IS_ERR(clk_wzrd->base))
return PTR_ERR(clk_wzrd->base); return PTR_ERR(clk_wzrd->base);
ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
if (!ret) {
if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
clk_wzrd->speed_grade);
clk_wzrd->speed_grade = 0;
}
}
clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
if (IS_ERR(clk_wzrd->clk_in1))
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
"clk_in1 not found\n");
clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
if (IS_ERR(clk_wzrd->axi_clk)) if (IS_ERR(clk_wzrd->axi_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
@ -1170,31 +1156,48 @@ static int clk_wzrd_probe(struct platform_device *pdev)
return -EINVAL; return -EINVAL;
} }
ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs); if (!of_property_present(np, "xlnx,static-config")) {
if (ret) ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
return ret; if (!ret) {
if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
clk_wzrd->speed_grade);
clk_wzrd->speed_grade = 0;
}
}
clk_wzrd->clk_data.num = nr_outputs; clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, &clk_wzrd->clk_data); if (IS_ERR(clk_wzrd->clk_in1))
if (ret) { return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
dev_err(&pdev->dev, "unable to register clock provider\n"); "clk_in1 not found\n");
return ret;
}
if (clk_wzrd->speed_grade) { ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs);
clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1,
&clk_wzrd->nb);
if (ret) if (ret)
dev_warn(&pdev->dev, return ret;
"unable to register clock notifier\n");
ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk, clk_wzrd->clk_data.num = nr_outputs;
&clk_wzrd->nb); ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
if (ret) &clk_wzrd->clk_data);
dev_warn(&pdev->dev, if (ret) {
"unable to register clock notifier\n"); dev_err(&pdev->dev, "unable to register clock provider\n");
return ret;
}
if (clk_wzrd->speed_grade) {
clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1,
&clk_wzrd->nb);
if (ret)
dev_warn(&pdev->dev,
"unable to register clock notifier\n");
ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk,
&clk_wzrd->nb);
if (ret)
dev_warn(&pdev->dev,
"unable to register clock notifier\n");
}
} }
return 0; return 0;