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MIPS: Add set/clear CP0 macros for PageGrain register

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Build set and clear macros for the PageGrain register.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9289/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Steven J. Hill 2015-02-19 10:18:52 -06:00 committed by Ralf Baechle
parent 05f9883a28
commit a5770df095
3 changed files with 5 additions and 4 deletions
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1
arch/mips/include/asm/mipsregs.h
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@ -1897,6 +1897,7 @@ __BUILD_SET_C0(config5)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
__BUILD_SET_C0(pagegrain)
__BUILD_SET_C0(brcm_config_0)
__BUILD_SET_C0(brcm_bus_pll)
__BUILD_SET_C0(brcm_reset)

2
arch/mips/kernel/cpu-probe.c
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@ -550,7 +550,7 @@ static void decode_configs(struct cpuinfo_mips *c)
if (cpu_has_rixi) {
/* Enable the RIXI exceptions */
write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
set_c0_pagegrain(PG_IEC);
back_to_back_c0_hazard();
/* Verify the IEC bit is set */
if (read_c0_pagegrain() & PG_IEC)

6
arch/mips/mm/tlb-r4k.c
View File

@ -485,11 +485,11 @@ static void r4k_tlb_configure(void)
* Enable the no read, no exec bits, and enable large virtual
* address.
*/
u32 pg = PG_RIE | PG_XIE;
#ifdef CONFIG_64BIT
pg |= PG_ELPA;
set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA);
#else
set_c0_pagegrain(PG_RIE | PG_XIE);
#endif
write_c0_pagegrain(pg);
}
temp_tlb_entry = current_cpu_data.tlbsize - 1;