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ASoC: tlv320aic32x4: replace codec to component
Now we can replace Codec to Component. Let's do it. Note: xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 0 -> .idle_bias_on = 1 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kuninori Morimoto
Mark Brown
parent
7928b2cbe5
commit
b154dc5d76
@ -82,10 +82,10 @@ struct aic32x4_priv {
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static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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val = snd_soc_read(codec, AIC32X4_DINCTL);
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val = snd_soc_component_read32(component, AIC32X4_DINCTL);
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ucontrol->value.integer.value[0] = (val & 0x01);
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@ -95,11 +95,11 @@ static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
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static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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u8 gpio_check;
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val = snd_soc_read(codec, AIC32X4_DOUTCTL);
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val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
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gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
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if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
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printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
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@ -115,7 +115,7 @@ static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
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else
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val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
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snd_soc_write(codec, AIC32X4_DOUTCTL, val);
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snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
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return 0;
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};
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@ -123,10 +123,10 @@ static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
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static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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val = snd_soc_read(codec, AIC32X4_SCLKCTL);
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val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
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ucontrol->value.integer.value[0] = (val & 0x01);
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@ -136,11 +136,11 @@ static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
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static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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u8 gpio_check;
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val = snd_soc_read(codec, AIC32X4_MISOCTL);
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val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
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gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
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if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
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printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
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@ -156,7 +156,7 @@ static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
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else
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val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
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snd_soc_write(codec, AIC32X4_MISOCTL, val);
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snd_soc_component_write(component, AIC32X4_MISOCTL, val);
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return 0;
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};
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@ -164,10 +164,10 @@ static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
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static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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val = snd_soc_read(codec, AIC32X4_GPIOCTL);
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val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
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ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
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return 0;
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@ -176,11 +176,11 @@ static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
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static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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u8 val;
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u8 gpio_check;
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val = snd_soc_read(codec, AIC32X4_GPIOCTL);
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val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
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gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
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if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
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printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
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@ -196,7 +196,7 @@ static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
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else
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val &= 0xfe;
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snd_soc_write(codec, AIC32X4_GPIOCTL, val);
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snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
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return 0;
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};
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@ -597,8 +597,8 @@ static inline int aic32x4_get_divs(int mclk, int rate)
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static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
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struct snd_soc_component *component = codec_dai->component;
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struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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switch (freq) {
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case 12000000:
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@ -613,7 +613,7 @@ static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct snd_soc_component *component = codec_dai->component;
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u8 iface_reg_1 = 0;
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u8 iface_reg_2 = 0;
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u8 iface_reg_3 = 0;
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@ -657,12 +657,12 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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return -EINVAL;
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}
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snd_soc_update_bits(codec, AIC32X4_IFACE1,
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snd_soc_component_update_bits(component, AIC32X4_IFACE1,
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AIC32X4_IFACE1_DATATYPE_MASK |
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AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
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snd_soc_update_bits(codec, AIC32X4_IFACE2,
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snd_soc_component_update_bits(component, AIC32X4_IFACE2,
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AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
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snd_soc_update_bits(codec, AIC32X4_IFACE3,
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snd_soc_component_update_bits(component, AIC32X4_IFACE3,
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AIC32X4_BCLKINV_MASK, iface_reg_3);
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return 0;
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@ -672,8 +672,8 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
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struct snd_soc_component *component = dai->component;
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struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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u8 iface1_reg = 0;
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u8 dacsetup_reg = 0;
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int i;
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@ -685,54 +685,54 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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}
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/* MCLK as PLL_CLKIN */
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snd_soc_update_bits(codec, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
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snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
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AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
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/* PLL as CODEC_CLKIN */
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snd_soc_update_bits(codec, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
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snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
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AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
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/* DAC_MOD_CLK as BDIV_CLKIN */
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snd_soc_update_bits(codec, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
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snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
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AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
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/* We will fix R value to 1 and will make P & J=K.D as variable */
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snd_soc_update_bits(codec, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
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snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
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/* PLL P value */
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snd_soc_update_bits(codec, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
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snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
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aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
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/* PLL J value */
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snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
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snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
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/* PLL D value */
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snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
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snd_soc_write(codec, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
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snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
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snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
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/* NDAC divider value */
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snd_soc_update_bits(codec, AIC32X4_NDAC,
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snd_soc_component_update_bits(component, AIC32X4_NDAC,
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AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
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/* MDAC divider value */
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snd_soc_update_bits(codec, AIC32X4_MDAC,
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snd_soc_component_update_bits(component, AIC32X4_MDAC,
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AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
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/* DOSR MSB & LSB values */
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snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
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snd_soc_write(codec, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
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snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
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snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
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/* NADC divider value */
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snd_soc_update_bits(codec, AIC32X4_NADC,
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snd_soc_component_update_bits(component, AIC32X4_NADC,
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AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
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/* MADC divider value */
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snd_soc_update_bits(codec, AIC32X4_MADC,
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snd_soc_component_update_bits(component, AIC32X4_MADC,
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AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
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/* AOSR value */
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snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
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snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
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/* BCLK N divider */
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snd_soc_update_bits(codec, AIC32X4_BCLKN,
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snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
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switch (params_width(params)) {
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@ -753,7 +753,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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}
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snd_soc_update_bits(codec, AIC32X4_IFACE1,
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snd_soc_component_update_bits(component, AIC32X4_IFACE1,
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AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
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if (params_channels(params) == 1) {
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@ -764,7 +764,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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else
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dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
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}
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snd_soc_update_bits(codec, AIC32X4_DACSETUP,
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snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
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AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
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return 0;
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@ -772,18 +772,18 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct snd_soc_component *component = dai->component;
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snd_soc_update_bits(codec, AIC32X4_DACMUTE,
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snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
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AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
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return 0;
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}
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static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
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static int aic32x4_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
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struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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int ret;
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switch (level) {
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@ -791,59 +791,59 @@ static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
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/* Switch on master clock */
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ret = clk_prepare_enable(aic32x4->mclk);
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if (ret) {
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dev_err(codec->dev, "Failed to enable master clock\n");
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dev_err(component->dev, "Failed to enable master clock\n");
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return ret;
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}
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/* Switch on PLL */
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snd_soc_update_bits(codec, AIC32X4_PLLPR,
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snd_soc_component_update_bits(component, AIC32X4_PLLPR,
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AIC32X4_PLLEN, AIC32X4_PLLEN);
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/* Switch on NDAC Divider */
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snd_soc_update_bits(codec, AIC32X4_NDAC,
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snd_soc_component_update_bits(component, AIC32X4_NDAC,
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AIC32X4_NDACEN, AIC32X4_NDACEN);
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/* Switch on MDAC Divider */
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snd_soc_update_bits(codec, AIC32X4_MDAC,
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snd_soc_component_update_bits(component, AIC32X4_MDAC,
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AIC32X4_MDACEN, AIC32X4_MDACEN);
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/* Switch on NADC Divider */
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snd_soc_update_bits(codec, AIC32X4_NADC,
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snd_soc_component_update_bits(component, AIC32X4_NADC,
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AIC32X4_NADCEN, AIC32X4_NADCEN);
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/* Switch on MADC Divider */
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snd_soc_update_bits(codec, AIC32X4_MADC,
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snd_soc_component_update_bits(component, AIC32X4_MADC,
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AIC32X4_MADCEN, AIC32X4_MADCEN);
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/* Switch on BCLK_N Divider */
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snd_soc_update_bits(codec, AIC32X4_BCLKN,
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snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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AIC32X4_BCLKEN, AIC32X4_BCLKEN);
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break;
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case SND_SOC_BIAS_PREPARE:
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break;
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case SND_SOC_BIAS_STANDBY:
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/* Switch off BCLK_N Divider */
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snd_soc_update_bits(codec, AIC32X4_BCLKN,
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snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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AIC32X4_BCLKEN, 0);
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/* Switch off MADC Divider */
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snd_soc_update_bits(codec, AIC32X4_MADC,
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snd_soc_component_update_bits(component, AIC32X4_MADC,
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AIC32X4_MADCEN, 0);
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/* Switch off NADC Divider */
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snd_soc_update_bits(codec, AIC32X4_NADC,
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snd_soc_component_update_bits(component, AIC32X4_NADC,
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AIC32X4_NADCEN, 0);
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/* Switch off MDAC Divider */
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snd_soc_update_bits(codec, AIC32X4_MDAC,
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snd_soc_component_update_bits(component, AIC32X4_MDAC,
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AIC32X4_MDACEN, 0);
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/* Switch off NDAC Divider */
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snd_soc_update_bits(codec, AIC32X4_NDAC,
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snd_soc_component_update_bits(component, AIC32X4_NDAC,
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AIC32X4_NDACEN, 0);
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/* Switch off PLL */
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snd_soc_update_bits(codec, AIC32X4_PLLPR,
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snd_soc_component_update_bits(component, AIC32X4_PLLPR,
|
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AIC32X4_PLLEN, 0);
|
||||
|
||||
/* Switch off master clock */
|
||||
@ -884,55 +884,55 @@ static struct snd_soc_dai_driver aic32x4_dai = {
|
||||
.symmetric_rates = 1,
|
||||
};
|
||||
|
||||
static void aic32x4_setup_gpios(struct snd_soc_codec *codec)
|
||||
static void aic32x4_setup_gpios(struct snd_soc_component *component)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
|
||||
|
||||
/* setup GPIO functions */
|
||||
/* MFP1 */
|
||||
if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_write(codec, AIC32X4_DINCTL,
|
||||
snd_soc_component_write(component, AIC32X4_DINCTL,
|
||||
aic32x4->setup->gpio_func[0]);
|
||||
snd_soc_add_codec_controls(codec, aic32x4_mfp1,
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp1,
|
||||
ARRAY_SIZE(aic32x4_mfp1));
|
||||
}
|
||||
|
||||
/* MFP2 */
|
||||
if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_write(codec, AIC32X4_DOUTCTL,
|
||||
snd_soc_component_write(component, AIC32X4_DOUTCTL,
|
||||
aic32x4->setup->gpio_func[1]);
|
||||
snd_soc_add_codec_controls(codec, aic32x4_mfp2,
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp2,
|
||||
ARRAY_SIZE(aic32x4_mfp2));
|
||||
}
|
||||
|
||||
/* MFP3 */
|
||||
if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_write(codec, AIC32X4_SCLKCTL,
|
||||
snd_soc_component_write(component, AIC32X4_SCLKCTL,
|
||||
aic32x4->setup->gpio_func[2]);
|
||||
snd_soc_add_codec_controls(codec, aic32x4_mfp3,
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp3,
|
||||
ARRAY_SIZE(aic32x4_mfp3));
|
||||
}
|
||||
|
||||
/* MFP4 */
|
||||
if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_write(codec, AIC32X4_MISOCTL,
|
||||
snd_soc_component_write(component, AIC32X4_MISOCTL,
|
||||
aic32x4->setup->gpio_func[3]);
|
||||
snd_soc_add_codec_controls(codec, aic32x4_mfp4,
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp4,
|
||||
ARRAY_SIZE(aic32x4_mfp4));
|
||||
}
|
||||
|
||||
/* MFP5 */
|
||||
if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_write(codec, AIC32X4_GPIOCTL,
|
||||
snd_soc_component_write(component, AIC32X4_GPIOCTL,
|
||||
aic32x4->setup->gpio_func[4]);
|
||||
snd_soc_add_codec_controls(codec, aic32x4_mfp5,
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp5,
|
||||
ARRAY_SIZE(aic32x4_mfp5));
|
||||
}
|
||||
}
|
||||
|
||||
static int aic32x4_codec_probe(struct snd_soc_codec *codec)
|
||||
static int aic32x4_component_probe(struct snd_soc_component *component)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
|
||||
u32 tmp_reg;
|
||||
|
||||
if (gpio_is_valid(aic32x4->rstn_gpio)) {
|
||||
@ -940,42 +940,42 @@ static int aic32x4_codec_probe(struct snd_soc_codec *codec)
|
||||
gpio_set_value(aic32x4->rstn_gpio, 1);
|
||||
}
|
||||
|
||||
snd_soc_write(codec, AIC32X4_RESET, 0x01);
|
||||
snd_soc_component_write(component, AIC32X4_RESET, 0x01);
|
||||
|
||||
if (aic32x4->setup)
|
||||
aic32x4_setup_gpios(codec);
|
||||
aic32x4_setup_gpios(component);
|
||||
|
||||
/* Power platform configuration */
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
|
||||
snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
|
||||
snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
|
||||
AIC32X4_MICBIAS_2075V);
|
||||
}
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
|
||||
snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
|
||||
snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
|
||||
|
||||
tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
|
||||
AIC32X4_LDOCTLEN : 0;
|
||||
snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
|
||||
snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
|
||||
|
||||
tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
|
||||
tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
|
||||
tmp_reg |= AIC32X4_LDOIN_18_36;
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
|
||||
tmp_reg |= AIC32X4_LDOIN2HP;
|
||||
snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
|
||||
snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
|
||||
|
||||
/* Mic PGA routing */
|
||||
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
|
||||
snd_soc_write(codec, AIC32X4_LMICPGANIN,
|
||||
snd_soc_component_write(component, AIC32X4_LMICPGANIN,
|
||||
AIC32X4_LMICPGANIN_IN2R_10K);
|
||||
else
|
||||
snd_soc_write(codec, AIC32X4_LMICPGANIN,
|
||||
snd_soc_component_write(component, AIC32X4_LMICPGANIN,
|
||||
AIC32X4_LMICPGANIN_CM1L_10K);
|
||||
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
|
||||
snd_soc_write(codec, AIC32X4_RMICPGANIN,
|
||||
snd_soc_component_write(component, AIC32X4_RMICPGANIN,
|
||||
AIC32X4_RMICPGANIN_IN1L_10K);
|
||||
else
|
||||
snd_soc_write(codec, AIC32X4_RMICPGANIN,
|
||||
snd_soc_component_write(component, AIC32X4_RMICPGANIN,
|
||||
AIC32X4_RMICPGANIN_CM1R_10K);
|
||||
|
||||
/*
|
||||
@ -983,27 +983,28 @@ static int aic32x4_codec_probe(struct snd_soc_codec *codec)
|
||||
* and down for the first capture to work properly. It seems related to
|
||||
* a HW BUG or some kind of behavior not documented in the datasheet.
|
||||
*/
|
||||
tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
|
||||
snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
|
||||
tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
|
||||
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
|
||||
AIC32X4_LADC_EN | AIC32X4_RADC_EN);
|
||||
snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
|
||||
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
|
||||
.probe = aic32x4_codec_probe,
|
||||
.set_bias_level = aic32x4_set_bias_level,
|
||||
.suspend_bias_off = true,
|
||||
|
||||
.component_driver = {
|
||||
.controls = aic32x4_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(aic32x4_snd_controls),
|
||||
.dapm_widgets = aic32x4_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
|
||||
.dapm_routes = aic32x4_dapm_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
|
||||
},
|
||||
static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
|
||||
.probe = aic32x4_component_probe,
|
||||
.set_bias_level = aic32x4_set_bias_level,
|
||||
.controls = aic32x4_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(aic32x4_snd_controls),
|
||||
.dapm_widgets = aic32x4_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
|
||||
.dapm_routes = aic32x4_dapm_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
|
||||
.suspend_bias_off = 1,
|
||||
.idle_bias_on = 1,
|
||||
.use_pmdown_time = 1,
|
||||
.endianness = 1,
|
||||
.non_legacy_dai_naming = 1,
|
||||
};
|
||||
|
||||
static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
|
||||
@ -1181,10 +1182,10 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(dev,
|
||||
&soc_codec_dev_aic32x4, &aic32x4_dai, 1);
|
||||
ret = devm_snd_soc_register_component(dev,
|
||||
&soc_component_dev_aic32x4, &aic32x4_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register codec\n");
|
||||
dev_err(dev, "Failed to register component\n");
|
||||
aic32x4_disable_regulators(aic32x4);
|
||||
return ret;
|
||||
}
|
||||
@ -1199,8 +1200,6 @@ int aic32x4_remove(struct device *dev)
|
||||
|
||||
aic32x4_disable_regulators(aic32x4);
|
||||
|
||||
snd_soc_unregister_codec(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(aic32x4_remove);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user