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Merge patch series "RISC-V: Fixes for riscv_has_extension[un]likely()'s alternative dependency"
Conor Dooley <conor.dooley@microchip.com> says: Here's my attempt at fixing both the use of an FPU on XIP kernels and the issue that Jason ran into where CONFIG_FPU, which needs the alternatives frame work for has_fpu() checks, could be enabled without the alternatives actually being present. For the former, a "slow" fallback that does not use alternatives is added to riscv_has_extension_[un]likely() that can be used with XIP. Obviously, we want to make use of Jisheng's alternatives based approach where possible, so any users of riscv_has_extension_[un]likely() will want to make sure that they select RISCV_ALTERNATIVE. If they don't however, they'll hit the fallback path which (should, sparing a silly mistake from me!) behave in the same way, thus succeeding silently. Sounds like a To prevent "depends on !XIP_KERNEL; select RISCV_ALTERNATIVE" spreading like the plague through the various places that want to check for the presence of extensions, and sidestep the potential silent "success" mentioned above, all users RISCV_ALTERNATIVE are converted from selects to dependencies, with the option being selected for all !XIP_KERNEL builds. I know that the VDSO was a key place that Jisheng wanted to use the new helper rather than static branches, and I think the fallback path should not cause issues there. See the thread at [1] for the prior discussion. 1 - https://lore.kernel.org/linux-riscv/20230128172856.3814-1-jszhang@kernel.org/T/#m21390d570997145d31dd8bb95002fd61f99c6573 [Palmer: these were also merged into fixes, but there's a cleanup that depends on the merge so I'm taking it into for-next as well.] * b4-shazam-merge: RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely() Link: https://lore.kernel.org/r/20230324100538.3514663-1-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> * commit '1ee7fc3f4d0a93831a20d5566f203d5ad6d44de8': RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()
This commit is contained in:
commit
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@ -127,6 +127,7 @@ config RISCV
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select OF_IRQ
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select PCI_DOMAINS_GENERIC if PCI
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select PCI_MSI if PCI
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select RISCV_ALTERNATIVE if !XIP_KERNEL
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select RISCV_INTC
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select RISCV_TIMER if RISCV_SBI
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select SIFIVE_PLIC
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@ -420,9 +421,8 @@ config RISCV_ISA_SVNAPOT
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config RISCV_ISA_SVPBMT
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bool "SVPBMT extension support"
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depends on 64BIT && MMU
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depends on !XIP_KERNEL
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depends on RISCV_ALTERNATIVE
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default y
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select RISCV_ALTERNATIVE
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help
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Adds support to dynamically detect the presence of the SVPBMT
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ISA-extension (Supervisor-mode: page-based memory types) and
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@ -447,8 +447,8 @@ config TOOLCHAIN_HAS_ZBB
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config RISCV_ISA_ZBB
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bool "Zbb extension support for bit manipulation instructions"
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depends on TOOLCHAIN_HAS_ZBB
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depends on !XIP_KERNEL && MMU
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select RISCV_ALTERNATIVE
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depends on MMU
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depends on RISCV_ALTERNATIVE
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default y
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help
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Adds support to dynamically detect the presence of the ZBB
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@ -462,9 +462,9 @@ config RISCV_ISA_ZBB
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config RISCV_ISA_ZICBOM
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bool "Zicbom extension support for non-coherent DMA operation"
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depends on !XIP_KERNEL && MMU
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depends on MMU
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depends on RISCV_ALTERNATIVE
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default y
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select RISCV_ALTERNATIVE
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select RISCV_DMA_NONCOHERENT
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help
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Adds support to dynamically detect the presence of the ZICBOM
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@ -2,8 +2,7 @@ menu "CPU errata selection"
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config ERRATA_SIFIVE
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bool "SiFive errata"
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depends on !XIP_KERNEL
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select RISCV_ALTERNATIVE
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depends on RISCV_ALTERNATIVE
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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@ -35,8 +34,7 @@ config ERRATA_SIFIVE_CIP_1200
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config ERRATA_THEAD
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bool "T-HEAD errata"
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depends on !XIP_KERNEL
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select RISCV_ALTERNATIVE
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depends on RISCV_ALTERNATIVE
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help
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All T-HEAD errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all T-HEAD errata. Please say "Y"
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@ -59,18 +59,31 @@ struct riscv_isa_ext_data {
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unsigned int isa_ext_id;
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};
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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static __always_inline bool
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riscv_has_extension_likely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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asm_volatile_goto(
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ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_no);
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm_volatile_goto(
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ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_no);
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} else {
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if (!__riscv_isa_extension_available(NULL, ext))
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goto l_no;
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}
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return true;
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l_no:
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@ -83,26 +96,23 @@ riscv_has_extension_unlikely(const unsigned long ext)
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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asm_volatile_goto(
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ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_yes);
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm_volatile_goto(
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ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_yes);
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} else {
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if (__riscv_isa_extension_available(NULL, ext))
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goto l_yes;
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}
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return false;
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l_yes:
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return true;
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}
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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#endif
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#endif /* _ASM_RISCV_HWCAP_H */
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