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spi: apple: Add driver for Apple SPI controller
This SPI controller is present in Apple SoCs such as the M1 (t8103) and M1 Pro/Max (t600x). It is a relatively straightforward design with two 16-entry FIFOs, arbitrary transfer sizes (up to 2**32 - 1) and fully configurable word size up to 32 bits. It supports one hardware CS line which can also be driven via the pinctrl/GPIO driver instead, if desired. TX and RX can be independently enabled. There are a surprising number of knobs for tweaking details of the transfer, most of which we do not use right now. Hardware CS control is available, but we haven't found a way to make it stay low across multiple logical transfers, so we just use software CS control for now. There is also a shared DMA offload coprocessor that can be used to handle larger transfers without requiring an IRQ every 8-16 words, but that feature depends on a bunch of scaffolding that isn't ready to be upstreamed yet, so leave it for later. The hardware shares some register bit definitions with spi-s3c24xx which suggests it has a shared legacy with Samsung SoCs, but it is too different to warrant sharing a driver. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://patch.msgid.link/20241106-asahi-spi-v5-2-e81a4f3a8e19@jannau.net Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Hector Martin
Mark Brown
parent
18096d3392
commit
c36212b261
@ -96,6 +96,17 @@ config SPI_AMLOGIC_SPIFC_A1
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This enables master mode support for the SPIFC (SPI flash
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controller) available in Amlogic A1 (A113L SoC).
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config SPI_APPLE
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tristate "Apple SoC SPI Controller platform driver"
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depends on ARCH_APPLE || COMPILE_TEST
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help
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This enables support for the SPI controller present on
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many Apple SoCs, including the t8103 (M1), t8112 (M2)
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and t600x (M1 Pro/Max/Ultra). Multiple SPI controller
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instances are present on the SoC and each connects usually
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to a single device like spi-nor (nvram), input device controller
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or fingerprint sensor.
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config SPI_AR934X
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tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
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depends on ATH79 || COMPILE_TEST
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@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
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obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
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obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
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obj-$(CONFIG_SPI_AMLOGIC_SPIFC_A1) += spi-amlogic-spifc-a1.o
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obj-$(CONFIG_SPI_APPLE) += spi-apple.o
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obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
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obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
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obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
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530
drivers/spi/spi-apple.c
Normal file
530
drivers/spi/spi-apple.c
Normal file
@ -0,0 +1,530 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Apple SoC SPI device driver
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//
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// Copyright The Asahi Linux Contributors
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//
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// Based on spi-sifive.c, Copyright 2018 SiFive, Inc.
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#define APPLE_SPI_CTRL 0x000
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#define APPLE_SPI_CTRL_RUN BIT(0)
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#define APPLE_SPI_CTRL_TX_RESET BIT(2)
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#define APPLE_SPI_CTRL_RX_RESET BIT(3)
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#define APPLE_SPI_CFG 0x004
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#define APPLE_SPI_CFG_CPHA BIT(1)
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#define APPLE_SPI_CFG_CPOL BIT(2)
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#define APPLE_SPI_CFG_MODE GENMASK(6, 5)
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#define APPLE_SPI_CFG_MODE_POLLED 0
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#define APPLE_SPI_CFG_MODE_IRQ 1
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#define APPLE_SPI_CFG_MODE_DMA 2
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#define APPLE_SPI_CFG_IE_RXCOMPLETE BIT(7)
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#define APPLE_SPI_CFG_IE_TXRXTHRESH BIT(8)
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#define APPLE_SPI_CFG_LSB_FIRST BIT(13)
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#define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15)
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#define APPLE_SPI_CFG_WORD_SIZE_8B 0
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#define APPLE_SPI_CFG_WORD_SIZE_16B 1
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#define APPLE_SPI_CFG_WORD_SIZE_32B 2
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#define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17)
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#define APPLE_SPI_CFG_FIFO_THRESH_8B 0
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#define APPLE_SPI_CFG_FIFO_THRESH_4B 1
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#define APPLE_SPI_CFG_FIFO_THRESH_1B 2
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#define APPLE_SPI_CFG_IE_TXCOMPLETE BIT(21)
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#define APPLE_SPI_STATUS 0x008
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#define APPLE_SPI_STATUS_RXCOMPLETE BIT(0)
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#define APPLE_SPI_STATUS_TXRXTHRESH BIT(1)
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#define APPLE_SPI_STATUS_TXCOMPLETE BIT(2)
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#define APPLE_SPI_PIN 0x00c
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#define APPLE_SPI_PIN_KEEP_MOSI BIT(0)
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#define APPLE_SPI_PIN_CS BIT(1)
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#define APPLE_SPI_TXDATA 0x010
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#define APPLE_SPI_RXDATA 0x020
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#define APPLE_SPI_CLKDIV 0x030
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#define APPLE_SPI_CLKDIV_MAX 0x7ff
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#define APPLE_SPI_RXCNT 0x034
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#define APPLE_SPI_WORD_DELAY 0x038
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#define APPLE_SPI_TXCNT 0x04c
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#define APPLE_SPI_FIFOSTAT 0x10c
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#define APPLE_SPI_FIFOSTAT_TXFULL BIT(4)
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#define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8)
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#define APPLE_SPI_FIFOSTAT_RXEMPTY BIT(20)
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#define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24)
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#define APPLE_SPI_IE_XFER 0x130
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#define APPLE_SPI_IF_XFER 0x134
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#define APPLE_SPI_XFER_RXCOMPLETE BIT(0)
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#define APPLE_SPI_XFER_TXCOMPLETE BIT(1)
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#define APPLE_SPI_IE_FIFO 0x138
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#define APPLE_SPI_IF_FIFO 0x13c
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#define APPLE_SPI_FIFO_RXTHRESH BIT(4)
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#define APPLE_SPI_FIFO_TXTHRESH BIT(5)
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#define APPLE_SPI_FIFO_RXFULL BIT(8)
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#define APPLE_SPI_FIFO_TXEMPTY BIT(9)
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#define APPLE_SPI_FIFO_RXUNDERRUN BIT(16)
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#define APPLE_SPI_FIFO_TXOVERFLOW BIT(17)
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#define APPLE_SPI_SHIFTCFG 0x150
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#define APPLE_SPI_SHIFTCFG_CLK_ENABLE BIT(0)
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#define APPLE_SPI_SHIFTCFG_CS_ENABLE BIT(1)
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#define APPLE_SPI_SHIFTCFG_AND_CLK_DATA BIT(8)
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#define APPLE_SPI_SHIFTCFG_CS_AS_DATA BIT(9)
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#define APPLE_SPI_SHIFTCFG_TX_ENABLE BIT(10)
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#define APPLE_SPI_SHIFTCFG_RX_ENABLE BIT(11)
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#define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16)
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#define APPLE_SPI_SHIFTCFG_OVERRIDE_CS BIT(24)
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#define APPLE_SPI_PINCFG 0x154
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#define APPLE_SPI_PINCFG_KEEP_CLK BIT(0)
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#define APPLE_SPI_PINCFG_KEEP_CS BIT(1)
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#define APPLE_SPI_PINCFG_KEEP_MOSI BIT(2)
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#define APPLE_SPI_PINCFG_CLK_IDLE_VAL BIT(8)
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#define APPLE_SPI_PINCFG_CS_IDLE_VAL BIT(9)
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#define APPLE_SPI_PINCFG_MOSI_IDLE_VAL BIT(10)
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#define APPLE_SPI_DELAY_PRE 0x160
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#define APPLE_SPI_DELAY_POST 0x168
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#define APPLE_SPI_DELAY_ENABLE BIT(0)
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#define APPLE_SPI_DELAY_NO_INTERBYTE BIT(1)
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#define APPLE_SPI_DELAY_SET_SCK BIT(4)
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#define APPLE_SPI_DELAY_SET_MOSI BIT(6)
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#define APPLE_SPI_DELAY_SCK_VAL BIT(8)
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#define APPLE_SPI_DELAY_MOSI_VAL BIT(12)
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#define APPLE_SPI_FIFO_DEPTH 16
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/*
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* The slowest refclock available is 24MHz, the highest divider is 0x7ff,
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* the largest word size is 32 bits, the FIFO depth is 16, the maximum
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* intra-word delay is 0xffff refclocks. So the maximum time a transfer
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* cycle can take is:
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*
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* (0x7ff * 32 + 0xffff) * 16 / 24e6 Hz ~= 87ms
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*
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* Double it and round it up to 200ms for good measure.
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*/
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#define APPLE_SPI_TIMEOUT_MS 200
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struct apple_spi {
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void __iomem *regs; /* MMIO register address */
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struct clk *clk; /* bus clock */
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struct completion done; /* wake-up from interrupt */
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};
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static inline void reg_write(struct apple_spi *spi, int offset, u32 value)
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{
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writel_relaxed(value, spi->regs + offset);
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}
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static inline u32 reg_read(struct apple_spi *spi, int offset)
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{
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return readl_relaxed(spi->regs + offset);
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}
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static inline void reg_mask(struct apple_spi *spi, int offset, u32 clear, u32 set)
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{
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u32 val = reg_read(spi, offset);
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val &= ~clear;
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val |= set;
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reg_write(spi, offset, val);
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}
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static void apple_spi_init(struct apple_spi *spi)
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{
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/* Set CS high (inactive) and disable override and auto-CS */
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reg_write(spi, APPLE_SPI_PIN, APPLE_SPI_PIN_CS);
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reg_mask(spi, APPLE_SPI_SHIFTCFG, APPLE_SPI_SHIFTCFG_OVERRIDE_CS, 0);
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reg_mask(spi, APPLE_SPI_PINCFG, APPLE_SPI_PINCFG_CS_IDLE_VAL, APPLE_SPI_PINCFG_KEEP_CS);
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/* Reset FIFOs */
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reg_write(spi, APPLE_SPI_CTRL, APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET);
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/* Configure defaults */
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reg_write(spi, APPLE_SPI_CFG,
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FIELD_PREP(APPLE_SPI_CFG_FIFO_THRESH, APPLE_SPI_CFG_FIFO_THRESH_8B) |
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FIELD_PREP(APPLE_SPI_CFG_MODE, APPLE_SPI_CFG_MODE_IRQ) |
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FIELD_PREP(APPLE_SPI_CFG_WORD_SIZE, APPLE_SPI_CFG_WORD_SIZE_8B));
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/* Disable IRQs */
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reg_write(spi, APPLE_SPI_IE_FIFO, 0);
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reg_write(spi, APPLE_SPI_IE_XFER, 0);
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/* Disable delays */
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reg_write(spi, APPLE_SPI_DELAY_PRE, 0);
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reg_write(spi, APPLE_SPI_DELAY_POST, 0);
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}
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static int apple_spi_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
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{
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struct apple_spi *spi = spi_controller_get_devdata(ctlr);
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struct spi_device *device = msg->spi;
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u32 cfg = ((device->mode & SPI_CPHA ? APPLE_SPI_CFG_CPHA : 0) |
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(device->mode & SPI_CPOL ? APPLE_SPI_CFG_CPOL : 0) |
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(device->mode & SPI_LSB_FIRST ? APPLE_SPI_CFG_LSB_FIRST : 0));
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/* Update core config */
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reg_mask(spi, APPLE_SPI_CFG,
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APPLE_SPI_CFG_CPHA | APPLE_SPI_CFG_CPOL | APPLE_SPI_CFG_LSB_FIRST, cfg);
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return 0;
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}
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static void apple_spi_set_cs(struct spi_device *device, bool is_high)
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{
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struct apple_spi *spi = spi_controller_get_devdata(device->controller);
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reg_mask(spi, APPLE_SPI_PIN, APPLE_SPI_PIN_CS, is_high ? APPLE_SPI_PIN_CS : 0);
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}
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static bool apple_spi_prep_transfer(struct apple_spi *spi, struct spi_transfer *t)
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{
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u32 cr, fifo_threshold;
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/* Calculate and program the clock rate */
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cr = DIV_ROUND_UP(clk_get_rate(spi->clk), t->speed_hz);
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reg_write(spi, APPLE_SPI_CLKDIV, min_t(u32, cr, APPLE_SPI_CLKDIV_MAX));
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/* Update bits per word */
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reg_mask(spi, APPLE_SPI_SHIFTCFG, APPLE_SPI_SHIFTCFG_BITS,
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FIELD_PREP(APPLE_SPI_SHIFTCFG_BITS, t->bits_per_word));
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/* We will want to poll if the time we need to wait is
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* less than the context switching time.
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* Let's call that threshold 5us. The operation will take:
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* bits_per_word * fifo_threshold / hz <= 5 * 10^-6
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* 200000 * bits_per_word * fifo_threshold <= hz
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*/
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fifo_threshold = APPLE_SPI_FIFO_DEPTH / 2;
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return (200000 * t->bits_per_word * fifo_threshold) <= t->speed_hz;
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}
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static irqreturn_t apple_spi_irq(int irq, void *dev_id)
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{
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struct apple_spi *spi = dev_id;
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u32 fifo = reg_read(spi, APPLE_SPI_IF_FIFO) & reg_read(spi, APPLE_SPI_IE_FIFO);
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u32 xfer = reg_read(spi, APPLE_SPI_IF_XFER) & reg_read(spi, APPLE_SPI_IE_XFER);
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if (fifo || xfer) {
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/* Disable interrupts until next transfer */
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reg_write(spi, APPLE_SPI_IE_XFER, 0);
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reg_write(spi, APPLE_SPI_IE_FIFO, 0);
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complete(&spi->done);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int apple_spi_wait(struct apple_spi *spi, u32 fifo_bit, u32 xfer_bit, int poll)
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{
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int ret = 0;
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if (poll) {
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u32 fifo, xfer;
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unsigned long timeout = jiffies + APPLE_SPI_TIMEOUT_MS * HZ / 1000;
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do {
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fifo = reg_read(spi, APPLE_SPI_IF_FIFO);
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xfer = reg_read(spi, APPLE_SPI_IF_XFER);
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if (time_after(jiffies, timeout)) {
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ret = -ETIMEDOUT;
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break;
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}
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} while (!((fifo & fifo_bit) || (xfer & xfer_bit)));
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} else {
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reinit_completion(&spi->done);
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reg_write(spi, APPLE_SPI_IE_XFER, xfer_bit);
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reg_write(spi, APPLE_SPI_IE_FIFO, fifo_bit);
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if (!wait_for_completion_timeout(&spi->done,
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msecs_to_jiffies(APPLE_SPI_TIMEOUT_MS)))
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ret = -ETIMEDOUT;
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reg_write(spi, APPLE_SPI_IE_XFER, 0);
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reg_write(spi, APPLE_SPI_IE_FIFO, 0);
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}
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return ret;
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}
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static void apple_spi_tx(struct apple_spi *spi, const void **tx_ptr, u32 *left,
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unsigned int bytes_per_word)
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{
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u32 inuse, words, wrote;
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if (!*tx_ptr)
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return;
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inuse = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_TX, reg_read(spi, APPLE_SPI_FIFOSTAT));
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words = wrote = min_t(u32, *left, APPLE_SPI_FIFO_DEPTH - inuse);
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if (!words)
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return;
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*left -= words;
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switch (bytes_per_word) {
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case 1: {
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const u8 *p = *tx_ptr;
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while (words--)
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reg_write(spi, APPLE_SPI_TXDATA, *p++);
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break;
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}
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case 2: {
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const u16 *p = *tx_ptr;
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while (words--)
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reg_write(spi, APPLE_SPI_TXDATA, *p++);
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break;
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}
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case 4: {
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const u32 *p = *tx_ptr;
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while (words--)
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reg_write(spi, APPLE_SPI_TXDATA, *p++);
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break;
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}
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default:
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WARN_ON(1);
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}
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*tx_ptr = ((u8 *)*tx_ptr) + bytes_per_word * wrote;
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}
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static void apple_spi_rx(struct apple_spi *spi, void **rx_ptr, u32 *left,
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unsigned int bytes_per_word)
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{
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u32 words, read;
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if (!*rx_ptr)
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return;
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words = read = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_RX, reg_read(spi, APPLE_SPI_FIFOSTAT));
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WARN_ON(words > *left);
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if (!words)
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return;
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*left -= min_t(u32, *left, words);
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switch (bytes_per_word) {
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case 1: {
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u8 *p = *rx_ptr;
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while (words--)
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*p++ = reg_read(spi, APPLE_SPI_RXDATA);
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break;
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}
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case 2: {
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u16 *p = *rx_ptr;
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while (words--)
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*p++ = reg_read(spi, APPLE_SPI_RXDATA);
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break;
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}
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case 4: {
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u32 *p = *rx_ptr;
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while (words--)
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*p++ = reg_read(spi, APPLE_SPI_RXDATA);
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break;
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}
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default:
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WARN_ON(1);
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}
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*rx_ptr = ((u8 *)*rx_ptr) + bytes_per_word * read;
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}
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static int apple_spi_transfer_one(struct spi_controller *ctlr, struct spi_device *device,
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struct spi_transfer *t)
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{
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struct apple_spi *spi = spi_controller_get_devdata(ctlr);
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bool poll = apple_spi_prep_transfer(spi, t);
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const void *tx_ptr = t->tx_buf;
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void *rx_ptr = t->rx_buf;
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unsigned int bytes_per_word;
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u32 words, remaining_tx, remaining_rx;
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u32 xfer_flags = 0;
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||||
u32 fifo_flags;
|
||||
int retries = 100;
|
||||
int ret = 0;
|
||||
|
||||
if (t->bits_per_word > 16)
|
||||
bytes_per_word = 4;
|
||||
else if (t->bits_per_word > 8)
|
||||
bytes_per_word = 2;
|
||||
else
|
||||
bytes_per_word = 1;
|
||||
|
||||
words = t->len / bytes_per_word;
|
||||
remaining_tx = tx_ptr ? words : 0;
|
||||
remaining_rx = rx_ptr ? words : 0;
|
||||
|
||||
/* Reset FIFOs */
|
||||
reg_write(spi, APPLE_SPI_CTRL, APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET);
|
||||
|
||||
/* Clear IRQ flags */
|
||||
reg_write(spi, APPLE_SPI_IF_XFER, ~0);
|
||||
reg_write(spi, APPLE_SPI_IF_FIFO, ~0);
|
||||
|
||||
/* Determine transfer completion flags we wait for */
|
||||
if (tx_ptr)
|
||||
xfer_flags |= APPLE_SPI_XFER_TXCOMPLETE;
|
||||
if (rx_ptr)
|
||||
xfer_flags |= APPLE_SPI_XFER_RXCOMPLETE;
|
||||
|
||||
/* Set transfer length */
|
||||
reg_write(spi, APPLE_SPI_TXCNT, remaining_tx);
|
||||
reg_write(spi, APPLE_SPI_RXCNT, remaining_rx);
|
||||
|
||||
/* Prime transmit FIFO */
|
||||
apple_spi_tx(spi, &tx_ptr, &remaining_tx, bytes_per_word);
|
||||
|
||||
/* Start transfer */
|
||||
reg_write(spi, APPLE_SPI_CTRL, APPLE_SPI_CTRL_RUN);
|
||||
|
||||
/* TX again since a few words get popped off immediately */
|
||||
apple_spi_tx(spi, &tx_ptr, &remaining_tx, bytes_per_word);
|
||||
|
||||
while (xfer_flags) {
|
||||
fifo_flags = 0;
|
||||
|
||||
if (remaining_tx)
|
||||
fifo_flags |= APPLE_SPI_FIFO_TXTHRESH;
|
||||
if (remaining_rx)
|
||||
fifo_flags |= APPLE_SPI_FIFO_RXTHRESH;
|
||||
|
||||
/* Wait for anything to happen */
|
||||
ret = apple_spi_wait(spi, fifo_flags, xfer_flags, poll);
|
||||
if (ret) {
|
||||
dev_err(&ctlr->dev, "transfer timed out (remaining %d tx, %d rx)\n",
|
||||
remaining_tx, remaining_rx);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Stop waiting on transfer halves once they complete */
|
||||
xfer_flags &= ~reg_read(spi, APPLE_SPI_IF_XFER);
|
||||
|
||||
/* Transmit and receive everything we can */
|
||||
apple_spi_tx(spi, &tx_ptr, &remaining_tx, bytes_per_word);
|
||||
apple_spi_rx(spi, &rx_ptr, &remaining_rx, bytes_per_word);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sometimes the transfer completes before the last word is in the RX FIFO.
|
||||
* Normally one retry is all it takes to get the last word out.
|
||||
*/
|
||||
while (remaining_rx && retries--)
|
||||
apple_spi_rx(spi, &rx_ptr, &remaining_rx, bytes_per_word);
|
||||
|
||||
if (remaining_tx)
|
||||
dev_err(&ctlr->dev, "transfer completed with %d words left to transmit\n",
|
||||
remaining_tx);
|
||||
if (remaining_rx)
|
||||
dev_err(&ctlr->dev, "transfer completed with %d words left to receive\n",
|
||||
remaining_rx);
|
||||
|
||||
err:
|
||||
fifo_flags = reg_read(spi, APPLE_SPI_IF_FIFO);
|
||||
WARN_ON(fifo_flags & APPLE_SPI_FIFO_TXOVERFLOW);
|
||||
WARN_ON(fifo_flags & APPLE_SPI_FIFO_RXUNDERRUN);
|
||||
|
||||
/* Stop transfer */
|
||||
reg_write(spi, APPLE_SPI_CTRL, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int apple_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct apple_spi *spi;
|
||||
int ret, irq;
|
||||
struct spi_controller *ctlr;
|
||||
|
||||
ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(struct apple_spi));
|
||||
if (!ctlr)
|
||||
return -ENOMEM;
|
||||
|
||||
spi = spi_controller_get_devdata(ctlr);
|
||||
init_completion(&spi->done);
|
||||
|
||||
spi->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(spi->regs))
|
||||
return PTR_ERR(spi->regs);
|
||||
|
||||
spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);
|
||||
if (IS_ERR(spi->clk))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),
|
||||
"Unable to find or enable bus clock\n");
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, apple_spi_irq, 0,
|
||||
dev_name(&pdev->dev), spi);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret, "Unable to bind to interrupt\n");
|
||||
|
||||
ctlr->dev.of_node = pdev->dev.of_node;
|
||||
ctlr->bus_num = pdev->id;
|
||||
ctlr->num_chipselect = 1;
|
||||
ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
|
||||
ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
||||
ctlr->prepare_message = apple_spi_prepare_message;
|
||||
ctlr->set_cs = apple_spi_set_cs;
|
||||
ctlr->transfer_one = apple_spi_transfer_one;
|
||||
ctlr->auto_runtime_pm = true;
|
||||
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
apple_spi_init(spi);
|
||||
|
||||
ret = devm_spi_register_controller(&pdev->dev, ctlr);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(&pdev->dev, ret, "devm_spi_register_controller failed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id apple_spi_of_match[] = {
|
||||
{ .compatible = "apple,spi", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, apple_spi_of_match);
|
||||
|
||||
static struct platform_driver apple_spi_driver = {
|
||||
.probe = apple_spi_probe,
|
||||
.driver = {
|
||||
.name = "apple-spi",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = apple_spi_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(apple_spi_driver);
|
||||
|
||||
MODULE_AUTHOR("Hector Martin <marcan@marcan.st>");
|
||||
MODULE_DESCRIPTION("Apple SoC SPI driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user