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[SPARC64]: Kill totally unused inline functions from asm/spitfire.h

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Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2005-07-24 19:35:56 -07:00
parent 620de54675
commit c5019a578f
1 changed files with 0 additions and 130 deletions
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130
include/asm-sparc64/spitfire.h
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@ -56,52 +56,6 @@ extern void cheetah_enable_pcache(void);
SPITFIRE_HIGHEST_LOCKED_TLBENT : \ SPITFIRE_HIGHEST_LOCKED_TLBENT : \
CHEETAH_HIGHEST_LOCKED_TLBENT) CHEETAH_HIGHEST_LOCKED_TLBENT)
static __inline__ unsigned long spitfire_get_isfsr(void)
{
unsigned long ret;
__asm__ __volatile__("ldxa [%1] %2, %0"
: "=r" (ret)
: "r" (TLB_SFSR), "i" (ASI_IMMU));
return ret;
}
static __inline__ unsigned long spitfire_get_dsfsr(void)
{
unsigned long ret;
__asm__ __volatile__("ldxa [%1] %2, %0"
: "=r" (ret)
: "r" (TLB_SFSR), "i" (ASI_DMMU));
return ret;
}
static __inline__ unsigned long spitfire_get_sfar(void)
{
unsigned long ret;
__asm__ __volatile__("ldxa [%1] %2, %0"
: "=r" (ret)
: "r" (DMMU_SFAR), "i" (ASI_DMMU));
return ret;
}
static __inline__ void spitfire_put_isfsr(unsigned long sfsr)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
: /* no outputs */
: "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU));
}
static __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
: /* no outputs */
: "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU));
}
/* The data cache is write through, so this just invalidates the /* The data cache is write through, so this just invalidates the
* specified line. * specified line.
*/ */
@ -193,90 +147,6 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
"i" (ASI_ITLB_DATA_ACCESS)); "i" (ASI_ITLB_DATA_ACCESS));
} }
/* Spitfire hardware assisted TLB flushes. */
/* Context level flushes. */
static __inline__ void spitfire_flush_dtlb_primary_context(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (0x40), "i" (ASI_DMMU_DEMAP));
}
static __inline__ void spitfire_flush_itlb_primary_context(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (0x40), "i" (ASI_IMMU_DEMAP));
}
static __inline__ void spitfire_flush_dtlb_secondary_context(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (0x50), "i" (ASI_DMMU_DEMAP));
}
static __inline__ void spitfire_flush_itlb_secondary_context(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (0x50), "i" (ASI_IMMU_DEMAP));
}
static __inline__ void spitfire_flush_dtlb_nucleus_context(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (0x60), "i" (ASI_DMMU_DEMAP));
}
static __inline__ void spitfire_flush_itlb_nucleus_context(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (0x60), "i" (ASI_IMMU_DEMAP));
}
/* Page level flushes. */
static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (page), "i" (ASI_DMMU_DEMAP));
}
static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (page), "i" (ASI_IMMU_DEMAP));
}
static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (page | 0x10), "i" (ASI_DMMU_DEMAP));
}
static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
: /* No outputs */
: "r" (page | 0x10), "i" (ASI_IMMU_DEMAP));
}
static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"