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GPIO: MIPS: lantiq: fix overflow inside stp-xway driver

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The driver was using a 16 bit field for storing the shadow value of the shift
register cascade. This resulted in only the first 2 shift registeres receiving
the correct data. The third shift register would always receive 0x00.

Fix this by using a 32bit field for the shadow value.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
John Crispin 2012-07-11 16:33:43 +02:00
parent 6a88a0f762
commit c9e854cf94
1 changed files with 1 additions and 1 deletions
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2
drivers/gpio/gpio-stp-xway.c
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@ -82,7 +82,7 @@ struct xway_stp {
struct gpio_chip gc;
void __iomem *virt;
u32 edge; /* rising or falling edge triggered shift register */
u16 shadow; /* shadow the shift registers state */
u32 shadow; /* shadow the shift registers state */
u8 groups; /* we can drive 1-3 groups of 8bit each */
u8 dsl; /* the 2 LSBs can be driven by the dsl core */
u8 phy1; /* 3 bits can be driven by phy1 */