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RISC-V: KVM: Add common nested acceleration support
Add a common nested acceleration support which will be shared by all parts of KVM RISC-V. This nested acceleration support detects and enables SBI NACL extension usage based on static keys which ensures minimum impact on the non-nested scenario. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-9-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
Anup Patel
parent
5daf89e73d
commit
d466c19cea
239
arch/riscv/include/asm/kvm_nacl.h
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239
arch/riscv/include/asm/kvm_nacl.h
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@ -0,0 +1,239 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 Ventana Micro Systems Inc.
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*/
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#ifndef __KVM_NACL_H
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#define __KVM_NACL_H
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#include <linux/jump_label.h>
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#include <linux/percpu.h>
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#include <asm/byteorder.h>
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#include <asm/csr.h>
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#include <asm/sbi.h>
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DECLARE_STATIC_KEY_FALSE(kvm_riscv_nacl_available);
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#define kvm_riscv_nacl_available() \
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static_branch_unlikely(&kvm_riscv_nacl_available)
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DECLARE_STATIC_KEY_FALSE(kvm_riscv_nacl_sync_csr_available);
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#define kvm_riscv_nacl_sync_csr_available() \
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static_branch_unlikely(&kvm_riscv_nacl_sync_csr_available)
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DECLARE_STATIC_KEY_FALSE(kvm_riscv_nacl_sync_hfence_available);
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#define kvm_riscv_nacl_sync_hfence_available() \
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static_branch_unlikely(&kvm_riscv_nacl_sync_hfence_available)
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DECLARE_STATIC_KEY_FALSE(kvm_riscv_nacl_sync_sret_available);
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#define kvm_riscv_nacl_sync_sret_available() \
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static_branch_unlikely(&kvm_riscv_nacl_sync_sret_available)
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DECLARE_STATIC_KEY_FALSE(kvm_riscv_nacl_autoswap_csr_available);
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#define kvm_riscv_nacl_autoswap_csr_available() \
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static_branch_unlikely(&kvm_riscv_nacl_autoswap_csr_available)
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struct kvm_riscv_nacl {
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void *shmem;
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phys_addr_t shmem_phys;
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};
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DECLARE_PER_CPU(struct kvm_riscv_nacl, kvm_riscv_nacl);
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void __kvm_riscv_nacl_hfence(void *shmem,
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unsigned long control,
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unsigned long page_num,
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unsigned long page_count);
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int kvm_riscv_nacl_enable(void);
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void kvm_riscv_nacl_disable(void);
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void kvm_riscv_nacl_exit(void);
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int kvm_riscv_nacl_init(void);
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#ifdef CONFIG_32BIT
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#define lelong_to_cpu(__x) le32_to_cpu(__x)
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#define cpu_to_lelong(__x) cpu_to_le32(__x)
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#else
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#define lelong_to_cpu(__x) le64_to_cpu(__x)
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#define cpu_to_lelong(__x) cpu_to_le64(__x)
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#endif
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#define nacl_shmem() \
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this_cpu_ptr(&kvm_riscv_nacl)->shmem
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#define nacl_scratch_read_long(__shmem, __offset) \
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({ \
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unsigned long *__p = (__shmem) + \
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SBI_NACL_SHMEM_SCRATCH_OFFSET + \
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(__offset); \
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lelong_to_cpu(*__p); \
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})
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#define nacl_scratch_write_long(__shmem, __offset, __val) \
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do { \
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unsigned long *__p = (__shmem) + \
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SBI_NACL_SHMEM_SCRATCH_OFFSET + \
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(__offset); \
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*__p = cpu_to_lelong(__val); \
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} while (0)
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#define nacl_scratch_write_longs(__shmem, __offset, __array, __count) \
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do { \
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unsigned int __i; \
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unsigned long *__p = (__shmem) + \
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SBI_NACL_SHMEM_SCRATCH_OFFSET + \
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(__offset); \
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for (__i = 0; __i < (__count); __i++) \
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__p[__i] = cpu_to_lelong((__array)[__i]); \
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} while (0)
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#define nacl_sync_hfence(__e) \
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sbi_ecall(SBI_EXT_NACL, SBI_EXT_NACL_SYNC_HFENCE, \
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(__e), 0, 0, 0, 0, 0)
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#define nacl_hfence_mkconfig(__type, __order, __vmid, __asid) \
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({ \
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unsigned long __c = SBI_NACL_SHMEM_HFENCE_CONFIG_PEND; \
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__c |= ((__type) & SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_MASK) \
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<< SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT; \
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__c |= (((__order) - SBI_NACL_SHMEM_HFENCE_ORDER_BASE) & \
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SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_MASK) \
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<< SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_SHIFT; \
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__c |= ((__vmid) & SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_MASK) \
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<< SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_SHIFT; \
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__c |= ((__asid) & SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_MASK); \
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__c; \
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})
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#define nacl_hfence_mkpnum(__order, __addr) \
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((__addr) >> (__order))
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#define nacl_hfence_mkpcount(__order, __size) \
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((__size) >> (__order))
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#define nacl_hfence_gvma(__shmem, __gpa, __gpsz, __order) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_GVMA, \
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__order, 0, 0), \
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nacl_hfence_mkpnum(__order, __gpa), \
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nacl_hfence_mkpcount(__order, __gpsz))
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#define nacl_hfence_gvma_all(__shmem) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_ALL, \
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0, 0, 0), 0, 0)
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#define nacl_hfence_gvma_vmid(__shmem, __vmid, __gpa, __gpsz, __order) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID, \
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__order, __vmid, 0), \
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nacl_hfence_mkpnum(__order, __gpa), \
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nacl_hfence_mkpcount(__order, __gpsz))
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#define nacl_hfence_gvma_vmid_all(__shmem, __vmid) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID_ALL, \
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0, __vmid, 0), 0, 0)
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#define nacl_hfence_vvma(__shmem, __vmid, __gva, __gvsz, __order) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_VVMA, \
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__order, __vmid, 0), \
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nacl_hfence_mkpnum(__order, __gva), \
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nacl_hfence_mkpcount(__order, __gvsz))
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#define nacl_hfence_vvma_all(__shmem, __vmid) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ALL, \
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0, __vmid, 0), 0, 0)
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#define nacl_hfence_vvma_asid(__shmem, __vmid, __asid, __gva, __gvsz, __order)\
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID, \
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__order, __vmid, __asid), \
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nacl_hfence_mkpnum(__order, __gva), \
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nacl_hfence_mkpcount(__order, __gvsz))
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#define nacl_hfence_vvma_asid_all(__shmem, __vmid, __asid) \
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__kvm_riscv_nacl_hfence(__shmem, \
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nacl_hfence_mkconfig(SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID_ALL, \
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0, __vmid, __asid), 0, 0)
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#define nacl_csr_read(__shmem, __csr) \
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({ \
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unsigned long *__a = (__shmem) + SBI_NACL_SHMEM_CSR_OFFSET; \
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lelong_to_cpu(__a[SBI_NACL_SHMEM_CSR_INDEX(__csr)]); \
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})
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#define nacl_csr_write(__shmem, __csr, __val) \
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do { \
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void *__s = (__shmem); \
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unsigned int __i = SBI_NACL_SHMEM_CSR_INDEX(__csr); \
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unsigned long *__a = (__s) + SBI_NACL_SHMEM_CSR_OFFSET; \
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u8 *__b = (__s) + SBI_NACL_SHMEM_DBITMAP_OFFSET; \
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__a[__i] = cpu_to_lelong(__val); \
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__b[__i >> 3] |= 1U << (__i & 0x7); \
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} while (0)
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#define nacl_csr_swap(__shmem, __csr, __val) \
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({ \
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void *__s = (__shmem); \
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unsigned int __i = SBI_NACL_SHMEM_CSR_INDEX(__csr); \
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unsigned long *__a = (__s) + SBI_NACL_SHMEM_CSR_OFFSET; \
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u8 *__b = (__s) + SBI_NACL_SHMEM_DBITMAP_OFFSET; \
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unsigned long __r = lelong_to_cpu(__a[__i]); \
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__a[__i] = cpu_to_lelong(__val); \
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__b[__i >> 3] |= 1U << (__i & 0x7); \
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__r; \
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})
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#define nacl_sync_csr(__csr) \
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sbi_ecall(SBI_EXT_NACL, SBI_EXT_NACL_SYNC_CSR, \
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(__csr), 0, 0, 0, 0, 0)
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/*
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* Each ncsr_xyz() macro defined below has it's own static-branch so every
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* use of ncsr_xyz() macro emits a patchable direct jump. This means multiple
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* back-to-back ncsr_xyz() macro usage will emit multiple patchable direct
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* jumps which is sub-optimal.
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*
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* Based on the above, it is recommended to avoid multiple back-to-back
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* ncsr_xyz() macro usage.
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*/
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#define ncsr_read(__csr) \
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({ \
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unsigned long __r; \
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if (kvm_riscv_nacl_available()) \
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__r = nacl_csr_read(nacl_shmem(), __csr); \
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else \
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__r = csr_read(__csr); \
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__r; \
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})
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#define ncsr_write(__csr, __val) \
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do { \
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if (kvm_riscv_nacl_sync_csr_available()) \
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nacl_csr_write(nacl_shmem(), __csr, __val); \
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else \
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csr_write(__csr, __val); \
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} while (0)
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#define ncsr_swap(__csr, __val) \
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({ \
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unsigned long __r; \
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if (kvm_riscv_nacl_sync_csr_available()) \
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__r = nacl_csr_swap(nacl_shmem(), __csr, __val); \
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else \
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__r = csr_swap(__csr, __val); \
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__r; \
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})
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#define nsync_csr(__csr) \
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do { \
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if (kvm_riscv_nacl_sync_csr_available()) \
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nacl_sync_csr(__csr); \
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} while (0)
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#endif
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@ -16,6 +16,7 @@ kvm-y += aia_device.o
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kvm-y += aia_imsic.o
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kvm-y += main.o
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kvm-y += mmu.o
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kvm-y += nacl.o
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kvm-y += tlb.o
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kvm-y += vcpu.o
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kvm-y += vcpu_exit.o
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@ -10,8 +10,8 @@
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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#include <asm/cpufeature.h>
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#include <asm/kvm_nacl.h>
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#include <asm/sbi.h>
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long kvm_arch_dev_ioctl(struct file *filp,
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@ -22,6 +22,12 @@ long kvm_arch_dev_ioctl(struct file *filp,
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int kvm_arch_enable_virtualization_cpu(void)
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{
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int rc;
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rc = kvm_riscv_nacl_enable();
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if (rc)
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return rc;
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csr_write(CSR_HEDELEG, KVM_HEDELEG_DEFAULT);
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csr_write(CSR_HIDELEG, KVM_HIDELEG_DEFAULT);
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@ -49,17 +55,21 @@ void kvm_arch_disable_virtualization_cpu(void)
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csr_write(CSR_HVIP, 0);
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csr_write(CSR_HEDELEG, 0);
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csr_write(CSR_HIDELEG, 0);
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kvm_riscv_nacl_disable();
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}
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static void kvm_riscv_teardown(void)
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{
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kvm_riscv_aia_exit();
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kvm_riscv_nacl_exit();
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kvm_unregister_perf_callbacks();
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}
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static int __init riscv_kvm_init(void)
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{
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int rc;
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char slist[64];
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const char *str;
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if (!riscv_isa_extension_available(NULL, h)) {
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@ -77,16 +87,53 @@ static int __init riscv_kvm_init(void)
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return -ENODEV;
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}
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rc = kvm_riscv_nacl_init();
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if (rc && rc != -ENODEV)
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return rc;
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kvm_riscv_gstage_mode_detect();
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kvm_riscv_gstage_vmid_detect();
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rc = kvm_riscv_aia_init();
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if (rc && rc != -ENODEV)
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if (rc && rc != -ENODEV) {
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kvm_riscv_nacl_exit();
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return rc;
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}
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kvm_info("hypervisor extension available\n");
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if (kvm_riscv_nacl_available()) {
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rc = 0;
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slist[0] = '\0';
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if (kvm_riscv_nacl_sync_csr_available()) {
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if (rc)
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strcat(slist, ", ");
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strcat(slist, "sync_csr");
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rc++;
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}
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if (kvm_riscv_nacl_sync_hfence_available()) {
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if (rc)
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strcat(slist, ", ");
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strcat(slist, "sync_hfence");
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rc++;
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}
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if (kvm_riscv_nacl_sync_sret_available()) {
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if (rc)
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strcat(slist, ", ");
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strcat(slist, "sync_sret");
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rc++;
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}
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if (kvm_riscv_nacl_autoswap_csr_available()) {
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if (rc)
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strcat(slist, ", ");
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strcat(slist, "autoswap_csr");
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rc++;
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}
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kvm_info("using SBI nested acceleration with %s\n",
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(rc) ? slist : "no features");
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}
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switch (kvm_riscv_gstage_mode()) {
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case HGATP_MODE_SV32X4:
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str = "Sv32x4";
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152
arch/riscv/kvm/nacl.c
Normal file
152
arch/riscv/kvm/nacl.c
Normal file
@ -0,0 +1,152 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2024 Ventana Micro Systems Inc.
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*/
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#include <linux/kvm_host.h>
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#include <linux/vmalloc.h>
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#include <asm/kvm_nacl.h>
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DEFINE_STATIC_KEY_FALSE(kvm_riscv_nacl_available);
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DEFINE_STATIC_KEY_FALSE(kvm_riscv_nacl_sync_csr_available);
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DEFINE_STATIC_KEY_FALSE(kvm_riscv_nacl_sync_hfence_available);
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DEFINE_STATIC_KEY_FALSE(kvm_riscv_nacl_sync_sret_available);
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DEFINE_STATIC_KEY_FALSE(kvm_riscv_nacl_autoswap_csr_available);
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DEFINE_PER_CPU(struct kvm_riscv_nacl, kvm_riscv_nacl);
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void __kvm_riscv_nacl_hfence(void *shmem,
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unsigned long control,
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unsigned long page_num,
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unsigned long page_count)
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{
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int i, ent = -1, try_count = 5;
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unsigned long *entp;
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again:
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for (i = 0; i < SBI_NACL_SHMEM_HFENCE_ENTRY_MAX; i++) {
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entp = shmem + SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(i);
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if (lelong_to_cpu(*entp) & SBI_NACL_SHMEM_HFENCE_CONFIG_PEND)
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continue;
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ent = i;
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break;
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}
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if (ent < 0) {
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if (try_count) {
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nacl_sync_hfence(-1UL);
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goto again;
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} else {
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pr_warn("KVM: No free entry in NACL shared memory\n");
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return;
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}
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}
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entp = shmem + SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(i);
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*entp = cpu_to_lelong(control);
|
||||
entp = shmem + SBI_NACL_SHMEM_HFENCE_ENTRY_PNUM(i);
|
||||
*entp = cpu_to_lelong(page_num);
|
||||
entp = shmem + SBI_NACL_SHMEM_HFENCE_ENTRY_PCOUNT(i);
|
||||
*entp = cpu_to_lelong(page_count);
|
||||
}
|
||||
|
||||
int kvm_riscv_nacl_enable(void)
|
||||
{
|
||||
int rc;
|
||||
struct sbiret ret;
|
||||
struct kvm_riscv_nacl *nacl;
|
||||
|
||||
if (!kvm_riscv_nacl_available())
|
||||
return 0;
|
||||
nacl = this_cpu_ptr(&kvm_riscv_nacl);
|
||||
|
||||
ret = sbi_ecall(SBI_EXT_NACL, SBI_EXT_NACL_SET_SHMEM,
|
||||
nacl->shmem_phys, 0, 0, 0, 0, 0);
|
||||
rc = sbi_err_map_linux_errno(ret.error);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void kvm_riscv_nacl_disable(void)
|
||||
{
|
||||
if (!kvm_riscv_nacl_available())
|
||||
return;
|
||||
|
||||
sbi_ecall(SBI_EXT_NACL, SBI_EXT_NACL_SET_SHMEM,
|
||||
SBI_SHMEM_DISABLE, SBI_SHMEM_DISABLE, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void kvm_riscv_nacl_exit(void)
|
||||
{
|
||||
int cpu;
|
||||
struct kvm_riscv_nacl *nacl;
|
||||
|
||||
if (!kvm_riscv_nacl_available())
|
||||
return;
|
||||
|
||||
/* Allocate per-CPU shared memory */
|
||||
for_each_possible_cpu(cpu) {
|
||||
nacl = per_cpu_ptr(&kvm_riscv_nacl, cpu);
|
||||
if (!nacl->shmem)
|
||||
continue;
|
||||
|
||||
free_pages((unsigned long)nacl->shmem,
|
||||
get_order(SBI_NACL_SHMEM_SIZE));
|
||||
nacl->shmem = NULL;
|
||||
nacl->shmem_phys = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static long nacl_probe_feature(long feature_id)
|
||||
{
|
||||
struct sbiret ret;
|
||||
|
||||
if (!kvm_riscv_nacl_available())
|
||||
return 0;
|
||||
|
||||
ret = sbi_ecall(SBI_EXT_NACL, SBI_EXT_NACL_PROBE_FEATURE,
|
||||
feature_id, 0, 0, 0, 0, 0);
|
||||
return ret.value;
|
||||
}
|
||||
|
||||
int kvm_riscv_nacl_init(void)
|
||||
{
|
||||
int cpu;
|
||||
struct page *shmem_page;
|
||||
struct kvm_riscv_nacl *nacl;
|
||||
|
||||
if (sbi_spec_version < sbi_mk_version(1, 0) ||
|
||||
sbi_probe_extension(SBI_EXT_NACL) <= 0)
|
||||
return -ENODEV;
|
||||
|
||||
/* Enable NACL support */
|
||||
static_branch_enable(&kvm_riscv_nacl_available);
|
||||
|
||||
/* Probe NACL features */
|
||||
if (nacl_probe_feature(SBI_NACL_FEAT_SYNC_CSR))
|
||||
static_branch_enable(&kvm_riscv_nacl_sync_csr_available);
|
||||
if (nacl_probe_feature(SBI_NACL_FEAT_SYNC_HFENCE))
|
||||
static_branch_enable(&kvm_riscv_nacl_sync_hfence_available);
|
||||
if (nacl_probe_feature(SBI_NACL_FEAT_SYNC_SRET))
|
||||
static_branch_enable(&kvm_riscv_nacl_sync_sret_available);
|
||||
if (nacl_probe_feature(SBI_NACL_FEAT_AUTOSWAP_CSR))
|
||||
static_branch_enable(&kvm_riscv_nacl_autoswap_csr_available);
|
||||
|
||||
/* Allocate per-CPU shared memory */
|
||||
for_each_possible_cpu(cpu) {
|
||||
nacl = per_cpu_ptr(&kvm_riscv_nacl, cpu);
|
||||
|
||||
shmem_page = alloc_pages(GFP_KERNEL | __GFP_ZERO,
|
||||
get_order(SBI_NACL_SHMEM_SIZE));
|
||||
if (!shmem_page) {
|
||||
kvm_riscv_nacl_exit();
|
||||
return -ENOMEM;
|
||||
}
|
||||
nacl->shmem = page_to_virt(shmem_page);
|
||||
nacl->shmem_phys = page_to_phys(shmem_page);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user