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phy fixes for 6.4
- init count imbalance fix in qcom-qmp-pcie and combo drivers - kernel doc header fix for qcom-snps driver - mediatek floating point comparison fix - amlogic fix register value -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmRzk3EACgkQfBQHDyUj g0cU9g/+PeOboaED0BCiX+n6O4yxrD5bdT1hJSEd/lRdogL4Sp9pPYuVOnyKcZrs uQHq0v5BIqWa7dgI+OYB3QL6nsQwNwT5YvDaJlmXRLvmYqyB93gGRVLkTMppEtPU 5zTE3pDj9BIotHH6i8LFhSyeFwxRRgNfYT6AqY1nx/I9KbA6VHBlmJqFAk1L+SZb SKjhK3DQ4ZViWNFUUeVvCcFy/66mm8MEkogGRA6mSkYRHQC5ZIU5QdZZeoXeMbN1 LQcuFonEOqqlzELn4Xujz4JBe9kMy+5zSqY+OSK3c4MjSczesQVaqAyIY7/EmdXa vbfQMfZS2SRtt26ksY2MncLmwoVxDFP0+2FX3rrzpWsaeZ8CiLpkywkkteH2u+6a MYFSeKbqTvnkc2AA4kAcHD5Eodmfe7fBKMCnwQK2bU4bjl+pQwB+8kAMNoNOJLFw KGZIpOUkBO0Za6fXc+QSNiFfgWdLO/SvYgWAldV+BOQgcQhFyFnJlU6GctZ7HzL2 GkHi1gzjCtPgn4lIfz/Nt6JqTFS24lrrreZTdVIybm2wieDOIgQgaYBOUsP9BGAn fPknh4WGayYm3lUBlgxXyxRiMQ3j/Cr9NYghEJPtN+9M5rpbQIu/dfXhtVVfsdSO Gatcrg3vKidbCW9B1xLcjc6iE5ZAfFmzh0ikZfU9O0BCgT9+iKU= =/mmj -----END PGP SIGNATURE----- Merge tag 'phy-fixes-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy fixes from Vinod Koul: - init count imbalance fix in qcom-qmp-pcie and combo drivers - kernel doc header fix for qcom-snps driver - mediatek floating point comparison fix - amlogic fix register value * tag 'phy-fixes-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: qcom-snps: correct struct qcom_snps_hsphy kerneldoc phy: amlogic: phy-meson-g12a-mipi-dphy-analog: fix CNTL2_DIF_TX_CTL0 value phy: mediatek: rework the floating point comparisons to fixed point phy: qcom-qmp-pcie-msm8996: fix init-count imbalance phy: qcom-qmp-combo: fix init-count imbalance
This commit is contained in:
commit
e338142b39
@ -70,7 +70,7 @@ static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
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HHI_MIPI_CNTL1_BANDGAP);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2,
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FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) |
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FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x45a) |
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FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
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reg = DSI_LANE_CLK;
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@ -237,11 +237,11 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
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*/
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if (tmds_clk < 54 * MEGA)
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txposdiv = 8;
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else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA)
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else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA)
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txposdiv = 4;
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else if (tmds_clk >= 148.35 * MEGA && tmds_clk < 296.7 * MEGA)
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else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA)
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txposdiv = 2;
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else if (tmds_clk >= 296.7 * MEGA && tmds_clk <= 594 * MEGA)
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else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA)
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txposdiv = 1;
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else
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return -EINVAL;
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@ -324,12 +324,12 @@ static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw)
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clk_channel_bias = 0x34; /* 20mA */
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impedance_en = 0xf;
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impedance = 0x36; /* 100ohm */
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} else if (pixel_clk >= 74.175 * MEGA && pixel_clk <= 300 * MEGA) {
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} else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) {
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data_channel_bias = 0x34; /* 20mA */
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clk_channel_bias = 0x2c; /* 16mA */
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impedance_en = 0xf;
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impedance = 0x36; /* 100ohm */
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} else if (pixel_clk >= 27 * MEGA && pixel_clk < 74.175 * MEGA) {
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} else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) {
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data_channel_bias = 0x14; /* 10mA */
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clk_channel_bias = 0x14; /* 10mA */
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impedance_en = 0x0;
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@ -2472,7 +2472,7 @@ static int qmp_combo_com_init(struct qmp_combo *qmp)
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ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
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if (ret) {
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dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
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goto err_unlock;
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goto err_decrement_count;
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}
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ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
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@ -2522,7 +2522,8 @@ static int qmp_combo_com_init(struct qmp_combo *qmp)
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reset_control_bulk_assert(cfg->num_resets, qmp->resets);
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err_disable_regulators:
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regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
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err_unlock:
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err_decrement_count:
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qmp->init_count--;
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mutex_unlock(&qmp->phy_mutex);
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return ret;
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@ -379,7 +379,7 @@ static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy)
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ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
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if (ret) {
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dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
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goto err_unlock;
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goto err_decrement_count;
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}
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ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
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@ -409,7 +409,8 @@ static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy)
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reset_control_bulk_assert(cfg->num_resets, qmp->resets);
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err_disable_regulators:
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regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
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err_unlock:
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err_decrement_count:
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qmp->init_count--;
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mutex_unlock(&qmp->phy_mutex);
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return ret;
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@ -115,11 +115,11 @@ struct phy_override_seq {
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*
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* @cfg_ahb_clk: AHB2PHY interface clock
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* @ref_clk: phy reference clock
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* @iface_clk: phy interface clock
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* @phy_reset: phy reset control
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* @vregs: regulator supplies bulk data
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* @phy_initialized: if PHY has been initialized correctly
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* @mode: contains the current mode the PHY is in
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* @update_seq_cfg: tuning parameters for phy init
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*/
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struct qcom_snps_hsphy {
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struct phy *phy;
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