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pwm: axi-pwmgen: Implementation of the waveform callbacks
Convert the axi-pwmgen driver to use the new callbacks for hardware programming. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Tested-by: Trevor Gamblin <tgamblin@baylibre.com> Link: https://lore.kernel.org/r/922277f07b1d1fb9c9cd915b1ec3fdeec888a916.1726819463.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
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@ -23,6 +23,7 @@
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#include <linux/err.h>
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#include <linux/fpga/adi-axi-common.h>
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#include <linux/io.h>
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#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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@ -53,81 +54,142 @@ static const struct regmap_config axi_pwmgen_regmap_config = {
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.max_register = 0xFC,
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};
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static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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/* This represents a hardware configuration for one channel */
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struct axi_pwmgen_waveform {
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u32 period_cnt;
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u32 duty_cycle_cnt;
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u32 duty_offset_cnt;
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};
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static int axi_pwmgen_round_waveform_tohw(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const struct pwm_waveform *wf,
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void *_wfhw)
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{
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struct axi_pwmgen_waveform *wfhw = _wfhw;
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struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
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if (wf->period_length_ns == 0) {
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*wfhw = (struct axi_pwmgen_waveform){
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.period_cnt = 0,
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.duty_cycle_cnt = 0,
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.duty_offset_cnt = 0,
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};
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} else {
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/* With ddata->clk_rate_hz < NSEC_PER_SEC this won't overflow. */
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wfhw->period_cnt = min_t(u64,
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mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
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U32_MAX);
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if (wfhw->period_cnt == 0) {
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/*
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* The specified period is too short for the hardware.
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* Let's round .duty_cycle down to 0 to get a (somewhat)
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* valid result.
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*/
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wfhw->period_cnt = 1;
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wfhw->duty_cycle_cnt = 0;
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wfhw->duty_offset_cnt = 0;
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} else {
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wfhw->duty_cycle_cnt = min_t(u64,
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mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
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U32_MAX);
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wfhw->duty_offset_cnt = min_t(u64,
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mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
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U32_MAX);
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}
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}
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dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> PERIOD: %08x, DUTY: %08x, OFFSET: %08x\n",
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pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
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ddata->clk_rate_hz, wfhw->period_cnt, wfhw->duty_cycle_cnt, wfhw->duty_offset_cnt);
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return 0;
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}
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static int axi_pwmgen_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,
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const void *_wfhw, struct pwm_waveform *wf)
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{
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const struct axi_pwmgen_waveform *wfhw = _wfhw;
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struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
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wf->period_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->period_cnt * NSEC_PER_SEC,
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ddata->clk_rate_hz);
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wf->duty_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_cycle_cnt * NSEC_PER_SEC,
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ddata->clk_rate_hz);
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wf->duty_offset_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_offset_cnt * NSEC_PER_SEC,
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ddata->clk_rate_hz);
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return 0;
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}
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static int axi_pwmgen_write_waveform(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const void *_wfhw)
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{
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const struct axi_pwmgen_waveform *wfhw = _wfhw;
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struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
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unsigned int ch = pwm->hwpwm;
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struct regmap *regmap = ddata->regmap;
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u64 period_cnt, duty_cnt;
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unsigned int ch = pwm->hwpwm;
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int ret;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), wfhw->period_cnt);
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if (ret)
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return ret;
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if (state->enabled) {
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period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC);
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if (period_cnt > UINT_MAX)
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period_cnt = UINT_MAX;
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), wfhw->duty_cycle_cnt);
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if (ret)
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return ret;
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if (period_cnt == 0)
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return -EINVAL;
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt);
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if (ret)
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return ret;
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duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC);
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if (duty_cnt > UINT_MAX)
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duty_cnt = UINT_MAX;
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt);
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if (ret)
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return ret;
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} else {
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0);
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if (ret)
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return ret;
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0);
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if (ret)
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return ret;
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}
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ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), wfhw->duty_offset_cnt);
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if (ret)
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return ret;
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return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG);
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}
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static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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static int axi_pwmgen_read_waveform(struct pwm_chip *chip,
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struct pwm_device *pwm,
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void *_wfhw)
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{
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struct axi_pwmgen_waveform *wfhw = _wfhw;
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struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
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struct regmap *regmap = ddata->regmap;
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unsigned int ch = pwm->hwpwm;
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u32 cnt;
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int ret;
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ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt);
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ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &wfhw->period_cnt);
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if (ret)
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return ret;
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state->enabled = cnt != 0;
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state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
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ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt);
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ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &wfhw->duty_cycle_cnt);
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if (ret)
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return ret;
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state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
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ret = regmap_read(regmap, AXI_PWMGEN_CHX_OFFSET(ch), &wfhw->duty_offset_cnt);
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if (ret)
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return ret;
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state->polarity = PWM_POLARITY_NORMAL;
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if (wfhw->duty_cycle_cnt > wfhw->period_cnt)
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wfhw->duty_cycle_cnt = wfhw->period_cnt;
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/* XXX: is this the actual behaviour of the hardware? */
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if (wfhw->duty_offset_cnt >= wfhw->period_cnt) {
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wfhw->duty_cycle_cnt = 0;
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wfhw->duty_offset_cnt = 0;
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}
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return 0;
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}
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static const struct pwm_ops axi_pwmgen_pwm_ops = {
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.apply = axi_pwmgen_apply,
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.get_state = axi_pwmgen_get_state,
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.sizeof_wfhw = sizeof(struct axi_pwmgen_waveform),
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.round_waveform_tohw = axi_pwmgen_round_waveform_tohw,
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.round_waveform_fromhw = axi_pwmgen_round_waveform_fromhw,
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.read_waveform = axi_pwmgen_read_waveform,
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.write_waveform = axi_pwmgen_write_waveform,
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};
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static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
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