mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-10 23:29:46 +00:00
Merge branch 'for-next/sysreg' into for-next/core
* for-next/sysreg: arm64/sysreg: Convert HFGITR_EL2 to automatic generation arm64/idreg: Don't disable SME when disabling SVE arm64/sysreg: Update ID_AA64PFR1_EL1 for DDI0601 2022-12 arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation arm64/sysreg: allow *Enum blocks in SysregFields blocks
This commit is contained in:
Will Deacon
commit
eeb3557cc1
@ -419,9 +419,6 @@
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#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
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#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
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#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
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#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
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#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
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#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
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#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
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#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
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@ -758,12 +755,6 @@
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#define ICH_VTR_TDS_SHIFT 19
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#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
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/* HFG[WR]TR_EL2 bit definitions */
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#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55
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#define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
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#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
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#define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
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#define ARM64_FEATURE_FIELD_BITS 4
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/* Defined for compatibility only, do not add new users. */
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@ -167,7 +167,7 @@ static const struct {
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} aliases[] __initconst = {
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{ "kvm-arm.mode=nvhe", "id_aa64mmfr1.vh=0" },
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{ "kvm-arm.mode=protected", "id_aa64mmfr1.vh=0" },
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{ "arm64.nosve", "id_aa64pfr0.sve=0 id_aa64pfr1.sme=0" },
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{ "arm64.nosve", "id_aa64pfr0.sve=0" },
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{ "arm64.nosme", "id_aa64pfr1.sme=0" },
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{ "arm64.nobti", "id_aa64pfr1.bt=0" },
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{ "arm64.nopauth",
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@ -4,23 +4,35 @@
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#
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# Usage: awk -f gen-sysreg.awk sysregs.txt
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function block_current() {
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return __current_block[__current_block_depth];
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}
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# Log an error and terminate
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function fatal(msg) {
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print "Error at " NR ": " msg > "/dev/stderr"
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printf "Current block nesting:"
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for (i = 0; i <= __current_block_depth; i++) {
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printf " " __current_block[i]
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}
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printf "\n"
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exit 1
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}
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# Sanity check that the start or end of a block makes sense at this point in
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# the file. If not, produce an error and terminate.
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#
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# @this - the $Block or $EndBlock
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# @prev - the only valid block to already be in (value of @block)
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# @new - the new value of @block
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function change_block(this, prev, new) {
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if (block != prev)
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fatal("unexpected " this " (inside " block ")")
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# Enter a new block, setting the active block to @block
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function block_push(block) {
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__current_block[++__current_block_depth] = block
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}
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block = new
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# Exit a block, setting the active block to the parent block
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function block_pop() {
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if (__current_block_depth == 0)
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fatal("error: block_pop() in root block")
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__current_block_depth--;
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}
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# Sanity check the number of records for a field makes sense. If not, produce
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@ -84,10 +96,14 @@ BEGIN {
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print "/* Generated file - do not edit */"
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print ""
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block = "None"
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__current_block_depth = 0
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__current_block[__current_block_depth] = "Root"
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}
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END {
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if (__current_block_depth != 0)
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fatal("Missing terminator for " block_current() " block")
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print "#endif /* __ASM_SYSREG_DEFS_H */"
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}
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@ -95,8 +111,9 @@ END {
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/^$/ { next }
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/^[\t ]*#/ { next }
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/^SysregFields/ {
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change_block("SysregFields", "None", "SysregFields")
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/^SysregFields/ && block_current() == "Root" {
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block_push("SysregFields")
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expect_fields(2)
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reg = $2
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@ -110,12 +127,10 @@ END {
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next
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}
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/^EndSysregFields/ {
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/^EndSysregFields/ && block_current() == "SysregFields" {
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if (next_bit > 0)
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fatal("Unspecified bits in " reg)
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change_block("EndSysregFields", "SysregFields", "None")
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define(reg "_RES0", "(" res0 ")")
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define(reg "_RES1", "(" res1 ")")
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define(reg "_UNKN", "(" unkn ")")
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@ -126,11 +141,13 @@ END {
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res1 = null
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unkn = null
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block_pop()
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next
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}
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/^Sysreg/ {
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change_block("Sysreg", "None", "Sysreg")
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/^Sysreg/ && block_current() == "Root" {
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block_push("Sysreg")
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expect_fields(7)
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reg = $2
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@ -160,12 +177,10 @@ END {
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next
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}
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/^EndSysreg/ {
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/^EndSysreg/ && block_current() == "Sysreg" {
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if (next_bit > 0)
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fatal("Unspecified bits in " reg)
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change_block("EndSysreg", "Sysreg", "None")
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if (res0 != null)
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define(reg "_RES0", "(" res0 ")")
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if (res1 != null)
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@ -185,12 +200,13 @@ END {
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res1 = null
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unkn = null
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block_pop()
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next
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}
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# Currently this is effectivey a comment, in future we may want to emit
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# defines for the fields.
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/^Fields/ && (block == "Sysreg") {
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/^Fields/ && block_current() == "Sysreg" {
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expect_fields(2)
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if (next_bit != 63)
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@ -208,7 +224,7 @@ END {
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}
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/^Res0/ && (block == "Sysreg" || block == "SysregFields") {
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/^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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expect_fields(2)
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parse_bitdef(reg, "RES0", $2)
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field = "RES0_" msb "_" lsb
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@ -218,7 +234,7 @@ END {
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next
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}
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/^Res1/ && (block == "Sysreg" || block == "SysregFields") {
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/^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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expect_fields(2)
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parse_bitdef(reg, "RES1", $2)
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field = "RES1_" msb "_" lsb
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@ -228,7 +244,7 @@ END {
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next
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}
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/^Unkn/ && (block == "Sysreg" || block == "SysregFields") {
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/^Unkn/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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expect_fields(2)
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parse_bitdef(reg, "UNKN", $2)
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field = "UNKN_" msb "_" lsb
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@ -238,7 +254,7 @@ END {
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next
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}
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/^Field/ && (block == "Sysreg" || block == "SysregFields") {
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/^Field/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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expect_fields(3)
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field = $3
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parse_bitdef(reg, field, $2)
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@ -249,15 +265,16 @@ END {
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next
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}
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/^Raz/ && (block == "Sysreg" || block == "SysregFields") {
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/^Raz/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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expect_fields(2)
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parse_bitdef(reg, field, $2)
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next
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}
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/^SignedEnum/ {
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change_block("Enum<", "Sysreg", "Enum")
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/^SignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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block_push("Enum")
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expect_fields(3)
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field = $3
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parse_bitdef(reg, field, $2)
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@ -268,8 +285,9 @@ END {
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next
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}
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/^UnsignedEnum/ {
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change_block("Enum<", "Sysreg", "Enum")
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/^UnsignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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block_push("Enum")
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expect_fields(3)
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field = $3
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parse_bitdef(reg, field, $2)
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@ -280,8 +298,9 @@ END {
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next
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}
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/^Enum/ {
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change_block("Enum", "Sysreg", "Enum")
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/^Enum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
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block_push("Enum")
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expect_fields(3)
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field = $3
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parse_bitdef(reg, field, $2)
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@ -291,16 +310,18 @@ END {
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next
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}
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/^EndEnum/ {
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change_block("EndEnum", "Enum", "Sysreg")
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/^EndEnum/ && block_current() == "Enum" {
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field = null
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msb = null
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lsb = null
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print ""
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block_pop()
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next
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}
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/0b[01]+/ && block == "Enum" {
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/0b[01]+/ && block_current() == "Enum" {
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expect_fields(2)
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val = $1
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name = $2
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@ -879,7 +879,30 @@ EndEnum
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EndSysreg
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Sysreg ID_AA64PFR1_EL1 3 0 0 4 1
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Res0 63:40
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UnsignedEnum 63:60 PFAR
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 59:56 DF2
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 55:52 MTEX
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0b0000 MTE
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0b0001 MTE4
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EndEnum
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UnsignedEnum 51:48 THE
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 47:44 GCS
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 43:40 MTE_frac
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0b0000 ASYNC
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0b1111 NI
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EndEnum
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UnsignedEnum 39:36 NMI
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0b0000 NI
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0b0001 IMP
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@ -1866,6 +1889,146 @@ Field 1 ZA
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Field 0 SM
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EndSysreg
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SysregFields HFGxTR_EL2
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Field 63 nAMIAIR2_EL1
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Field 62 nMAIR2_EL1
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Field 61 nS2POR_EL1
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Field 60 nPOR_EL1
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Field 59 nPOR_EL0
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Field 58 nPIR_EL1
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Field 57 nPIRE0_EL1
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Field 56 nRCWMASK_EL1
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Field 55 nTPIDR2_EL0
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Field 54 nSMPRI_EL1
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Field 53 nGCS_EL1
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Field 52 nGCS_EL0
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Res0 51
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Field 50 nACCDATA_EL1
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Field 49 ERXADDR_EL1
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Field 48 EXRPFGCDN_EL1
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Field 47 EXPFGCTL_EL1
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Field 46 EXPFGF_EL1
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Field 45 ERXMISCn_EL1
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Field 44 ERXSTATUS_EL1
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Field 43 ERXCTLR_EL1
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Field 42 ERXFR_EL1
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Field 41 ERRSELR_EL1
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Field 40 ERRIDR_EL1
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Field 39 ICC_IGRPENn_EL1
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Field 38 VBAR_EL1
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Field 37 TTBR1_EL1
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Field 36 TTBR0_EL1
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Field 35 TPIDR_EL0
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Field 34 TPIDRRO_EL0
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Field 33 TPIDR_EL1
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Field 32 TCR_EL1
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Field 31 SCTXNUM_EL0
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Field 30 SCTXNUM_EL1
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Field 29 SCTLR_EL1
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Field 28 REVIDR_EL1
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Field 27 PAR_EL1
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Field 26 MPIDR_EL1
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Field 25 MIDR_EL1
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Field 24 MAIR_EL1
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Field 23 LORSA_EL1
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Field 22 LORN_EL1
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Field 21 LORID_EL1
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Field 20 LOREA_EL1
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Field 19 LORC_EL1
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Field 18 ISR_EL1
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Field 17 FAR_EL1
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Field 16 ESR_EL1
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Field 15 DCZID_EL0
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Field 14 CTR_EL0
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Field 13 CSSELR_EL1
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Field 12 CPACR_EL1
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Field 11 CONTEXTIDR_EL1
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Field 10 CLIDR_EL1
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Field 9 CCSIDR_EL1
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Field 8 APIBKey
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Field 7 APIAKey
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Field 6 APGAKey
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Field 5 APDBKey
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Field 4 APDAKey
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Field 3 AMAIR_EL1
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Field 2 AIDR_EL1
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Field 1 AFSR1_EL1
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Field 0 AFSR0_EL1
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EndSysregFields
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Sysreg HFGRTR_EL2 3 4 1 1 4
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Fields HFGxTR_EL2
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EndSysreg
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Sysreg HFGWTR_EL2 3 4 1 1 5
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Fields HFGxTR_EL2
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EndSysreg
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Sysreg HFGITR_EL2 3 4 1 1 6
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Res0 63:61
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Field 60 COSPRCTX
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Field 59 nGCSEPP
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Field 58 nGCSSTR_EL1
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Field 57 nGCSPUSHM_EL1
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Field 56 nBRBIALL
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Field 55 nBRBINJ
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Field 54 DCCVAC
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Field 53 SVC_EL1
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Field 52 SVC_EL0
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Field 51 ERET
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Field 50 CPPRCTX
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Field 49 DVPRCTX
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Field 48 CFPRCTX
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Field 47 TLBIVAALE1
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Field 46 TLBIVALE1
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Field 45 TLBIVAAE1
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Field 44 TLBIASIDE1
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Field 43 TLBIVAE1
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Field 42 TLBIVMALLE1
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Field 41 TLBIRVAALE1
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Field 40 TLBIRVALE1
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Field 39 TLBIRVAAE1
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Field 38 TLBIRVAE1
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Field 37 TLBIRVAALE1IS
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Field 36 TLBIRVALE1IS
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Field 35 TLBIRVAAE1IS
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Field 34 TLBIRVAE1IS
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Field 33 TLBIVAALE1IS
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Field 32 TLBIVALE1IS
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Field 31 TLBIVAAE1IS
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Field 30 TLBIASIDE1IS
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Field 29 TLBIVAE1IS
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Field 28 TLBIVMALLE1IS
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Field 27 TLBIRVAALE1OS
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Field 26 TLBIRVALE1OS
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Field 25 TLBIRVAAE1OS
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Field 24 TLBIRVAE1OS
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Field 23 TLBIVAALE1OS
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Field 22 TLBIVALE1OS
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Field 21 TLBIVAAE1OS
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Field 20 TLBIASIDE1OS
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Field 19 TLBIVAE1OS
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Field 18 TLBIVMALLE1OS
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Field 17 ATS1E1WP
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Field 16 ATS1E1RP
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Field 15 ATS1E0W
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Field 14 ATS1E0R
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Field 13 ATS1E1W
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Field 12 ATS1E1R
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Field 11 DCZVA
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Field 10 DCCIVAC
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Field 9 DCCVADP
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Field 8 DCCVAP
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Field 7 DCCVAU
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Field 6 DCCISW
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Field 5 DCCSW
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Field 4 DCISW
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Field 3 DCIVAC
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Field 2 ICIVAU
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Field 1 ICIALLU
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Field 0 ICIALLUIS
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EndSysreg
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Sysreg ZCR_EL2 3 4 1 2 0
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Fields ZCR_ELx
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EndSysreg
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