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cpufreq: stats: Add memory barrier to store_reset()
There is nothing to prevent the CPU or the compiler from reordering the writes to stats->reset_time and stats->reset_pending in store_reset(), in which case the readers of stats->reset_time may see a stale value. Moreover, on 32-bit arches the write to reset_time cannot be completed in one go, so the readers of it may see a partially updated value in that case. To prevent that from happening, add a write memory barrier between the writes to stats->reset_time and stats->reset_pending in store_reset() and corresponding read memory barrier in the readers of stats->reset_time. Fixes: 40c3bd4cfa6f ("cpufreq: stats: Defer stats update to cpufreq_stats_record_transition()") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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@ -47,6 +47,11 @@ static void cpufreq_stats_reset_table(struct cpufreq_stats *stats)
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/* Adjust for the time elapsed since reset was requested */
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WRITE_ONCE(stats->reset_pending, 0);
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/*
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* Prevent the reset_time read from being reordered before the
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* reset_pending accesses in cpufreq_stats_record_transition().
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*/
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smp_rmb();
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cpufreq_stats_update(stats, READ_ONCE(stats->reset_time));
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}
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@ -71,10 +76,16 @@ static ssize_t show_time_in_state(struct cpufreq_policy *policy, char *buf)
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for (i = 0; i < stats->state_num; i++) {
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if (pending) {
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if (i == stats->last_index)
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if (i == stats->last_index) {
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/*
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* Prevent the reset_time read from occurring
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* before the reset_pending read above.
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*/
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smp_rmb();
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time = get_jiffies_64() - READ_ONCE(stats->reset_time);
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else
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} else {
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time = 0;
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}
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} else {
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time = stats->time_in_state[i];
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if (i == stats->last_index)
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@ -99,6 +110,11 @@ static ssize_t store_reset(struct cpufreq_policy *policy, const char *buf,
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* avoid races.
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*/
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WRITE_ONCE(stats->reset_time, get_jiffies_64());
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/*
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* The memory barrier below is to prevent the readers of reset_time from
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* seeing a stale or partially updated value.
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*/
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smp_wmb();
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WRITE_ONCE(stats->reset_pending, 1);
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return count;
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