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irqchip/gic-v4.1: Allow direct invalidation of VLPIs

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Just like for INVALL, GICv4.1 has grown a VPE-aware INVLPI register.
Let's plumb it in and make use of the DirectLPI code in that case.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20191224111055.11836-16-maz@kernel.org
This commit is contained in:
Marc Zyngier 2019-12-24 11:10:38 +00:00
parent 3858d4dfdf
commit f4a81f5a85
2 changed files with 37 additions and 19 deletions
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55
drivers/irqchip/irq-gic-v3-its.c
View File

@ -227,11 +227,27 @@ static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
return &its_dev->event_map.vlpi_maps[event]; return &its_dev->event_map.vlpi_maps[event];
} }
static struct its_collection *irq_to_col(struct irq_data *d) static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
{
if (irqd_is_forwarded_to_vcpu(d)) {
struct its_device *its_dev = irq_data_get_irq_chip_data(d);
u32 event = its_get_event_id(d);
return dev_event_to_vlpi_map(its_dev, event);
}
return NULL;
}
static int irq_to_cpuid(struct irq_data *d)
{ {
struct its_device *its_dev = irq_data_get_irq_chip_data(d); struct its_device *its_dev = irq_data_get_irq_chip_data(d);
struct its_vlpi_map *map = get_vlpi_map(d);
return dev_event_to_col(its_dev, its_get_event_id(d)); if (map)
return map->vpe->col_idx;
return its_dev->event_map.col_map[its_get_event_id(d)];
} }
static struct its_collection *valid_col(struct its_collection *col) static struct its_collection *valid_col(struct its_collection *col)
@ -1269,18 +1285,6 @@ static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
/* /*
* irqchip functions - assumes MSI, mostly. * irqchip functions - assumes MSI, mostly.
*/ */
static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
{
if (irqd_is_forwarded_to_vcpu(d)) {
struct its_device *its_dev = irq_data_get_irq_chip_data(d);
u32 event = its_get_event_id(d);
return dev_event_to_vlpi_map(its_dev, event);
}
return NULL;
}
static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
{ {
struct its_vlpi_map *map = get_vlpi_map(d); struct its_vlpi_map *map = get_vlpi_map(d);
@ -1323,13 +1327,25 @@ static void wait_for_syncr(void __iomem *rdbase)
static void direct_lpi_inv(struct irq_data *d) static void direct_lpi_inv(struct irq_data *d)
{ {
struct its_collection *col; struct its_vlpi_map *map = get_vlpi_map(d);
void __iomem *rdbase; void __iomem *rdbase;
u64 val;
if (map) {
struct its_device *its_dev = irq_data_get_irq_chip_data(d);
WARN_ON(!is_v4_1(its_dev->its));
val = GICR_INVLPIR_V;
val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
} else {
val = d->hwirq;
}
/* Target the redistributor this LPI is currently routed to */ /* Target the redistributor this LPI is currently routed to */
col = irq_to_col(d); rdbase = per_cpu_ptr(gic_rdists->rdist, irq_to_cpuid(d))->rd_base;
rdbase = per_cpu_ptr(gic_rdists->rdist, col->col_id)->rd_base; gic_write_lpir(val, rdbase + GICR_INVLPIR);
gic_write_lpir(d->hwirq, rdbase + GICR_INVLPIR);
wait_for_syncr(rdbase); wait_for_syncr(rdbase);
} }
@ -1339,7 +1355,8 @@ static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
struct its_device *its_dev = irq_data_get_irq_chip_data(d); struct its_device *its_dev = irq_data_get_irq_chip_data(d);
lpi_write_config(d, clr, set); lpi_write_config(d, clr, set);
if (gic_rdists->has_direct_lpi && !irqd_is_forwarded_to_vcpu(d)) if (gic_rdists->has_direct_lpi &&
(is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
direct_lpi_inv(d); direct_lpi_inv(d);
else if (!irqd_is_forwarded_to_vcpu(d)) else if (!irqd_is_forwarded_to_vcpu(d))
its_send_inv(its_dev, its_get_event_id(d)); its_send_inv(its_dev, its_get_event_id(d));

1
include/linux/irqchip/arm-gic-v3.h
View File

@ -247,6 +247,7 @@
#define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24) #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
#define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32) #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
#define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32) #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
#define GICR_INVLPIR_V GENMASK_ULL(63, 63) #define GICR_INVLPIR_V GENMASK_ULL(63, 63)