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staging: sm750fb: restructure multi-line comments to follow CodingStyle
Eliminates all checkpatch.pl BLOCK_COMMENT_STYLE warnings in sm750fb, and coincidentally eliminates some line-length (80) warnings. Signed-off-by: Eric S. Stone <esstone@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Eric S. Stone
Greg Kroah-Hartman
parent
57935a3f87
commit
f5016082f6
@ -1,16 +1,16 @@
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/*
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* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
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*
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* All rights are reserved. Reproduction or in part is prohibited
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* without the written consent of the copyright owner.
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*
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* RegSC.h --- SM718 SDK
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* This file contains the definitions for the System Configuration registers.
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*/
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#ifndef DDK750_H__
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#define DDK750_H__
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/*******************************************************************
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*
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* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
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*
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* All rights are reserved. Reproduction or in part is prohibited
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* without the written consent of the copyright owner.
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*
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* RegSC.h --- SM718 SDK
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* This file contains the definitions for the System Configuration registers.
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*
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*******************************************************************/
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#include "ddk750_reg.h"
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#include "ddk750_mode.h"
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#include "ddk750_chip.h"
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@ -62,17 +62,18 @@ static void set_chip_clock(unsigned int frequency)
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if (frequency) {
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/*
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* Set up PLL, a structure to hold the value to be set in clocks.
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*/
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* Set up PLL structure to hold the value to be set in clocks.
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*/
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pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
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pll.clockType = MXCLK_PLL;
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/*
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* Call calc_pll_value() to fill the other fields of PLL structure.
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* Sometime, the chip cannot set up the exact clock
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* required by the User.
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* Return value of calc_pll_value gives the actual possible clock.
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*/
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* Call calc_pll_value() to fill the other fields of the PLL
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* structure. Sometimes, the chip cannot set up the exact
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* clock required by the User.
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* Return value of calc_pll_value gives the actual possible
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* clock.
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*/
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ulActualMxClk = calc_pll_value(frequency, &pll);
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/* Master Clock Control: MXCLK_PLL */
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@ -84,7 +85,8 @@ static void set_memory_clock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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/* Cheok_0509: For SM750LE, the memory clock is fixed.
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/*
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* Cheok_0509: For SM750LE, the memory clock is fixed.
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* Nothing to set.
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*/
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if (sm750_get_chip_type() == SM750LE)
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@ -135,14 +137,16 @@ static void set_master_clock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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/* Cheok_0509: For SM750LE, the memory clock is fixed.
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/*
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* Cheok_0509: For SM750LE, the memory clock is fixed.
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* Nothing to set.
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*/
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if (sm750_get_chip_type() == SM750LE)
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return;
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if (frequency) {
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/* Set the frequency to the maximum frequency
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/*
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* Set the frequency to the maximum frequency
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* that the SM750 engine can run, which is about 190 MHz.
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*/
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if (frequency > MHz(190))
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@ -241,7 +245,8 @@ int ddk750_init_hw(struct initchip_param *pInitParam)
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set_master_clock(MHz(pInitParam->masterClock));
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/* Reset the memory controller.
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/*
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* Reset the memory controller.
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* If the memory controller is not reset in SM750,
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* the system might hang when sw accesses the memory.
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* The memory should be resetted after changing the MXCLK.
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@ -306,7 +311,8 @@ int ddk750_init_hw(struct initchip_param *pInitParam)
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*/
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unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
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{
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/* as sm750 register definition,
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/*
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* as sm750 register definition,
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* N located in 2,15 and M located in 1,255
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*/
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int N, M, X, d;
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@ -318,7 +324,8 @@ unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
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int max_d = 6;
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if (sm750_get_chip_type() == SM750LE) {
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/* SM750LE don't have
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/*
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* SM750LE don't have
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* programmable PLL and M/N values to work on.
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* Just return the requested clock.
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*/
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@ -330,14 +337,16 @@ unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
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request = request_orig / 1000;
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input = pll->inputFreq / 1000;
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/* for MXCLK register,
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/*
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* for MXCLK register,
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* no POD provided, so need be treated differently
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*/
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if (pll->clockType == MXCLK_PLL)
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max_d = 3;
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for (N = 15; N > 1; N--) {
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/* RN will not exceed maximum long
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/*
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* RN will not exceed maximum long
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* if @request <= 285 MHZ (for 32bit cpu)
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*/
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RN = N * request;
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@ -46,31 +46,42 @@ struct pll_value {
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/* input struct to initChipParam() function */
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struct initchip_param {
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unsigned short powerMode; /* Use power mode 0 or 1 */
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unsigned short chipClock; /**
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* Speed of main chip clock in MHz unit
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* 0 = keep the current clock setting
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* Others = the new main chip clock
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*/
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unsigned short memClock; /**
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* Speed of memory clock in MHz unit
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* 0 = keep the current clock setting
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* Others = the new memory clock
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*/
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unsigned short masterClock; /**
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* Speed of master clock in MHz unit
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* 0 = keep the current clock setting
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* Others = the new master clock
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*/
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unsigned short setAllEngOff; /**
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* 0 = leave all engine state untouched.
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* 1 = make sure they are off: 2D, Overlay,
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* video alpha, alpha, hardware cursors
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*/
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unsigned char resetMemory; /**
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* 0 = Do not reset the memory controller
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* 1 = Reset the memory controller
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*/
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/* Use power mode 0 or 1 */
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unsigned short powerMode;
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/*
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* Speed of main chip clock in MHz unit
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* 0 = keep the current clock setting
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* Others = the new main chip clock
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*/
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unsigned short chipClock;
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/*
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* Speed of memory clock in MHz unit
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* 0 = keep the current clock setting
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* Others = the new memory clock
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*/
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unsigned short memClock;
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/*
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* Speed of master clock in MHz unit
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* 0 = keep the current clock setting
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* Others = the new master clock
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*/
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unsigned short masterClock;
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/*
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* 0 = leave all engine state untouched.
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* 1 = make sure they are off: 2D, Overlay,
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* video alpha, alpha, hardware cursors
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*/
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unsigned short setAllEngOff;
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/*
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* 0 = Do not reset the memory controller
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* 1 = Reset the memory controller
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*/
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unsigned char resetMemory;
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/* More initialization parameter can be added if needed */
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};
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@ -1,7 +1,8 @@
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#ifndef DDK750_DISPLAY_H__
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#define DDK750_DISPLAY_H__
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/* panel path select
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/*
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* panel path select
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* 80000[29:28]
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*/
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@ -12,7 +13,8 @@
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#define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE)
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/* primary timing & plane enable bit
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/*
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* primary timing & plane enable bit
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* 1: 80000[8] & 80000[2] on
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* 0: both off
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*/
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@ -23,7 +25,8 @@
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#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)
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/* panel sequency status
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/*
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* panel sequency status
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* 80000[27:24]
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*/
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#define PNL_SEQ_OFFSET 6
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@ -32,7 +35,8 @@
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#define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
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#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
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/* dual digital output
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/*
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* dual digital output
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* 80000[19]
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*/
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#define DUAL_TFT_OFFSET 8
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@ -41,7 +45,8 @@
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#define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
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#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
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/* secondary timing & plane enable bit
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/*
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* secondary timing & plane enable bit
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* 1:80200[8] & 80200[2] on
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* 0: both off
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*/
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@ -51,7 +56,8 @@
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#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
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#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
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/* crt path select
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/*
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* crt path select
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* 80200[19:18]
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*/
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#define CRT_2_OFFSET 2
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@ -61,7 +67,8 @@
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#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)
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/* DAC affect both DVI and DSUB
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/*
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* DAC affect both DVI and DSUB
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* 4[20]
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*/
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#define DAC_OFFSET 7
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@ -70,7 +77,8 @@
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#define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
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#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
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/* DPMS only affect D-SUB head
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/*
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* DPMS only affect D-SUB head
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* 0[31:30]
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*/
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#define DPMS_OFFSET 9
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@ -81,7 +89,8 @@
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/* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
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/*
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* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
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* CRT means crt path DSUB
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*/
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typedef enum _disp_output_t {
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@ -89,7 +98,8 @@ typedef enum _disp_output_t {
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do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
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do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
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do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
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/* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
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/*
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* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
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* do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON,
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*/
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do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
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@ -20,7 +20,8 @@ unsigned char bus_speed_mode
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value |= (GPIO_MUX_30 | GPIO_MUX_31);
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POKE32(GPIO_MUX, value);
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/* Enable Hardware I2C power.
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/*
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* Enable Hardware I2C power.
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* TODO: Check if we need to enable GPIO power?
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*/
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enableI2C(1);
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@ -92,7 +93,8 @@ static unsigned int hw_i2c_write_data(
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/* Set the Device Address */
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POKE32(I2C_SLAVE_ADDRESS, addr & ~0x01);
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/* Write data.
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/*
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* Write data.
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* Note:
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* Only 16 byte can be accessed per i2c start instruction.
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*/
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@ -158,7 +160,8 @@ static unsigned int hw_i2c_read_data(
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/* Set the Device Address */
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POKE32(I2C_SLAVE_ADDRESS, addr | 0x01);
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/* Read data and save them to the buffer.
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/*
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* Read data and save them to the buffer.
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* Note:
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* Only 16 byte can be accessed per i2c start instruction.
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*/
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@ -3,7 +3,8 @@
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#include "ddk750_mode.h"
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#include "ddk750_chip.h"
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/* SM750LE only:
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/*
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* SM750LE only:
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* This function takes care extra registers and bit fields required to set
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* up a mode in SM750LE
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*
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@ -18,7 +19,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
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x = pModeParam->horizontal_display_end;
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y = pModeParam->vertical_display_end;
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/* SM750LE has to set up the top-left and bottom-right
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/*
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* SM750LE has to set up the top-left and bottom-right
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* registers as well.
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* Note that normal SM750/SM718 only use those two register for
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* auto-centering mode.
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@ -30,7 +32,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
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CRT_AUTO_CENTERING_BR_BOTTOM_MASK) |
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((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK));
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/* Assume common fields in dispControl have been properly set before
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/*
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* Assume common fields in dispControl have been properly set before
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* calling this function.
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* This function only sets the extra fields in dispControl.
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*/
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@ -176,14 +179,14 @@ static int programModeRegisters(mode_parameter_t *pModeParam,
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DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING |
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DISPLAY_CTRL_PLANE);
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/* May a hardware bug or just my test chip (not confirmed).
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* PANEL_DISPLAY_CTRL register seems requiring few writes
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* before a value can be successfully written in.
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* Added some masks to mask out the reserved bits.
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* Note: This problem happens by design. The hardware will wait for the
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* next vertical sync to turn on/off the plane.
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*/
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/*
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* May a hardware bug or just my test chip (not confirmed).
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* PANEL_DISPLAY_CTRL register seems requiring few writes
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* before a value can be successfully written in.
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* Added some masks to mask out the reserved bits.
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* Note: This problem happens by design. The hardware will wait
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* for the next vertical sync to turn on/off the plane.
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*/
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POKE32(PANEL_DISPLAY_CTRL, tmp | reg);
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while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) !=
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@ -173,7 +173,8 @@ long sii164InitChip(
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i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
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/* De-skew enabled with default 111b value.
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/*
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* De-skew enabled with default 111b value.
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* This fixes some artifacts problem in some mode on board 2.2.
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* Somehow this fix does not affect board 2.1.
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*/
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@ -1,21 +1,20 @@
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/*******************************************************************
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*
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* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
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*
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* All rights are reserved. Reproduction or in part is prohibited
|
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* without the written consent of the copyright owner.
|
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*
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* swi2c.c --- SM750/SM718 DDK
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* This file contains the source code for I2C using software
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* implementation.
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*
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*******************************************************************/
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/*
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* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
|
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*
|
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* All rights are reserved. Reproduction or in part is prohibited
|
||||
* without the written consent of the copyright owner.
|
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*
|
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* swi2c.c --- SM750/SM718 DDK
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* This file contains the source code for I2C using software
|
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* implementation.
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*/
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#include "ddk750_chip.h"
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#include "ddk750_reg.h"
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#include "ddk750_swi2c.h"
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#include "ddk750_power.h"
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/*******************************************************************
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/*
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* I2C Software Master Driver:
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* ===========================
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* Each i2c cycle is split into 4 sections. Each of these section marks
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@ -51,7 +50,7 @@
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* SCL | L | | H | |
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* ---------------+---+---+---+---+
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*
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******************************************************************/
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*/
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/* GPIO pins used for this I2C. It ranges from 0 to 63. */
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static unsigned char sw_i2c_clk_gpio = DEFAULT_I2C_SCL;
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@ -1,15 +1,15 @@
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/*******************************************************************
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*
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* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
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*
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* All rights are reserved. Reproduction or in part is prohibited
|
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* without the written consent of the copyright owner.
|
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*
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* swi2c.h --- SM750/SM718 DDK
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* This file contains the definitions for i2c using software
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* implementation.
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*
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*******************************************************************/
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/*
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* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
|
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*
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* All rights are reserved. Reproduction or in part is prohibited
|
||||
* without the written consent of the copyright owner.
|
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*
|
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* swi2c.h --- SM750/SM718 DDK
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* This file contains the definitions for i2c using software
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* implementation.
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*
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*/
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#ifndef _SWI2C_H_
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#define _SWI2C_H_
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@ -146,14 +146,16 @@ struct lynxfb_crtc {
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struct lynxfb_output {
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int dpms;
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int paths;
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/* which paths(s) this output stands for,for sm750:
|
||||
/*
|
||||
* which paths(s) this output stands for,for sm750:
|
||||
* paths=1:means output for panel paths
|
||||
* paths=2:means output for crt paths
|
||||
* paths=3:means output for both panel and crt paths
|
||||
*/
|
||||
|
||||
int *channel;
|
||||
/* which channel these outputs linked with,for sm750:
|
||||
/*
|
||||
* which channel these outputs linked with,for sm750:
|
||||
* *channel=0 means primary channel
|
||||
* *channel=1 means secondary channel
|
||||
* output->channel ==> &crtc->channel
|
||||
|
||||
@ -65,7 +65,8 @@ void hw_de_init(struct lynx_accel *accel)
|
||||
write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr);
|
||||
}
|
||||
|
||||
/* set2dformat only be called from setmode functions
|
||||
/*
|
||||
* set2dformat only be called from setmode functions
|
||||
* but if you need dual framebuffer driver,need call set2dformat
|
||||
* every time you use 2d function
|
||||
*/
|
||||
@ -90,7 +91,8 @@ int hw_fillrect(struct lynx_accel *accel,
|
||||
u32 deCtrl;
|
||||
|
||||
if (accel->de_wait() != 0) {
|
||||
/* int time wait and always busy,seems hardware
|
||||
/*
|
||||
* int time wait and always busy,seems hardware
|
||||
* got something error
|
||||
*/
|
||||
pr_debug("De engine always busy\n");
|
||||
@ -213,25 +215,29 @@ unsigned int rop2) /* ROP value */
|
||||
opSign = (-1);
|
||||
}
|
||||
|
||||
/* Note:
|
||||
/*
|
||||
* Note:
|
||||
* DE_FOREGROUND are DE_BACKGROUND are don't care.
|
||||
* DE_COLOR_COMPARE and DE_COLOR_COMPARE_MAKS
|
||||
* are set by set deSetTransparency().
|
||||
*/
|
||||
|
||||
/* 2D Source Base.
|
||||
/*
|
||||
* 2D Source Base.
|
||||
* It is an address offset (128 bit aligned)
|
||||
* from the beginning of frame buffer.
|
||||
*/
|
||||
write_dpr(accel, DE_WINDOW_SOURCE_BASE, sBase); /* dpr40 */
|
||||
|
||||
/* 2D Destination Base.
|
||||
/*
|
||||
* 2D Destination Base.
|
||||
* It is an address offset (128 bit aligned)
|
||||
* from the beginning of frame buffer.
|
||||
*/
|
||||
write_dpr(accel, DE_WINDOW_DESTINATION_BASE, dBase); /* dpr44 */
|
||||
|
||||
/* Program pitch (distance between the 1st points of two adjacent lines).
|
||||
/*
|
||||
* Program pitch (distance between the 1st points of two adjacent lines).
|
||||
* Note that input pitch is BYTE value, but the 2D Pitch register uses
|
||||
* pixel values. Need Byte to pixel conversion.
|
||||
*/
|
||||
@ -240,7 +246,8 @@ unsigned int rop2) /* ROP value */
|
||||
DE_PITCH_DESTINATION_MASK) |
|
||||
(sPitch / Bpp & DE_PITCH_SOURCE_MASK)); /* dpr10 */
|
||||
|
||||
/* Screen Window width in Pixels.
|
||||
/*
|
||||
* Screen Window width in Pixels.
|
||||
* 2D engine uses this value to calculate the linear address in frame buffer
|
||||
* for a given point.
|
||||
*/
|
||||
@ -316,7 +323,8 @@ int hw_imageblit(struct lynx_accel *accel,
|
||||
if (accel->de_wait() != 0)
|
||||
return -1;
|
||||
|
||||
/* 2D Source Base.
|
||||
/*
|
||||
* 2D Source Base.
|
||||
* Use 0 for HOST Blt.
|
||||
*/
|
||||
write_dpr(accel, DE_WINDOW_SOURCE_BASE, 0);
|
||||
@ -326,16 +334,19 @@ int hw_imageblit(struct lynx_accel *accel,
|
||||
* from the beginning of frame buffer.
|
||||
*/
|
||||
write_dpr(accel, DE_WINDOW_DESTINATION_BASE, dBase);
|
||||
/* Program pitch (distance between the 1st points of two adjacent lines).
|
||||
* Note that input pitch is BYTE value, but the 2D Pitch register uses
|
||||
* pixel values. Need Byte to pixel conversion.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Program pitch (distance between the 1st points of two adjacent
|
||||
* lines). Note that input pitch is BYTE value, but the 2D Pitch
|
||||
* register uses pixel values. Need Byte to pixel conversion.
|
||||
*/
|
||||
write_dpr(accel, DE_PITCH,
|
||||
((dPitch / bytePerPixel << DE_PITCH_DESTINATION_SHIFT) &
|
||||
DE_PITCH_DESTINATION_MASK) |
|
||||
(dPitch / bytePerPixel & DE_PITCH_SOURCE_MASK)); /* dpr10 */
|
||||
|
||||
/* Screen Window width in Pixels.
|
||||
/*
|
||||
* Screen Window width in Pixels.
|
||||
* 2D engine uses this value to calculate the linear address
|
||||
* in frame buffer for a given point.
|
||||
*/
|
||||
@ -344,7 +355,8 @@ int hw_imageblit(struct lynx_accel *accel,
|
||||
DE_WINDOW_WIDTH_DST_MASK) |
|
||||
(dPitch / bytePerPixel & DE_WINDOW_WIDTH_SRC_MASK));
|
||||
|
||||
/* Note: For 2D Source in Host Write, only X_K1_MONO field is needed,
|
||||
/*
|
||||
* Note: For 2D Source in Host Write, only X_K1_MONO field is needed,
|
||||
* and Y_K2 field is not used.
|
||||
* For mono bitmap, use startBit for X_K1.
|
||||
*/
|
||||
|
||||
@ -36,7 +36,8 @@ int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
|
||||
|
||||
pr_info("mmio phyAddr = %lx\n", sm750_dev->vidreg_start);
|
||||
|
||||
/* reserve the vidreg space of smi adaptor
|
||||
/*
|
||||
* reserve the vidreg space of smi adaptor
|
||||
* if you do this, you need to add release region code
|
||||
* in lynxfb_remove, or memory will not be mapped again
|
||||
* successfully
|
||||
@ -65,7 +66,8 @@ int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
|
||||
sm750_set_chip_type(sm750_dev->devid, sm750_dev->revid);
|
||||
|
||||
sm750_dev->vidmem_start = pci_resource_start(pdev, 0);
|
||||
/* don't use pdev_resource[x].end - resource[x].start to
|
||||
/*
|
||||
* don't use pdev_resource[x].end - resource[x].start to
|
||||
* calculate the resource size, it's only the maximum available
|
||||
* size but not the actual size, using
|
||||
* @ddk750_get_vm_size function can be safe.
|
||||
@ -144,7 +146,8 @@ int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
|
||||
}
|
||||
POKE32(PANEL_DISPLAY_CTRL, val);
|
||||
} else {
|
||||
/* for 750LE, no DVI chip initialization
|
||||
/*
|
||||
* for 750LE, no DVI chip initialization
|
||||
* makes Monitor no signal
|
||||
*
|
||||
* Set up GPIO for software I2C to program DVI chip in the
|
||||
@ -152,13 +155,15 @@ int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
|
||||
*/
|
||||
sm750_sw_i2c_init(0, 1);
|
||||
|
||||
/* Customer may NOT use CH7301 DVI chip, which has to be
|
||||
/*
|
||||
* Customer may NOT use CH7301 DVI chip, which has to be
|
||||
* initialized differently.
|
||||
*/
|
||||
if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) {
|
||||
/* The following register values for CH7301 are from
|
||||
* Chrontel app note and our experiment.
|
||||
*/
|
||||
/*
|
||||
* The following register values for CH7301 are from
|
||||
* Chrontel app note and our experiment.
|
||||
*/
|
||||
pr_info("yes,CH7301 DVI chip found\n");
|
||||
sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16);
|
||||
sm750_sw_i2c_write_reg(0xec, 0x21, 0x9);
|
||||
@ -311,7 +316,8 @@ int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc,
|
||||
crtc->oScreen & PANEL_FB_ADDRESS_ADDRESS_MASK);
|
||||
|
||||
reg = var->xres * (var->bits_per_pixel >> 3);
|
||||
/* crtc->channel is not equal to par->index on numeric,
|
||||
/*
|
||||
* crtc->channel is not equal to par->index on numeric,
|
||||
* be aware of that
|
||||
*/
|
||||
reg = ALIGN(reg, crtc->line_pad);
|
||||
@ -345,7 +351,8 @@ int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc,
|
||||
/* not implemented now */
|
||||
POKE32(CRT_FB_ADDRESS, crtc->oScreen);
|
||||
reg = var->xres * (var->bits_per_pixel >> 3);
|
||||
/* crtc->channel is not equal to par->index on numeric,
|
||||
/*
|
||||
* crtc->channel is not equal to par->index on numeric,
|
||||
* be aware of that
|
||||
*/
|
||||
reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user