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iio: frequency: admv4420: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: b59c041559 ("iio: frequency: admv4420.c: Add support for ADMV4420")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-71-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:50 +01:00
parent a3e38a557a
commit f890aaac77
1 changed files with 1 additions and 1 deletions
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2
drivers/iio/frequency/admv4420.c
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@ -113,7 +113,7 @@ struct admv4420_state {
struct admv4420_n_counter n_counter;
enum admv4420_mux_sel mux_sel;
struct mutex lock;
u8 transf_buf[4] ____cacheline_aligned;
u8 transf_buf[4] __aligned(IIO_DMA_MINALIGN);
};
static const struct regmap_config admv4420_regmap_config = {