This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2,
MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624
MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To
make switching frequencies faster, we ping-pong between MMPLL2
and MMPLL8 when we're switching between frequencies that aren't
the maximum. Implement custom rcg clk ops for this type of
frequency switching.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for configuring rates of, enabling, and disabling
Alpha PLLs. This is sufficient for the types of PLLs found in
the global and multimedia clock controllers.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
When we use a clk divider with a divider table, we limit the
maximum divider value in divider_get_val() to the
div_mask(width), but when we calculate the divider in
divider_round_rate() we don't consider that the maximum divider
may be limited by the width. Pass the width along to
_get_table_maxdiv() so that we only return the maximum divider
that is valid. This is useful for clocks that want to share the
same divider table while limiting the available dividers to some
subset of the table depending on the width of the bitfield.
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
for_each_available_child_of_node performs an of_node_get on each iteration,
so a break out of the loop requires an of_node_put.
The semantic patch that fixes this problem is as follows
(http://coccinelle.lip6.fr):
// <smpl>
@@
expression root,e;
local idexpression child;
@@
for_each_available_child_of_node(root, child) {
... when != of_node_put(child)
when != e = child
(
return child;
|
+ of_node_put(child);
? return ...;
)
...
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
If get_pll_div() fails we exited by returning NULL but we missed
releasing hwc.
Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
do_div() is meant to be used with an unsigned dividend.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
do_div() is meant to be used with an unsigned dividend.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The word "cases" is doubled. Keep decent forms for the following
lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Errata i810 states that DPLL controller can get stuck while transitioning
to a power saving state, while its M/N ratio is being re-programmed.
As a workaround, before re-programming the M/N ratio, SW has to ensure
the DPLL cannot start an idle state transition. SW can disable DPLL
idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
active by setting a dependent clock domain in SW_WKUP.
This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The common clk implementation for MMP broke without anyone noticing
when we stopped including linux/clk.h from the clk-provider header.
This did not show up in the defconfig builds because those use the
legacy MMP clk drivers, and it did not show up in my randconfig tests
either because I was testing with my mmp multiplatform series
applied, which at some point gained the fixup.
This fixes the three broken files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 61ae76563ec3 ("clk: Remove clk.h from clk-provider.h")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add 'is_prepared' callback function for pllv3 type clk to make sure when
the system is bootup, the unused clk is in a known state to match the
prepare count info.
Signed-off-by: Bai Ping <b51503@freescale.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The 'osc' clock is already initialized by the fixed clock defined in
imx25.dtsi. The imx25 clock driver tries to add this clock for a second
time and fails with -EEXIST:
i.MX clk 1: register failed with -17
As the clock is already properly setup in DT with a different driver, we
can completely remove the handling in the imx25 clock driver.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
TI's mux and divider clock drivers do not require locking and they do
not initialize internal spinlocks. This code was occasionally
copy-posted from generic mux/divider drivers. So remove it.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add missing clkdev dmtimer related entries for dm816x.
32Khz and ext sources were missing.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Set the newly added id for the crypto clk, so that it can be called
in other parts.
Signed-off-by: Zain Wang <zain.wang@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Move the xo and sleep clocks to device-tree, instead of hard-coding
them in the driver. This allows us to insert the RPM clocks (if they
are enabled) in between the on-board oscillators and the actual clock.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clk_hw_omap_ops structures are never modified, so declare this one as
const, like the others.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
BCM63138 has a simple clocking domain which is primarily the ARMPLL
clocking complex, from which the ARM (CPU), APB and AXI clocks would be
derived from.
Since the ARMPLL controller is entirely compatible with the iProc ARM
PLL, we just initialize it without additional parameters.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
All these clock controllers are little endian devices, but so far
we've been relying on the regmap mmio bus handling this for us
without explicitly stating that fact. After commit 4a98da2164cf
(regmap-mmio: Use native endianness for read/write, 2015-10-29),
the regmap mmio bus will read/write with the __raw_*() IO
accessors, instead of using the readl/writel() APIs that do
proper byte swapping for little endian devices.
So if we're running on a big endian processor and haven't
specified the endianness explicitly in the regmap config or in
DT, we're going to switch from doing little endian byte swapping
to big endian accesses without byte swapping, leading to some
confusing results. On my apq8074 dragonboard, this causes the
device to fail to boot as we access the clock controller with
big endian IO accesses even though the device is little endian.
Specify the endianness explicitly so that the regmap core
properly byte swaps the accesses for us.
Reported-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Cc: Simon Arlott <simon@fire.lp0.eu>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
quadfs_pll_fs660c32_round_rate prints a few structure members
that are never initialized, and also doesn't print the only one
it cares about. We get a gcc warning about the ones that
are printed:
clk/st/clkgen-fsyn.c:560:93: warning: 'params.sdiv' may be used uninitialized in this function
clk/st/clkgen-fsyn.c:560:93: warning: 'params.mdiv' may be used uninitialized in this function
clk/st/clkgen-fsyn.c:560:93: warning: 'params.pe' may be used uninitialized in this function
clk/st/clkgen-fsyn.c:560:93: warning: 'params.nsdiv' may be used uninitialized in this function
This changes the code to no longer print uninitialized data, and
for good measure it also prints the ndiv member that is being
set.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 5f7aa9071e93 ("clk: st: Support for QUADFS inside ClockGenB/C/D/E/F")
Acked-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
hang") added a workaround for the slow clock as it is not properly handled
by its users.
Now that the slow clock is taken properly by the drivers, this workaround
is not necessary anymore, revert it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The X-Gene clock driver missed the divider shift operation when
set the divider value.
Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This is according to figure 12 ("I2C Programming Procedure") in
"Si5351A/B/C Data Sheet"
(https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf).
Without the PLL soft reset, we were unable to get three outputs
working at the same time.
According to Silicon Labs support, performing PLL soft reset will only
be noticeable if the PLL parameters have been changed.
Signed-off-by: Jacob Siverskog <jacob@teenage.engineering>
Signed-off-by: Jens Rudberg <jens@teenage.engineering>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This minor refactoring does not change the function behavior.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This if-block can be dropped because the of_parse_phandle_with_args()
in the following line returns -EINVAL for negative index.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
If kzalloc fails we will already have many messages in the log and we do
not need another message to know that kzalloc for sp810 has failed.
Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
PLLM is fixed for Tegra30 up through Tegra114. Starting with Tegra124
PLLM can change rate. Mark PLLM as TEGRA_PLL_FIXED for the generations
where it should be. Modify the check in clk_pll_round_rate() and
clk_pll_recalc_rate() to allow for the non-fixed version to return the
correct rate.
Note that there is no change for Tegra20. This is because PLLM is not
distinguished in that driver, and adding either the PLLM or FIXED_RATE
flags will cause potential problems.
PLLM never supported dynamic ramping. On Tegra20 and Tegra30, there is
no dynamic ramping at all, and on Tegra114, Tegra124 and Tegra132, only
PLLX and PLLC support dynamic ramping, so we can go ahead and remove the
specialized pllm_ops.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.
Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
setting all the other fields.
In order to prevent regressions on earlier SoC generations, all of the
frequency tables need to be updated so that they contain the actual
divider values. If they contain hardware values these would be converted
to hardware values again, yielding the wrong value.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: fix regressions on earlier SoC generations]
Signed-off-by: Thierry Reding <treding@nvidia.com>
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
For Tegra210, the logic to calculate out-of-table rates is different
from previous generations. Add callbacks that can be overridden to
allow for different ways of calculating rates. Default to
_cal_rate when not specified.
This patch also includes a new flag which is used to set which method
of fixed_mdiv calculation is used. The new method for calculating the
fixed divider value for M can be more accurate especially when
fractional dividers are in play. This allows for older chipsets to use
the existing logic and new generations to use a newer version which
may work better for them.
Based on original work by Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
SoC specific drivers should define the appropriate flags for each
PLL rather than relying on the registration functions to automatically
set flags on their behalf. This will properly allow for changes between
SoC generations where flags might be different and allow sharing the
same logic functions.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Swap out the generic WARN_ON with a WARN which gives more information
about what is happening.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
