Add arch timer node to enable arch-timer support. MT8127 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add arch timer node to enable arch-timer support. MT8135 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit add new cpu enable method "mediatek,mt65xx-smp" and
"mediatek,mt81xx-tz-smp".
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add clocks needed by Mediatek VENC and VENC_LT power domianis.
These clocks were needed by accessing subsystem's registers,
so they need to be enabled before power on these subsystems.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add compatible string for mt8127, mt8135 and mt8173 and sort
the list.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This cosmetic patch reorder nodes under internal-regs by increasing
address order, as expected.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
By default, armada-370-xp.dtsi file has internal RTC enabled.
NETGEAR ReadyNAS 102, 104 and 2120 all use an Intersil ISL12057
I2C RTC chip. The internal RTC not being disabled in the .dts
files of those devices result in the following useless first
line during boot:
[ 4.500056] rtc-mv d0010300.rtc: internal RTC not ticking
[ 4.505684] i2c /dev entries driver
[ 4.513246] rtc-isl12057 0-0068: rtc core: registered rtc-isl12057 as rtc0
This patch marks Armada internal RTC as disabled in individual .dts
files of those devices.
Reported-by: TuxOholic <tuxoholic@hotmail.de>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch adds DT support for the Seagate Personal Cloud 1 and 2-Bay.
Here are some information allowing to identify these devices:
Product name | Personal Cloud | Personal Cloud 2-Bay
Code name (board/PCB) | Cumulus | Cumulus Max
Model name (case sticker) | SRN21C | SRN22C
Material desc (product spec) | STCRxxxxxxx | STCSxxxxxxx
Chipset list:
- SoC Marvell Armada 370 88F6707, CPU @1GHz
- SDRAM memory: 512MB DDR3 667MHz (16-bits bandwidth)
- SPI flash 1MB (Macronix MX25L8006E)
- 1 or 2 SATA internal ports
- 1 Ethernet Gigabit port (PHY Marvell 88E1518)
- 1 USB3 host port (PCIe controller ASM1042)
- 1 USB2 host port (SoC)
- 2 push buttons (power and reset)
- 1 SATA LED (bi-color, white and red)
Note that support for the white SATA LED is missing. A dedicated LED
driver is needed.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch adds DT support for the Seagate NAS 2 and 4-Bay.
Here are some information allowing to identify these devices:
Product name | Seagate NAS 2-Bay | Seagate NAS 4-Bay
Code name (board/PCB) | Dart 2-Bay | Dart 4-Bay
Model name (case sticker) | SRPD20 | SRPD40
Material desc (product spec) | STCTxxxxxxx | STCUxxxxxxx
Chipset list (common):
- SoC Marvell Armada 370 88F6707, CPU @1.2GHz
- SDRAM memory: 512MB DDR3 600MHz (16-bits bandwidth)
- NAND flash 256MB, 8-bits (Micron MT29F2G08AAB or Hinyx H27U2G8F2CTR-BC)
- 2 SATA II ports (SoC)
- 1 Ethernet Gigabit ports (PHY Marvell 88E1518)
- 2 USB3 host ports (PCIe controller ASM1042)
- GPIO fan (4 speeds)
- External I2C RTC (MCP7940NT)
- 3 push buttons (power, backup and reset)
- 2 SATA LEDs (bi-color, blue and red)
- 1 power LED (bi-color, blue and red)
Only on 4-Bay models:
- 2 extra SATA III ports (PCIe AHCI controller Marvell 88SE9170)
- 1 extra Ethernet Gigabit ports (PHY Marvell 88E1518)
- I2C GPIO expander (PCA9554A)
- 2 extra SATA LEDs (bi-color, blue and red)
Note that support for the white SATA LEDs associated with HDDs 0 and 1
is missing. A dedicated LED driver is needed.
Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.
We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.
So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
All A13 based q8 formfactor tablets use the same backlight setup, add
a backlight devicetree node for controlling the backlight on these devices.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Q8 format tablets use channel 0 of the PWM controller for backlight dimming.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add a pinmux setting for the first pwm channel. This is often used for
backlight dimming on tablets.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add dts nodes for the PWM controller on the A13 / A10s.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The AXP22x family of PMIC is used with some Allwinner SoCs. This
includes the AXP221, AXP221s and AXP223. They differ in the host
interface, maximum supply current for DCDC1 regulator, and default
voltage and state for various LDO regulators. Also, the AXP221s
does not support fine calibration of the battery fuel gauge.
This patch adds a dtsi file for all the common bindings for these
PMICs. Currently this is just listing all the regulator nodes. The
regulators are initialized based on their device node names.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Enable the PCIe controller and clock for the Porter board.
This patch is analogous to the commit 485f3ce67c11 ("ARM: shmobile:
henninger: Enable PCIe Controller & PCIe bus clock") as there are no
differences between the boards in this respect.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Porter board dependent part of the QSPI device node.
Add device nodes for Spansion S25FL512S SPI flash and the MTD partitions
on it.
This patch is mostly analogous to the commit f59838d44835 ("ARM:
shmobile: henninger: add QSPI DT support") as there are no differences
between the boards in this respect.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
single RT9701GB regulator, which has its enable input tied to the A20's
PD2 pin, pulled up to 3v3 via a 10k resistor.
However, the script.bin that shipped with the device listed PH11 and PH3
as Vbus control pins for the two USB ports. Neither of these are
actually connected to anything.
Siarhei Siamashka spotted this problem while reviewing the other
LinkSprite boards. This patch fixes it by only defining a single
regulator, controlled by PD2. Testing shows that the USB ports are now
(correctly) only powered up once the USB PHY driver is loaded.
Reported-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Adam Sampson <ats@offog.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add a separate pinctrl node for the UART3 CTS and RTS pins shared between
the A10s and A13.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
The uart3 pins are shared between the A10s and A13, move the pinctrl node
to the common DTSI to avoid duplication.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
The R8 is very close to the A13, but it still has a few differences,
notably a composite output, which the A13 lacks.
Add a DTSI based on the A13's to hold those differences.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Enable the otg/drc usb controller on the pcDuino1/2 board. Note
that the pcDuino1 FEX file from the vendor contains the following
information in the [usbc0] section:
usb_id_gpio = port:PH04<0><1><default><default>
usb_det_vbus_gpio = port:PH05<0><0><default><default>
usb_drv_vbus_gpio = port:PB09<1><0><default><0>
While the pcDuino2 FEX has:
usb_id_gpio = port:PH04<0><1><default><default>
usb_det_vbus_gpio = port:PH05<0><0><default><default>
usb_drv_vbus_gpio = port:PD02<1><0><default><0>
The ID pin is indeed PH4. The PD2 pin can be used to switch power
on/off for the USB Type A receptacle on pcDuino2, but it has nothing
to do with the MicroUSB OTG receptacle. The VBUS pin of the MicroUSB
receptacle is always connected to 5V according to the schematics
(both pcDuino1 and pcDuino2) and confirmed by doing some tests on
pcDuino2. The PH5 pin is just one of the pins on the J8 expansion
header and has nothing to do with USB OTG. The PB9 pin is pulled
up and connected to the N_VBUSEN pin of AXP209 PMIC, while the
VBUS pin of AXP209 only has a capacitor between it and the
ground (this pin is not used for anything else).
To sum it up. Only the ID pin (PH4) has a real use. And 5V voltage
is always served to the MicroUSB OTG receptacle no matter what is
the state of the PB9/PD2 pins.
This patch has been tested on pcDuino2 to work fine in a host role
with a USB keyboard connected via an OTG cable. It also works fine
in a device role (cdc_ether) with a regular Micro-B cable connected
to a desktop PC.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The LinkSprite pcDuino2 board is almost identical to the older
LinkSprite pcDuino1 board according to the schematic pdf files.
So we just include the existing "sun4i-a10-pcduino.dts" file and
make the necessary adjustments.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The pcDuino1 board does not use any power switches at all for its
two USB host ports and the VBUS pins are always connected to 5V.
The pcDuino2 board uses the RT9701GB power switch for its single
USB host port, but the USB_EN pin (PD2) is pulled up with a 10K
resistor. So that the USB power is still enabled by default,
resulting in the same behaviour as pcDuino1 if nobody touches
the PD2 pin. This minor difference is going to be handled in a
follow-up patch, introducing a separate dts file for pcDuino2.
The primary reason for this fix is that the current dts file
unnecessarily meddles with the PH3 and PH6 pins. But the PH6 pin
is available on the Arduino-compatible expansion header and may
have a better use for other purposes. This patch fixes the
problem and now the PH6 pin can be used with the GPIO sysfs
interface. Tested on a pcDuino2 board with a multimeter:
echo 230 > /sys/class/gpio/export
echo "out" > /sys/class/gpio/gpio230/direction
echo 0 > /sys/class/gpio/gpio230/value
echo 1 > /sys/class/gpio/gpio230/value
USB still works as expected too.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Enable the otg/drc usb controller on the Bananapi.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
sun7i-a20-bananapi.dts doesn't contain regulator nodes for the AXP209 PMU
driver, so add them to allow for voltage-scaling with cpufreq-dt. Also
add board-specific OPP to use slightly higher voltages at lower
frequencies since Kevin Hilman reported that not all BananaPi boards run
stable at the default voltages inherited by sun7i-a20.dtsi.
Signed-off-by: Timo Sigurdsson <public_timo.s@silentcreek.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Replace console with stdout-path so that we don't have to put the
console on the kernel command line.
Remove earlyprintk to allow the kernel to boot on a system even
if DEBUG_LL is configured for another system.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Merge "Broadcom devicetree changes for v4.4" from Florian Fainelli:
This pull requests contains the following Broadcom SoCs Device Tree changes:
- Brian Norris documents the BCM7445 SoCs Power Management controllers and
hardware and updates the reference BCM7445 Device Tree with these nodes
- Florian Fainelli documents the BCM7xxx write-pairing feature in the top-level
BCM7xxx binding document
- Hauke Merthens enables the NAND controller for the Asus RT-AC87U and adds the
GPIO pin controlling the USB power supply on Netgear R6250
- Jon Mason adds support for the NorthStar Plus SoC by providing a top-level
binding document and the minimalist device tree skeleton for these SoCs
- Rafal Milecki adds support for the Netgear R7000 (BCM5301x SoC)
- Ray Jui provides a set of Cygnus DT changes that make the Device Tree clearer
and more correct with respect to how the hardware is designed. He also enables
the NAND controller on the bcm911360_entphn design, enables a bunch of
peripherals on the bcm958305k evaluation board, and adds a skeleton .dtsi file
for the touchscreen extansion board(s)
* tag 'arm-soc/for-4.4/devicetree' of http://github.com/Broadcom/stblinux:
ARM: dts: move aliases back to .dts in Cygnus
ARM: dts: fix Cygnus nand device node
ARM: dts: enable touchscreen support on Cygnus
ARM: dts: Enable NAND support on bcm911360_entphn
ARM: dts: Enable various peripherals on bcm958305k
ARM: dts: Reorder Cygnus peripherals
ARM: dts: Move all Cygnus peripherals into axi bus
ARM: dts: Put Cygnus core components under core bus
ARM: dts: Use label for device nodes in Cygnus dts
ARM: dts: consolidate aliases for Cygnus dt files
ARM: BCM5301X: Netgear R6250 add USB GPIO
Documentation: bindings: brcmstb: Document write-pairing
ARM: dts: brcmstb: add BCM7445 system PM DT nodes
Documentation: dt: brcmstb: add system PM bindings
ARM: BCM5301X: add NAND flash chip description for Asus RT-AC87U
ARM: BCM5301X: Add DT for Netgear R7000
ARM: NSP: add minimal Northstar Plus device tree
dt-bindings: Create Documentation for NSP DT bindings
system-on-module as well as the square baseboard. On top of that
a lot of mmc-related changes to improve speeds on the Cortex-A9
socs and also setting up the supplies for rk3288 mmc-controllers
for the following mmc-tuning support. And of course the dts-part
of the rk3288 power-domains.
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Merge tag 'v4.4-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "Rockchip dts32 changes for 4.4" from Heiko Stuebner:
DTS changes including one new Veyron-board and the Radxa Rock2
system-on-module as well as the square baseboard. On top of that
a lot of mmc-related changes to improve speeds on the Cortex-A9
socs and also setting up the supplies for rk3288 mmc-controllers
for the following mmc-tuning support. And of course the dts-part
of the rk3288 power-domains.
* tag 'v4.4-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add the support power-domain node on RK3288 SoCs
ARM: dts: rockchip: add rk3288-firefly iodomains
ARM: dts: rockchip: fixup firefly mmc supplies
ARM: dts: rockchip: add rk3288-popmetal iodomains
ARM: dts: rockchip: add rk3288-popmetal mmc supplies
ARM: dts: rockchip: add rk3288-popmetal board to dtb list
ARM: dts: rockchip: Add dtb for the Radxa Rock 2 Square board
ARM: dts: rockchip: support highspeed sd-cards on rk3066a boards
ARM: dts: rockchip: support highspeed sd-cards for rk3188-radxarock
ARM: dts: rockchip: Add the hdmi-ddc pinctrl settings for rk3288
ARM: dts: rockchip: Remove specific cts pullup from veyron
ARM: dts: rockchip: pull up cts lines on rk3288
ARM: dts: rockchip: add veyron-jaq board
ARM: dts: rockchip: Add support for SD/MMC on MarsBoard-RK3066
dt-bindings: add power-domain header for RK3288 SoCs
Explicitly use the SoC specific compatible strings in kirkwood.dtsi and
dove.dtsi, so that the crypto devices have access to the TDMA feature
when attached to the new CESA driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The new bindings split the crypto and sram node in two separate devices.
Modify the existing crypto nodes to match the new representation.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Define the crypto SRAM ranges so that the resources referenced by the
sa-sram node can be properly extracted from the DT.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add crypto related nodes in armada-38x.dtsi.
[gregory.clement@free-electrons.com: Fix typo for compatible string
armada38x instead of armada375]
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The SCP firmware on Juno provides access to SoC sensors via the
SCPI. Add the sensor nodes to the device tree to enable this support.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
This patch adds the CPU clocks so that the CPU DVFS can be enabled.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
This patch adds CPU topology on Juno. It will be useful for ther other
IP blocks depending on this topology.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
This patch adds support for the MHU mailbox peripheral used on Juno by
application processors to communicate with remote SCP handling most of
the CPU/system power management. It also adds the SRAM reserving the
shared memory and SCPI message protocol using that shared memory.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Define the Porter board dependent part of the VIN0 device node.
Add the device node for Analog Devices ADV7180 video decoder to I2C2 bus.
Add the necessary subnodes to interconnect VIN0 and ADV7180 devices.
This patch is analogous to the commit 8d62f4f75320 ("ARM: shmobile:
henninger: add VIN0/ADV7180 DT support") as there are no differences
between the boards in this respect.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Porter board dependent part of the I2C2 device node.
This patch is analogous to the commit 29a647c396a0 ("ARM: shmobile:
henninger: add I2C2 DT support") as there are no differences between
the boards in this respect.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device tree binding documentation for the Qualcom Shared Memory
Manager.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <agross@codeaurora.org>
We can add more domains node in the future.
This patch add the needed clocks into power-controller.
As the discuess about all the device clocks being listed in
the power-domains itself.
There are several reasons as follows:
Firstly, the clocks need be turned off to save power when
the system enter the suspend state. So we need to enumerate
the clocks in the dts. In order to power domain can turn on and off.
Secondly, the reset-circuit should reset be synchronous on RK3288,
then sync revoked. So we need to enable clocks of all devices.
In other words, we have to enable the clocks before you operate them
if all the device clocks are included in someone domians.
Thirdly, as the chip designs for PM hardhare. we need turn on the noc
clocks, if we are operating the "pd_vio" domain to enter the idle status.
The device's clock be included in domains that needed turn on if do that.
The clocks in the dts are needed to enable before you want to happy work.
At the moment, This patch is very good work for PM hardware.
Also, we can add these clocks in the future if we have some hidden clocks.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
[add necessary power-domain properties to keep drm subsys working]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the iodomains node and reference the correct regulator for each
domain. This also includes adding the currently unused dvp regulators.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Fix some incorrect references to mmc regulators.
vccio_wl for example is the io-voltage supply not the core supply
of the wifi module itself, which is vbat_wl instead.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the iodomains node and reference the correct regulator for each
domain. This also includes adding the currently unused dvp regulators
and fixing up two regulators to follow the naming in the schematics.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The popmetal board was not included in the list of Rockchip boards,
so was only built when explicitly called with make rk3288-popmetal.dtb
but not in a generic make dtbs, so add the missing entry.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
