mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-15 09:34:17 +00:00
700 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Conor Dooley
|
bc2da26599 |
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
While moving all the reset code in the PolarFire SoC clock driver to the
reset subsystem, I removed an `#if IS_ENABLED(RESET_CONTROLLER)` from
the driver and moved it to the header, however this was not the correct
thing to do. In the driver such a condition over-eagerly provided a
complete implementation for mpfs_reset_{read,write}() when the reset
subsystem was enabled without the PolarFire SoC reset driver, but in the
header it meant that when the subsystem was enabled and the driver was
not, no implementation for mpfs_reset_controller_register() was
provided. Fix the condition so that the stub implementation of
mpfs_reset_controller_register() is used when the reset driver is
disabled.
Fixes: 098c290a490d ("clock, reset: microchip: move all mpfs reset code to the reset subsystem")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202405082259.44DzHvaN-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202405082200.tBrEs5CZ-lkp@intel.com/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240508-unabashed-cheese-8f645b4f69ba@spud
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||
|
Conor Dooley
|
098c290a49 |
clock, reset: microchip: move all mpfs reset code to the reset subsystem
Stephen and Philipp, while reviewing patches, said that all of the aux device creation and the register read/write code could be moved to the reset subsystem, leaving the clock driver with no implementations of reset_* functions at all. Move them. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240424-strangle-sharpener-34755c5e6e3e@spud Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Linus Torvalds
|
bb41fe35dc |
Char/Misc and other driver subsystem updates for 6.9-rc1
Here is the big set of char/misc and a number of other driver subsystem
updates for 6.9-rc1. Included in here are:
- IIO driver updates, loads of new ones and evolution of existing ones
- coresight driver updates
- const cleanups for many driver subsystems
- speakup driver additions
- platform remove callback void cleanups
- mei driver updates
- mhi driver updates
- cdx driver updates for MSI interrupt handling
- nvmem driver updates
- other smaller driver updates and cleanups, full details in the
shortlog
All of these have been in linux-next for a long time with no reported
issue, other than a build warning with some older versions of gcc for a
speakup driver, fix for that will come in a few days when I catch up
with my pending patch queues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCZfwuLg8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+ynKVACgjvR1cD8NYk9PcGWc9ZaXAZ6zSnwAn260kMoe
lLFtwszo7m0N6ZULBWBd
=y3yz
-----END PGP SIGNATURE-----
Merge tag 'char-misc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc and other driver subsystem updates from Greg KH:
"Here is the big set of char/misc and a number of other driver
subsystem updates for 6.9-rc1. Included in here are:
- IIO driver updates, loads of new ones and evolution of existing ones
- coresight driver updates
- const cleanups for many driver subsystems
- speakup driver additions
- platform remove callback void cleanups
- mei driver updates
- mhi driver updates
- cdx driver updates for MSI interrupt handling
- nvmem driver updates
- other smaller driver updates and cleanups, full details in the
shortlog
All of these have been in linux-next for a long time with no reported
issue, other than a build warning for the speakup driver"
The build warning hits clang and is a gcc (and C23) extension, and is
fixed up in the merge.
Link: https://lore.kernel.org/all/20240321134831.GA2762840@dev-arch.thelio-3990X/
* tag 'char-misc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (279 commits)
binder: remove redundant variable page_addr
uio_dmem_genirq: UIO_MEM_DMA_COHERENT conversion
uio_pruss: UIO_MEM_DMA_COHERENT conversion
cnic,bnx2,bnx2x: use UIO_MEM_DMA_COHERENT
uio: introduce UIO_MEM_DMA_COHERENT type
cdx: add MSI support for CDX bus
pps: use cflags-y instead of EXTRA_CFLAGS
speakup: Add /dev/synthu device
speakup: Fix 8bit characters from direct synth
parport: sunbpp: Convert to platform remove callback returning void
parport: amiga: Convert to platform remove callback returning void
char: xillybus: Convert to platform remove callback returning void
vmw_balloon: change maintainership
MAINTAINERS: change the maintainer for hpilo driver
char: xilinx_hwicap: Fix NULL vs IS_ERR() bug
hpet: remove hpets::hp_clocksource
platform: goldfish: move the separate 'default' propery for CONFIG_GOLDFISH
char: xilinx_hwicap: drop casting to void in dev_set_drvdata
greybus: move is_gb_* functions out of greybus.h
greybus: Remove usage of the deprecated ida_simple_xx() API
...
|
||
|
Arnd Bergmann
|
daa0987e1f |
Qualcomm driver updates for v6.9
This introduces the Qualcomm Programmable Boot Sequencer (PBS) driver. The Qualcomm SMEM no longer acquires the hwspinlock during the "get" operation, to improve the system behavior during the recovery of a remoteproc that crashed with the hwspinlock held. The Qualcomm Always On Subsystem (AOSS) message protocol driver gains tracepoints, printf annotation, and a debugfs interface is introduced for tweaking system properties during development and debugging. The Qualcomm socinfo driver gains data for SM8475, QCM8550 and QCS8550 platforms, and the PM2250 is renamed to PM4125. Support for controlling the voltage regulator in SPM/SAW2 is introduced. The gfx.lvl power-domain is dropped for SA8540P, as this resource was incorrectly inherited from SC8280XP. Additionally some code cleanup improvements is introduced across APR, LLCC, SMP2P and SPM. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmXarn0VHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FzZoP/2hYUMS+sR2kD7gZDGi8oV71C+dQ Vmo1MQIhGjYEb6HSHdrxp/11GPlLVU45xuk9/FFVqAPrxNQm2y9NC60Ye1TQNWZR XS+w5+YkIFdfZIbZ8GGmlPspeXDSnq2DGWQjht+cBNyASzhjO5ICP79WQ0jfHgjH l5pNw3YMamc7pwdX2oslxXV8HzDr4JxzpveV0+QbsVDU4J04mrxoBRmv2cdqv2Eb 5jNR4HjmCQkdI/bp/2frCmWmGP9bqP24C6XWCe4lXuCAsmNKAeEeuyABnsPNRYrO 5ELd2sPpXBLBUhR9w/0rY9ouIsJ500BD7U1yLrHocwGICL1Ro7dGjnyp6j/7Tm9X 1nx2mHK7ywH7E6BxVTcmDS3CtymcMknpUfUjANJ/yQrAmcqvKRA3F0ELiXywrndQ 0R97qjc9ixVaM5LU4kMgQG50NZCmsNPJ7a3smOihpmfJK+6Mmkc5XxFRYuJgL9Ag b1PwnVgzeBPQAs+Tx7i5bBfFOa49zVxHYIFfu+XY50DL80viiKCRAeXQNyWmJ0qM 3tKgMeIY2nXZJ0DvySFfro51AnZcXEMa3Bc5qNZlM4jaqXGPkDocAV9CYKntlXFU POnOnGo4liZalWqel3tTuDoBu3nVAq0q4+ooWl755TRGBtIvW1tWAOgldjg6v3Ef 6BgAWh8GrEHM0etB =T09a -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXl7kUACgkQYKtH/8kJ UidEfQ//eugpCwNrv6q1TdlSBJkwlVV/3VJLewh4SCdpckQNJ9ysxDt0hnbTVVz8 ykR0ilYLrpuinbWSaBIZp4oxypIHOEhXzQf1diyrAjM9T5mVnv+Ytdy3qDrQ1SOM yg8n64aaBCrJiCJk3vHitS2DxStbmikX8i0dzQNeG7YskplrkbKXqtXjQ8zmanAc 2Y4Ot1DMoTKjp4t6mC7yF5YXTEfCkg0eHaIdzMREarWRUU+g0qqR43T416AhayM5 4mNH42/0rxJtvN3+EeQkVBXMWu2hmHt9esdR216GZ22fS+J9HAVOGPM+oga1Td7c 947T2BB55AalfjiNxWbfabxNmHyEuVyYWaDAJO/qU0ZIE+539QAVaW9xrTxYeOFp PbctLehm3DUPmR453R4oUTGC6UD+OnZOj+ppy/vB08UbdF5bV0KRT/hviOR+bb6U VCYRbDIsfzY1fFFLJShZONogZADtciDjel7WATwhttw503NLH5DaebD+OjPbHVgq U4y7maUGPkbAPJT4YbYOcetqVOnYiFp8OG3J/JDTOr3+3RNtInPYao5TSb1QNjGh A7+4jKf0X8err26xpmGXfa2nG8hUNOPn/PYVNwxgWmq0P74KR2GwenB4ze+SME2J sc6ZQy4LAnU8KSAZpLVPrv78R9cbyCvCtWbQpKzY8l8PfzhaK24= =bPSM -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.9 This introduces the Qualcomm Programmable Boot Sequencer (PBS) driver. The Qualcomm SMEM no longer acquires the hwspinlock during the "get" operation, to improve the system behavior during the recovery of a remoteproc that crashed with the hwspinlock held. The Qualcomm Always On Subsystem (AOSS) message protocol driver gains tracepoints, printf annotation, and a debugfs interface is introduced for tweaking system properties during development and debugging. The Qualcomm socinfo driver gains data for SM8475, QCM8550 and QCS8550 platforms, and the PM2250 is renamed to PM4125. Support for controlling the voltage regulator in SPM/SAW2 is introduced. The gfx.lvl power-domain is dropped for SA8540P, as this resource was incorrectly inherited from SC8280XP. Additionally some code cleanup improvements is introduced across APR, LLCC, SMP2P and SPM. * tag 'qcom-drivers-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits) dt-bindings: soc: qcom: qcom,saw2: add msm8226 l2 compatible soc: qcom: spm: add support for voltage regulator soc: qcom: spm: remove driver-internal structures from the driver API dt-bindings: soc: qcom: qcom,saw2: define optional regulator node dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml soc: qcom: llcc: Check return value on Broadcast_OR reg read soc: qcom: socinfo: Add Soc IDs for SM8475 family dt-bindings: arm: qcom,ids: Add IDs for SM8475 family soc: qcom: apr: make aprbus const dt-bindings: soc: qcom: qcom,pmic-glink: document X1E80100 compatible soc: qcom: add QCOM PBS driver dt-bindings: soc: qcom: Add qcom,pbs bindings pmdomain: qcom: rpmhpd: Drop SA8540P gfx.lvl soc: qcom: socinfo: rename PM2250 to PM4125 soc: qcom: aoss: Add tracepoints in qmp_send() soc: qcom: socinfo: add SoC Info support for QCM8550 and QCS8550 platform dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550 soc: qcom: aoss: Add debugfs interface for sending messages soc: qcom: smem: remove hwspinlock from item get routine ... Link: https://lore.kernel.org/r/20240225030612.480241-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Krzysztof Kozlowski
|
0dc5b8abfa |
interconnect: constify of_phandle_args in xlate
The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> # Tegra Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> # Samsung Link: https://lore.kernel.org/r/20240220072213.35779-1-krzysztof.kozlowski@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org> |
||
|
Dmitry Baryshkov
|
57e2b067f1 |
soc: qcom: spm: remove driver-internal structures from the driver API
Move internal SPM driver structures to the driver itself, removing them from the public API. The CPUidle driver doesn't use them at all. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-saw2-spm-regulator-v7-4-0472ec237f49@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Kartik
|
8402074f30 |
soc/tegra: fuse: Add support for Tegra241
Add support for Tegra241 which use ACPI boot. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Christophe JAILLET
|
9863084dd9 |
soc/tegra: pmc: Remove some old and deprecated functions and constants
These TEGRA_IO_RAIL_... functions and constants have been deprecated in
commit 21b499105178 ("soc/tegra: pmc: Add I/O pad voltage support") in
2016-11.
There seems to be no users since kernel 4.16.
Remove them now.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
||
|
Dmitry Baryshkov
|
5155e48128 |
soc: qcom: socinfo: rename PM2250 to PM4125
It seems, the only actual mentions of PM2250 can be found are related to
the Qualcomm RB1 platform. However even RB1 schematics use PM4125 as a
PMIC name. Rename PM2250 to PM4125 to follow the documentation.
Fixes: 082f9bc60f33 ("soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs")
Fixes: 112d96fd2927 ("soc: qcom: socinfo: Add some PMICs")
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240128-pm2250-pm4125-rename-v2-1-d51987e9f83a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||
|
Linus Torvalds
|
2385018a4e |
- New Device Support
- Add support for Qualcomm PM8937 PMIC to QCOM SPMI PMIC
- Fix-ups
- Use/convert to new/better APIs/helpers/MACROs instead of hand-rolling implementations
- Device Tree binding adaptions/conversions/creation
- Improve error handling; return proper error values, simplify, avoid duplicates, etc
- Continue work to remove superfluous platform .remove() call-backs
- Move some exported symbols into private namespaces
- Clean-up and staticify PM related operations
- Trivial; spelling, whitespace, clean-ups, etc
- Fix include lists; alphabetise, remove unused, explicitly add used
- Bug Fixes
- Use PLATFORM_DEVID_AUTO to ensure multiple duplicate devices can co-exist
- Ensure debugfs register view is correctly presented
- Fix ordering and value issues in current use of clk_register_fractional_divider()
- Repair Kconfig based dependency lists
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAmWmsH0ACgkQUa+KL4f8
d2HIpQ//TWvqbUtHFxK89b/g4soIo2LS8Odz6CnbMlAwlNnhjgrqqFXnPxifN+TP
L6aZX9buij7kH6iPfIi/hFDKVMwxgLUax0rTHNIvzOgg++jw3UoR/x4CvLITJ8Yb
FUVMGLF1lPbXrURS7G23LnZpM0WTWEgJvb+zOLVsL3J6HihGi9JO2EoNHwM/GwSl
eTtZydwdRo0u7m+z+EjaZnoSamBF+5i8ZJUAg8eF9LZtCB0AXe/zMWjgtZNz1Pqn
dAd7CbOdJQjaxYtBlRRpgdIuI6d29yotY91pGu5OEhmXPMZuZRUjtz0HnNDNcPvU
+Mnz3L8tcci8ZUmQ0Zr8OBrYtw623074+h/TSeUj88Ce4LAzYkvIfprw21qxl9Wx
h1VxHf0GsJRswi6lgOA4JItZEARhU37ePMPZ2zyT7e8IWh35KGbdYubUstLFittP
zzwiPO0haGeprvSgX+pn2rxJofaFtSIpqiMB7LtSKqmiEl1DgdC06+wikLe8l9+y
LnvyzQOECh1ANMHdvoQO2mqa97WxlzTBe9zg5mQQrOnyUJgYb0D5dDA8l/xvobUz
XlMIsJ8ZCulwVkQWdXIHZFtfaoKs3jM4G3vJIy+vkQSf+U3y4pGhNhMJ67Cz33Ge
W2riI+Vq/mmLMUDayCZENxTJ3WNUO6rqymvbtCPEuiHRSFnjBYU=
=R7SR
-----END PGP SIGNATURE-----
Merge tag 'mfd-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull mfd updates from Lee Jones:
"New Device Support:
- Add support for Qualcomm PM8937 PMIC to QCOM SPMI PMIC
Fix-ups:
- Use/convert to new/better APIs/helpers/MACROs instead of
hand-rolling implementations
- Device Tree binding adaptions/conversions/creation
- Improve error handling; return proper error values, simplify,
avoid duplicates, etc
- Continue work to remove superfluous platform .remove() call-backs
- Move some exported symbols into private namespaces
- Clean-up and staticify PM related operations
- Trivial; spelling, whitespace, clean-ups, etc
- Fix include lists; alphabetise, remove unused, explicitly add used
Bug Fixes:
- Use PLATFORM_DEVID_AUTO to ensure multiple duplicate devices can
co-exist
- Ensure debugfs register view is correctly presented
- Fix ordering and value issues in current use of
clk_register_fractional_divider()
- Repair Kconfig based dependency lists"
* tag 'mfd-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (50 commits)
mfd: ti_am335x_tscadc: Fix TI SoC dependencies
dt-bindings: mfd: sprd: Add support for UMS9620
mfd: ab8500-sysctrl: Drop ancient charger
mfd: intel-lpss: Fix the fractional clock divider flags
mfd: tps6594: Add null pointer check to tps6594_device_init()
dt-bindings: mfd: pm8008: Clean up example node names
dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Clean up example
dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Fix regulator binding
dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Fix up binding reference
mfd: da9062: Simplify obtaining I2C match data
mfd: syscon: Fix null pointer dereference in of_syscon_register()
mfd: intel-lpss: Don't fail probe on success of pci_alloc_irq_vectors()
mfd: twl6030-irq: Revert to use of_match_device()
mfd: cs42l43: Correct order of include files to be alphabetical
mfd: cs42l43: Correct SoundWire port list
mfd: Fix a few spelling mistakes in PMIC header file comments
mfd: intel-lpss: Provide Intel LPSS PM ops structure
mfd: intel-lpss: Move exported symbols to INTEL_LPSS namespace
mfd: intel-lpss: Adjust header inclusions
mfd: intel-lpss: Use device_get_match_data()
...
|
||
|
Arnd Bergmann
|
8d446ff13a |
Memory controller drivers for v6.8
Few improvements for Tegra Memory Controller: Override the SID programming in the device, if firmware or bootloader left it in bypass mode, e.g. after resuming from suspend. Skip prorgamming the SID, if given Memory Controller client does not support it. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmV5S74QHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD12mVD/4tj4NUiVuytvYTI5J9+z+u+69/Nbkr9xz8 C6APNPovUHFJTvy76J1sRzzJNL/MFSLMC271hcSEvpfQAkBNvdW4drq8seDsRJcx 5CbJPX0U+fxgSTubOJq1Q/vDe+29v6xhpt/LEauB3KvxJl3uJdVkPFnURzREvFHL +eEdQSq60td6I65me///D5QNBYr03Qjyfag7GTf05fbnfcc9zkXVV1rIEl/KlBpy 1cw5/8mxvRS0JUKLJxQ/2VHJDkadcGiFbS1DwtSY5ouXqiWDgNaXk7pvMKU8UBAQ 6kgKjNfnr+BkI1nbqGlB0bHIgoSeEGDeYMXsgETsliuOUKw8Hg5bFhy137e0gLOg A0/o3fDQUbsYAjp3NuN1habt5IqIdvm2a66gAOnYxgZHRuy4HZeUrxjPqFU70TRA uPTjms3SUmzb7IfV1i5nA9FFxH3vRk+NmjxCP9bDmsAMvSRZADORDKWFnWhWP4h3 +UB2pFAZVcM2x2qBPZUP5zB8BVhyRc4qMDT/Lnj+1/zBTdDEIkxXhLAqADU9EkZB 59JSp6n967MpWhYNUmjTYdnQ9ZLVEWjA/ZHJMgEfFtU0ackRct4sySiR7+oOyiJS bgynakMgK894k2TSAKWCStXwi8lfeKkgPb3oNqmE4WE8SgNGjIoCean8fNLOCc1f 28xZ1BHCKQ== =rulX -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWFcoYACgkQYKtH/8kJ Uiff9hAAgPBABQIC9MfH3+H8dsyZ2Z+ylHmkWlkyjyFQYZz6RbNgwD4p1jCxXVJY EX3yT2KAJGaa0tHy2zo3vsFrD/jFlHYuqwJE9TTHvyl+bjJhi9iZWhIe+AmN+dk4 CFIK8CPzgKS/Dd2/4NpwE09RZz5qw2W+SppcdV6kgte7kmCcc4Cj9GWLZMAq5Me5 iIdwTIzUaWcmKP153p17/X3UKR8RcTIvKl8Ebf4NoD05wI7f7z60PNDjfiALSV5j yRwKKsgBTowmOrBb5G5LKT4qDynkRpPJAN+P8kmRXjnZFRrnT7eUfjm6zYKBsClb XpR3X6sId+OH7iXpww7IX/r1Htgksfa/Tsyoh5L0d8RiSSEC0E+ZoZfdn8c+TjPR ZxgfrdmOE1Qs6TufIb8FXzrJ22RAY8/2HfmI0aFeMX5HDWjSd8EmuFfINqADLTm8 v3wGZYUPH3PMcLvcPMtjBk2pQhWIGePY6bMH8oi9625fZxa4vmILxCF5VzIt0Xol wkqXQizhCSIIU90MzSilq0TIjK81pE1Lbq97KRqpAWl/+lAITNI2jEF70yjPxcn9 TPsJNMmbORli9lc2/Tmp43NJcMyor5ss63Yu+hJaz87I/Jx/mC4zR024sW2a/5+e Mi+k0ny5MpZRUCscr4NskzSKMAL4Z4uUoBbFqoEwhA7pIKo3VTE= =QWhm -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers Memory controller drivers for v6.8 Few improvements for Tegra Memory Controller: Override the SID programming in the device, if firmware or bootloader left it in bypass mode, e.g. after resuming from suspend. Skip prorgamming the SID, if given Memory Controller client does not support it. * tag 'memory-controller-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: tegra: Protect SID override call under CONFIG_IOMMU_API memory: tegra: Skip SID programming if SID registers aren't set memory: tegra: Add SID override programming for MC clients Link: https://lore.kernel.org/r/20231213061523.4803-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
cd845dfd46 |
RISC-V SoC drivers for v6.8
There's only one set of changes here, the addition of "Auto Update" support for PolarFire SoC. Auto Update is one of the ways that the FPGA bitstream can be updated, and the only one suitable for use from Linux as it does not immediately initiate a reboot when started. The driver was not accepted in the FPGA manager subsystem as the update only occurs after a reboot and makes no use of the FPGA manager framework. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZYQwXQAKCRB4tDGHoIJi 0lieAQC6en0Y0TRDRF18NX0SqnmrxMaiwJxV0tGp+WGgykpmEwEA9vZliqRRG+zJ ZTMkk+zHVTtYgIXt2WFelDLKj5abHAE= =4VMq -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWFcWgACgkQYKtH/8kJ UifdChAAjnUWNXC7jCfVqj5ALE/dGz8vPpXnY8FpNr90hZpbgAldMOvIkIGD1MlC eAglMXDDYnvuM5WUa6Pui/EHSSTbG4J8R6w36EUmG9mjzyCSsZ8fx4/hss6UI/hB pAHhpR3Er9v8eIg2Td0LE/hN+vVwJJiOgGkQgEYcr9ipmGDv+tXjUqDbtA7z933S lQO2zYZKcDA+WqfUnCKmN79MsZ/qo5Ve+VrJNyBhhQD1whRG/G0cFHvzA4oa2n5q UJ6KAAjLDDdG0zWd/Ig+KIXusDHHFyv65jaPMb0e9VLcMHhBl4uPZigVC64Q/SUA jrRT82PN2QA4hcDFwTmQ1xVzjXfsRfTCUvCVleYm/nU5tE7HAkIfwTDVTn3i7usd enoQmk08EDI6sM8fqq+vm0JuX8Lu/XzInQtegZswi4S8qR3dwwAxIVwabHc7CVse S2YIW+tWGaID2G1bFhHs5LnhqvlPsQD64o5Dft2orLkPGx0Rp7e2hfiBB3ghuloM Kk9lxtUa+Hw/gpQMuuk/X3jaBFQXEBa62P2vqqUicUH/Hj5y80MHbxtH/uQKrSVY FxnJY+D0PZ2ggnDXAkDv6+GGIO9WXVQ+KTGKoQHYJ6tCLUWN+1JiK61WyQ9ewdC1 jE2Tig88hGRdEmTCAKZjUmLVuoNqnU7knKHaslg7+2lSAj1jpCE= =yAyj -----END PGP SIGNATURE----- Merge tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.8 There's only one set of changes here, the addition of "Auto Update" support for PolarFire SoC. Auto Update is one of the ways that the FPGA bitstream can be updated, and the only one suitable for use from Linux as it does not immediately initiate a reboot when started. The driver was not accepted in the FPGA manager subsystem as the update only occurs after a reboot and makes no use of the FPGA manager framework. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: add auto-update driver to mpfs entry firmware: microchip: Replace of_device.h with explicit include firmware: microchip: add PolarFire SoC Auto Update support soc: microchip: mpfs: add auto-update subdev to system controller soc: microchip: mpfs: print service status in warning message soc: microchip: mpfs: enable access to the system controller's flash dt-bindings: soc: microchip: add a property for system controller flash firmware_loader: Expand Firmware upload error codes with firmware invalid error Link: https://lore.kernel.org/r/20231221-droop-unblock-81e4fe14acee@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Herve Codina
|
7a2ee1576d |
soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime
Introduce qmc_chan_{get,set}_ts_info() function to allow timeslots
modification at runtime.
The modification is provided using qmc_chan_set_ts_info() and will be
applied on next qmc_chan_start().
qmc_chan_set_ts_info() must be called with the channel rx and/or tx
stopped.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20231205152116.122512-18-herve.codina@bootlin.com
|
||
|
Herve Codina
|
ba3b7e4753 |
soc: fsl: cpm1: qmc: Add support for child devices
QMC child devices support is needed to avoid orphan DT nodes that use a simple DT phandle to reference a QMC channel. Allow to instantiate child devices and also extend the API to get the qmc_chan using a child device. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20231205152116.122512-7-herve.codina@bootlin.com |
||
|
Herve Codina
|
0e034aec5b |
soc: fsl: cpm1: qmc: Extend the API to provide Rx status
In HDLC mode, some status flags related to the data read transfer can be set by the hardware and need to be known by a QMC consumer for further analysis. Extend the API in order to provide these transfer status flags at the read complete() call. In TRANSPARENT mode, these flags have no meaning. Keep only one read complete() API and update the consumers working in transparent mode. In this case, the newly introduced flags parameter is simply unused. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20231205152116.122512-5-herve.codina@bootlin.com |
||
|
Dang Huynh
|
4773d2f1a5 |
mfd: qcom-spmi-pmic: Add support for PM8937
Add the subtype and compatible strings for PM8937. The PM8937 is found in various SoCs, including MSM8917, MSM8937, MSM8940 and APQ variants. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Dang Huynh <danct12@riseup.net> Link: https://lore.kernel.org/r/20231121-pm8937-v2-1-b0171ab62075@riseup.net Signed-off-by: Lee Jones <lee@kernel.org> |
||
|
Conor Dooley
|
742aa6c563 |
soc: microchip: mpfs: enable access to the system controller's flash
The system controller has a flash that contains images used to reprogram the FPGA using IAP (In-Application Programming). Introduce a function that allows a driver with a reference to the system controller to get one to a flash device attached to it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Ashish Mhetre
|
fe3b082a6e |
memory: tegra: Add SID override programming for MC clients
For some devices the bootloader/firmware may set up the device in
bypass. Memory clients like display needs kernel to program SID after
resume because bootloader/firmware programs the SID of display device to
bypass. In order to make sure that kernel IOMMU mappings for these
devices work after resume, add SID override programming support for all
memory clients on memory controller resume.
This partially reverts 'commit ef86b2c2807f ("memory: tegra: Remove
clients SID override programming")'
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Link: https://lore.kernel.org/r/20231107112713.21399-1-amhetre@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||
|
Linus Torvalds
|
4bbdb725a3 |
IOMMU Updates for Linux v6.7
Including:
- Core changes:
- Make default-domains mandatory for all IOMMU drivers
- Remove group refcounting
- Add generic_single_device_group() helper and consolidate
drivers
- Cleanup map/unmap ops
- Scaling improvements for the IOVA rcache depot
- Convert dart & iommufd to the new domain_alloc_paging()
- ARM-SMMU:
- Device-tree binding update:
- Add qcom,sm7150-smmu-v2 for Adreno on SM7150 SoC
- SMMUv2:
- Support for Qualcomm SDM670 (MDSS) and SM7150 SoCs
- SMMUv3:
- Large refactoring of the context descriptor code to
move the CD table into the master, paving the way
for '->set_dev_pasid()' support on non-SVA domains
- Minor cleanups to the SVA code
- Intel VT-d:
- Enable debugfs to dump domain attached to a pasid
- Remove an unnecessary inline function.
- AMD IOMMU:
- Initial patches for SVA support (not complete yet)
- S390 IOMMU:
- DMA-API conversion and optimized IOTLB flushing
- Some smaller fixes and improvements
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmVJFcEACgkQK/BELZcB
GuMgDxAAsnYVQjQ7wRkwR0rHARuEaJ+Lz2vkLNH+uYXjBzhFe2bT+ykMcZysAkdK
A5PMLOFT5Etf+PAqOM0CoIGQFOefAId6uGl7S61Fp9ZWDKhMrOBFWhxGOaufA1Du
tNvt3i66hwPSDZa82kY3wRCluYtj0aBBzmM6ZTwBwFZdQ7LABMtE8OxisqncVvq0
H6vhV213fqvhCFSQJ6PnTAEiv70WvWBWygA+Z/gwYf9hypZQae91PNXdK9313a9z
OvCzGBkL/R5/3KkJd88UhFwyYzyNGxq/DmH1etawYR5gYZ8UT/Z/sYpcx9hlO7qr
eENPqeQc+YHZXpKqkaq66HBA1FSnXUqRZLl4cVaZahRRMe/yArsBM6R0W1AfkMAR
rZxwHKoHUWeuHQLMVvmSDNL57h/GJJpTXjRc8HMxLZkVp+ScvnT5XCYHWWzRdCdx
TcC/pJ1tet0FQ8rw09ovlwpGVA6eojWvcpVbLVLfGN8ZWViSVfvNFoPNb7HsGK6M
iRi+L41Y7s63cyogC/Gsae2RAvYv29ZpvE91lmon2u+VBlTpMdOFX9EhWS6RqOBF
cV30bhsw0dyCB7v5jDPtABYEOaR6l1mPLhn1gX3u0Ue/tmPhLX69k4bVWBY6wP3p
gmmJD9ub8FuPQtFCGPE7/8ZINjGGrfiKO24DNI2Ty3XEeq21hU4=
=UyWC
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
"Core changes:
- Make default-domains mandatory for all IOMMU drivers
- Remove group refcounting
- Add generic_single_device_group() helper and consolidate drivers
- Cleanup map/unmap ops
- Scaling improvements for the IOVA rcache depot
- Convert dart & iommufd to the new domain_alloc_paging()
ARM-SMMU:
- Device-tree binding update:
- Add qcom,sm7150-smmu-v2 for Adreno on SM7150 SoC
- SMMUv2:
- Support for Qualcomm SDM670 (MDSS) and SM7150 SoCs
- SMMUv3:
- Large refactoring of the context descriptor code to move the CD
table into the master, paving the way for '->set_dev_pasid()'
support on non-SVA domains
- Minor cleanups to the SVA code
Intel VT-d:
- Enable debugfs to dump domain attached to a pasid
- Remove an unnecessary inline function
AMD IOMMU:
- Initial patches for SVA support (not complete yet)
S390 IOMMU:
- DMA-API conversion and optimized IOTLB flushing
And some smaller fixes and improvements"
* tag 'iommu-updates-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (102 commits)
iommu/dart: Remove the force_bypass variable
iommu/dart: Call apple_dart_finalize_domain() as part of alloc_paging()
iommu/dart: Convert to domain_alloc_paging()
iommu/dart: Move the blocked domain support to a global static
iommu/dart: Use static global identity domains
iommufd: Convert to alloc_domain_paging()
iommu/vt-d: Use ops->blocked_domain
iommu/vt-d: Update the definition of the blocking domain
iommu: Move IOMMU_DOMAIN_BLOCKED global statics to ops->blocked_domain
Revert "iommu/vt-d: Remove unused function"
iommu/amd: Remove DMA_FQ type from domain allocation path
iommu: change iommu_map_sgtable to return signed values
iommu/virtio: Add __counted_by for struct viommu_request and use struct_size()
iommu/vt-d: debugfs: Support dumping a specified page table
iommu/vt-d: debugfs: Create/remove debugfs file per {device, pasid}
iommu/vt-d: debugfs: Dump entry pointing to huge page
iommu/vt-d: Remove unused function
iommu/arm-smmu-v3-sva: Remove bond refcount
iommu/arm-smmu-v3-sva: Remove unused iommu_sva handle
iommu/arm-smmu-v3: Rename cdcfg to cd_table
...
|
||
|
Linus Torvalds
|
babe393974 |
The number of commits for documentation is not huge this time around, but
there are some significant changes nonetheless:
- Some more Spanish-language and Chinese translations.
- The much-discussed documentation of the confidential-computing threat
model.
- Powerpc and RISCV documentation move under Documentation/arch - these
complete this particular bit of documentation churn.
- A large traditional-Chinese documentation update.
- A new document on backporting and conflict resolution.
- Some kernel-doc and Sphinx fixes.
Plus the usual smattering of smaller updates and typo fixes.
-----BEGIN PGP SIGNATURE-----
iQFDBAABCAAtFiEEIw+MvkEiF49krdp9F0NaE2wMflgFAmVBNv8PHGNvcmJldEBs
d24ubmV0AAoJEBdDWhNsDH5Y0JkH/36MOpkaDnsY69/dMRKSuD4mAAP2H6LS8V63
SsMgH5VCj8lcy/Tz1+J89t14pbcX8l0viKxSo4UxvzoJ5snrz8A8gZ9oqY7NCcNs
nMtolnN5IwdbgGnEGqASSLsl07lnabhRK0VYv9ZO7lHjYQp97VsJ/qrjJn385HFE
vYW8iRcxcKdwtuuwOtbPcdAMjP54saJdNC5wMLsfMR0csKcGbzaSNpqpiGovzT7l
phG2DSxrJH0gUZyeGPryroNppaf+mVKSDSiwRdI8mzm0J67p6dZYYwBS1Iw6Awbf
8iYoj6W63/FVQbXffPx5d6ffOSQh4JkAskxgBUOzluSGusSDc+4=
=9HU5
-----END PGP SIGNATURE-----
Merge tag 'docs-6.7' of git://git.lwn.net/linux
Pull documentation updates from Jonathan Corbet:
"The number of commits for documentation is not huge this time around,
but there are some significant changes nonetheless:
- Some more Spanish-language and Chinese translations
- The much-discussed documentation of the confidential-computing
threat model
- Powerpc and RISCV documentation move under Documentation/arch -
these complete this particular bit of documentation churn
- A large traditional-Chinese documentation update
- A new document on backporting and conflict resolution
- Some kernel-doc and Sphinx fixes
Plus the usual smattering of smaller updates and typo fixes"
* tag 'docs-6.7' of git://git.lwn.net/linux: (40 commits)
scripts/kernel-doc: Fix the regex for matching -Werror flag
docs: backporting: address feedback
Documentation: driver-api: pps: Update PPS generator documentation
speakup: Document USB support
doc: blk-ioprio: Bring the doc in line with the implementation
docs: usb: fix reference to nonexistent file in UVC Gadget
docs: doc-guide: mention 'make refcheckdocs'
Documentation: fix typo in dynamic-debug howto
scripts/kernel-doc: match -Werror flag strictly
Documentation/sphinx: Remove the repeated word "the" in comments.
docs: sparse: add SPDX-License-Identifier
docs/zh_CN: Add subsystem-apis Chinese translation
docs/zh_TW: update contents for zh_TW
docs: submitting-patches: encourage direct notifications to commenters
docs: add backporting and conflict resolution document
docs: move riscv under arch
docs: update link to powerpc/vmemmap_dedup.rst
mm/memory-hotplug: fix typo in documentation
docs: move powerpc under arch
PCI: Update the devres documentation regarding to pcim_*()
...
|
||
|
Linus Torvalds
|
385903a7ec |
SoC driver updates for 6.7
The highlights for the driver support this time are
- Qualcomm platforms gain support for the Qualcomm Secure Execution
Environment firmware interface to access EFI variables on certain
devices, and new features for multiple platform and firmware drivers.
- Arm FF-A firmware support gains support for v1.1 specification features,
in particular notification and memory transaction descriptor changes.
- SCMI firmware support now support v3.2 features for clock and DVFS
configuration and a new transport for Qualcomm platforms.
- Minor cleanups and bugfixes are added to pretty much all the active
platforms: qualcomm, broadcom, dove, ti-k3, rockchip, sifive, amlogic,
atmel, tegra, aspeed, vexpress, mediatek, samsung and more.
In particular, this contains portions of the treewide conversion to
use __counted_by annotations and the device_get_match_data helper.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmVC10IACgkQYKtH/8kJ
UifFoQ//Tw7aux88EA2UkyL2Wulv80NwRQn3tQlxI/6ltjBX64yeQ6Y8OzmYdSYK
20NEpbU7VWOFftN+D6Jp1HLrvfi0OV9uJn3WiTX3ChgDXixpOXo4TYgNNTlb9uZ4
MrSTG3NkS27m/oTaCmYprOObgSNLq1FRCGIP7w4U9gyMk9N9FSKMpSJjlH06qPz6
WBLTaIwPgBsyrLfCdxfA1y7AFCAHVxQJO4bp0VWSIalTrneGTeQrd2FgYMUesQ2e
fIUNCaU4mpmj8XnQ/W19Wsek8FRB+fOh0hn/Gl+iHYibpxusIsn7bkdZ5BOJn2J0
OY3C1biopaaxXcZ+wmnX9X0ieZ3TDsHzYOEf0zmNGzMZaZkV8kQt4/Ykv77xz6Gc
4Bl6JI5QZ4rTZvlHYGMYxhy3hKuB31mO2rHbei7eR7J7UmjzWcl5P6HYfCgj7wzH
crIWj1IR1Nx6Dt/wXf3HlRcEiAEJ2D0M3KIFjAVT239TsxacBfDrRk+YedF2bKbn
WMYfVM6jJnPOykGg/gMRlttS/o/7TqHBl3y/900Idiijcm3cRPbQ+uKfkpHXftN/
2vOtsw7pzEg7QQI9GVrb4drTrLvYJ7GQOi4o0twXTCshlXUk2V684jvHt0emFkdX
ew9Zft4YLAYSmuJ3XqGhhMP63FsHKMlB1aSTKKPeswdIJmrdO80=
=QIut
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The highlights for the driver support this time are
- Qualcomm platforms gain support for the Qualcomm Secure Execution
Environment firmware interface to access EFI variables on certain
devices, and new features for multiple platform and firmware
drivers.
- Arm FF-A firmware support gains support for v1.1 specification
features, in particular notification and memory transaction
descriptor changes.
- SCMI firmware support now support v3.2 features for clock and DVFS
configuration and a new transport for Qualcomm platforms.
- Minor cleanups and bugfixes are added to pretty much all the active
platforms: qualcomm, broadcom, dove, ti-k3, rockchip, sifive,
amlogic, atmel, tegra, aspeed, vexpress, mediatek, samsung and
more.
In particular, this contains portions of the treewide conversion to
use __counted_by annotations and the device_get_match_data helper"
* tag 'soc-drivers-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (156 commits)
soc: qcom: pmic_glink_altmode: Print return value on error
firmware: qcom: scm: remove unneeded 'extern' specifiers
firmware: qcom: scm: add a missing forward declaration for struct device
firmware: qcom: move Qualcomm code into its own directory
soc: samsung: exynos-chipid: Convert to platform remove callback returning void
soc: qcom: apr: Add __counted_by for struct apr_rx_buf and use struct_size()
soc: qcom: pmic_glink: fix connector type to be DisplayPort
soc: ti: k3-socinfo: Avoid overriding return value
soc: ti: k3-socinfo: Fix typo in bitfield documentation
soc: ti: knav_qmss_queue: Use device_get_match_data()
firmware: ti_sci: Use device_get_match_data()
firmware: qcom: qseecom: add missing include guards
soc/pxa: ssp: Convert to platform remove callback returning void
soc/mediatek: mtk-mmsys: Convert to platform remove callback returning void
soc/mediatek: mtk-devapc: Convert to platform remove callback returning void
soc/loongson: loongson2_guts: Convert to platform remove callback returning void
soc/litex: litex_soc_ctrl: Convert to platform remove callback returning void
soc/ixp4xx: ixp4xx-qmgr: Convert to platform remove callback returning void
soc/ixp4xx: ixp4xx-npe: Convert to platform remove callback returning void
soc/hisilicon: kunpeng_hccs: Convert to platform remove callback returning void
...
|
||
|
Sascha Hauer
|
481d97ba61 |
PM / devfreq: rockchip-dfi: add support for RK3588
Add support for the RK3588 to the driver. The RK3588 has four DDR channels with a register stride of 0x4000 between the channel registers, also it has a DDRMON_CTRL register per channel. Link: https://lore.kernel.org/all/20231018061714.3553817-20-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> |
||
|
Sascha Hauer
|
4d586b5724 |
PM / devfreq: rockchip-dfi: Add perf support
The DFI is a unit which is suitable for measuring DDR utilization, but
so far it could only be used as an event driver for the DDR frequency
scaling driver. This adds perf support to the DFI driver.
Usage with the 'perf' tool can look like:
perf stat -a -e rockchip_ddr/cycles/,\
rockchip_ddr/read-bytes/,\
rockchip_ddr/write-bytes/,\
rockchip_ddr/bytes/ sleep 1
Performance counter stats for 'system wide':
1582524826 rockchip_ddr/cycles/
1802.25 MB rockchip_ddr/read-bytes/
1793.72 MB rockchip_ddr/write-bytes/
3595.90 MB rockchip_ddr/bytes/
1.014369709 seconds time elapsed
perf support has been tested on a RK3568 and a RK3399, the latter with
dual channel DDR.
Link: https://lore.kernel.org/all/20231019064819.3496740-1-s.hauer@pengutronix.de/
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[cw00.choi: Fix typo from 'write_acccess' to 'write_access']
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
|
||
|
Sascha Hauer
|
d8c6e337e7 |
PM / devfreq: rockchip-dfi: Handle LPDDR4X
In the DFI driver LPDDR4X can be handled in the same way as LPDDR4. Add the missing case. Link: https://lore.kernel.org/all/20231018061714.3553817-13-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> |
||
|
Sascha Hauer
|
076b0597f5 |
PM / devfreq: rockchip-dfi: Add RK3568 support
This adds RK3568 support to the DFI driver. Only iniitialization differs from the currently supported RK3399. Link: https://lore.kernel.org/all/20231018061714.3553817-11-s.hauer@pengutronix.de/ Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> |
||
|
Sascha Hauer
|
74002e668d |
PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines
The DDRTYPE defines are named to be RK3399 specific, but they can be used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_ prefix with ROCKCHIP_. They are defined in a SoC specific header file, so when generalizing the prefix also move the new defines to a SoC agnostic header file. While at it use GENMASK to define the DDRTYPE bitfield and give it a name including the full register name. Link: https://lore.kernel.org/all/20231018061714.3553817-9-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> |
||
|
Sumit Gupta
|
ea608a01d4 |
firmware: tegra: Add suspend hook and reset BPMP IPC early on resume
Add suspend hook and a 'suspended' field in the 'struct tegra_bpmp'
to mark if BPMP is suspended. Also, add a 'flags' field in the
'struct tegra_bpmp_message' whose 'TEGRA_BPMP_MESSAGE_RESET' bit can be
set from the Tegra MC driver to signal that the reset of BPMP IPC
channels is required before sending MRQ to the BPMP FW. Together both
the fields allow us to handle any requests that might be sent too soon
as they can cause hang during system resume.
One case where we see BPMP requests being sent before the BPMP driver
has resumed is the memory bandwidth requests which are triggered by
onlining the CPUs during system resume. The CPUs are onlined before the
BPMP has resumed and we need to reset the BPMP IPC channels to handle
these requests.
The additional check for 'flags' is done to avoid any un-intended BPMP
IPC reset if the tegra_bpmp_transfer*() API gets called during suspend
sequence after the BPMP driver is suspended.
Fixes: f41e1442ac5b ("cpufreq: tegra194: add OPP support and set bandwidth")
Co-developed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
||
|
Deming Wang
|
bde3ce7257 |
firmware: tegra: Fix a typo
successfully, not 'succesfully' Signed-off-by: Deming Wang <wangdeming@inspur.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Costa Shulyupin
|
17e02586ed |
docs: move powerpc under arch
and fix all in-tree references. Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Signed-off-by: Costa Shulyupin <costa.shul@redhat.com> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20230826165737.2101199-1-costa.shul@redhat.com |
||
|
Jason Gunthorpe
|
c462944901 |
iommu/tegra-gart: Remove tegra-gart
Thierry says this is not used anymore, and doesn't think it makes sense as
an iommu driver. The HW it supports is about 10 years old now and newer HW
uses different IOMMU drivers.
As this is the only driver with a GART approach, and it doesn't really
meet the driver expectations from the IOMMU core, let's just remove it
so we don't have to think about how to make it fit in.
It has a number of identified problems:
- The assignment of iommu_groups doesn't match the HW behavior
- It claims to have an UNMANAGED domain but it is really an IDENTITY
domain with a translation aperture. This is inconsistent with the core
expectation for security sensitive operations
- It doesn't implement a SW page table under struct iommu_domain so
* It can't accept a map until the domain is attached
* It forgets about all maps after the domain is detached
* It doesn't clear the HW of maps once the domain is detached
(made worse by having the wrong groups)
Cc: Thierry Reding <treding@nvidia.com>
Cc: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/6-v8-81230027b2fa+9d-iommu_all_defdom_jgg@nvidia.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
|
||
|
Linus Torvalds
|
0468be89b3 |
IOMMU Updates for Linux v6.6
Including:
- Core changes:
- Consolidate probe_device path
- Make the PCI-SAC IOVA allocation trick PCI-only
- AMD IOMMU:
- Consolidate PPR log handling
- Interrupt handling improvements
- Refcount fixes for amd_iommu_v2 driver
- Intel VT-d driver:
- Enable idxd device DMA with pasid through iommu dma ops.
- Lift RESV_DIRECT check from VT-d driver to core.
- Miscellaneous cleanups and fixes.
- ARM-SMMU drivers:
- Device-tree binding updates:
- Add additional compatible strings for Qualcomm SoCs
- Allow ASIDs to be configured in the DT to work around Qualcomm's
broken hypervisor
- Fix clocks for Qualcomm's MSM8998 SoC
- SMMUv2:
- Support for Qualcomm's legacy firmware implementation featured on
at least MSM8956 and MSM8976.
- Match compatible strings for Qualcomm SM6350 and SM6375 SoC variants
- SMMUv3:
- Use 'ida' instead of a bitmap for VMID allocation
- Rockchip IOMMU:
- Lift page-table allocation restrictions on newer hardware
- Mediatek IOMMU:
- Add MT8188 IOMMU Support
- Renesas IOMMU:
- Allow PCIe devices
- Usual set of cleanups an smaller fixes
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmTx7IMACgkQK/BELZcB
GuMxUA/+P/wYvAKCbDpXyszIpyCTx37BkeRTBaVqG0vEKLG6439i+PIm3oudQK+6
0y+1clJi0Ddu0uv1ck90cIEP1YDuKaKdrOVeE7TtlK+6LKYxTyeN+mz4csMIbahI
6JMrWzrIEPIyMBHzAepQiGDCsmDkrCngPj0WmA7+EQZSSHVYp+TLe6OLzNs74vDF
zCITkYNq6aKyg/dNJpMRy6VOHvw9PUiwRvm7ko7WONP4VCtpW4g3Jpkerf19zoV2
s0nwZuGn3o7F0aFOpRJPPKQNfQnNjOjHdxjcsGBafD9qqAk4TLvnZH24njKtPidJ
P8CiAu//HxhDyUPTgTIrDroVOGVG7s85XO+WesjPkEI3vnNjXy+qEIinQBJ3oIaI
ppDLSnArEhfSRgt6dXvPCJ/g4+WGS9jNV85GCa7XBtal2Msu8G89NKC97mpmjCkb
lnGmCF9t7Tkt/fLWxw4GADBN3m2tOib1GQMvPYAF2WM3jH5aRq2UliIRuCHZkzwv
EF3SiFQQqab6oogU9tF/A1QLUKQ8QfYOdabqL9z2COgF5tS00VC6b/6VTNkKeBHe
qIiOpI7IWo76tFJule5gRaUth9nVkjpEo6kL9I6rEldOlFJrX6uaHTta6/isY3gx
vkN98V/OThRUbDwMD122YVKNNjZE2MNsTeptXqB3jHvl3UWiLsQ=
=RV+G
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
"Core changes:
- Consolidate probe_device path
- Make the PCI-SAC IOVA allocation trick PCI-only
AMD IOMMU:
- Consolidate PPR log handling
- Interrupt handling improvements
- Refcount fixes for amd_iommu_v2 driver
Intel VT-d driver:
- Enable idxd device DMA with pasid through iommu dma ops
- Lift RESV_DIRECT check from VT-d driver to core
- Miscellaneous cleanups and fixes
ARM-SMMU drivers:
- Device-tree binding updates:
- Add additional compatible strings for Qualcomm SoCs
- Allow ASIDs to be configured in the DT to work around Qualcomm's
broken hypervisor
- Fix clocks for Qualcomm's MSM8998 SoC
- SMMUv2:
- Support for Qualcomm's legacy firmware implementation featured
on at least MSM8956 and MSM8976
- Match compatible strings for Qualcomm SM6350 and SM6375 SoC
variants
- SMMUv3:
- Use 'ida' instead of a bitmap for VMID allocation
- Rockchip IOMMU:
- Lift page-table allocation restrictions on newer hardware
- Mediatek IOMMU:
- Add MT8188 IOMMU Support
- Renesas IOMMU:
- Allow PCIe devices
.. and the usual set of cleanups an smaller fixes"
* tag 'iommu-updates-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (64 commits)
iommu: Explicitly include correct DT includes
iommu/amd: Remove unused declarations
iommu/arm-smmu-qcom: Add SM6375 SMMUv2
iommu/arm-smmu-qcom: Add SM6350 DPU compatible
iommu/arm-smmu-qcom: Add SM6375 DPU compatible
iommu/arm-smmu-qcom: Sort the compatible list alphabetically
dt-bindings: arm-smmu: Fix MSM8998 clocks description
iommu/vt-d: Remove unused extern declaration dmar_parse_dev_scope()
iommu/vt-d: Fix to convert mm pfn to dma pfn
iommu/vt-d: Fix to flush cache of PASID directory table
iommu/vt-d: Remove rmrr check in domain attaching device path
iommu: Prevent RESV_DIRECT devices from blocking domains
dmaengine/idxd: Re-enable kernel workqueue under DMA API
iommu/vt-d: Add set_dev_pasid callback for dma domain
iommu/vt-d: Prepare for set_dev_pasid callback
iommu/vt-d: Make prq draining code generic
iommu/vt-d: Remove pasid_mutex
iommu/vt-d: Add domain_flush_pasid_iotlb()
iommu: Move global PASID allocation from SVA to core
iommu: Generalize PASID 0 for normal DMA w/o PASID
...
|
||
|
Linus Torvalds
|
f8fd5c2483 |
This pull request is full of clk driver changes. In fact, there aren't any
changes to the clk framework this time around. That's probably because everyone
was on vacation (yours truly included). We did lose a couple clk drivers this
time around because nobody was using those devices. That skews the diffstat a
bit, but either way, nothing looks out of the ordinary here. The usual suspects
are chugging along adding support for more SoCs and fixing bugs.
If I had to choose, I'd say the theme for the past few months has been
"polish". There's quite a few patches that migrate to
devm_platform_ioremap_resource() in here. And there's more than a handful of
patches that move the NR_CLKS define from the DT binding header to the driver.
There's even patches that migrate drivers to use clk_parent_data and clk_hw to
describe clk tree topology. It seems that the spring (summer?) cleaning bug got
some folks, or the semiconductor shortage finally hit the software side.
New Drivers:
- StarFive JH7110 SoC clock drivers
- Qualcomm IPQ5018 Global Clock Controller driver
- Versa3 clk generator to support 48KHz playback/record with audio codec on
RZ/G2L SMARC EVK
Removed Drivers:
- Remove non-OF mmp clk drivers
- Remove OXNAS clk driver
Updates:
- Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
- Move defines for numbers of clks (NR_CLKS) from DT headers to drivers
- Introduce kstrdup_and_replace() and use it
- Add PLL rates for Rockchip rk3568
- Add the display clock tree for Rockchip rv1126
- Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs
- Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource()
- Fix function name in a comment in ccu_mmc_timing.c
- Parameter name correction for ccu_nkm_round_rate()
- Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative
parent rates when determining clock rates
- Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
- Support finding closest (as opposed to closest but not higher) clock rate
for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0
- Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks
- Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to
the interconnect drivers
- Fix various PM runtime bugs across many Qualcomm clk drivers
- Migrate Qualcomm MDM9615 is to parent_hw and parent_data
- Add network related resets on Qualcomm IPQ4019
- Add a couple missing USB related clocks to Qualcomm IPQ9574
- Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller
- In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are
added, while PCIe pipe clock, SDCC rcg ops are corrected
- Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver
- Support retention for the Qualcomm SC8280XP display clock controller GDSCs.
- Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix
issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250,
while sm8450 is corrected to use floor ops
- Correct Qualcomm SM6350 GPU clock controller's clock supplies
- Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
- Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
- Change the delay in the Qualcomm reset controller to fsleep() for correctness
- Extend the Qualcomm SM83550 Video clock controller to support SC8280XP
- Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3,
M3-W, and M3-N SoCs
- Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
- Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
- Add the PDM IPC clock for i.MX93
- Add 519.75MHz frequency support for i.MX9 PLL
- Simplify the .determine_rate() implementation for i.MX GPR mux
- Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
- Add the audio mux clock to i.MX8
- Fix the SPLL2 MULT range for PLLv4
- Update the SPLL2 type in i.MX8ULP
- Fix the SAI4 clock on i.MX8MP
- Add silicon revision print for i.MX25 on clocks init
- Drop the return value from __mx25_clocks_init()
- Fix the clock pauses on no-op set_rate for i.MX8M composite clock
- Drop restrictions for i.MX PLL14xx and fix its max prediv value
- Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow
glitch free switching
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmTv2wkRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSW1LRAAuHR2HoyB4bRHmCa1bfOfYYDfSWsBWEav
tWIfBl86Nl/Je50Gk2NJ9vqU5OPqRZ57TIniijHHoX5n7/kYcr8KVmlomY07hUeg
CzWyothkxg4k7+rQwVAWvmlR2YAVwzHDKcwq7gkMZOnW/y26LXip99cjopu2CJLx
zVwTgvWollmd4KVlicnAlx4zUjgNkWR24iA4Lcf5ir+Dr6FYNjxLI+akBA8EPxxi
wLixZbScgBSgpGn6KVgoFhclCToPS0gt5m6HfQxJ/svOCU54l+jRKpzkNZGWvyu4
A8t3CRrwL2iS/mfCGk2yRlaKySoLLpjlpW1AI7fHTWbG2P6p8ZphtN7jOeeAEsbq
TNpzWEjtY6B/lfRzxxINXkrtLaqmlnFY/P5np5fDrf/61gRFxLFQemyRdY/xCSJf
Kwq8ja1mrSGWoDGG9XhDqTf9Yek9LRObNzlDrEmn/i/qLTcxhOIz58pzHg4iAlx5
9HDtnJ8hKg4uE1TtT12Bmasb1+WzG7GYYESNfKWZhCvbRqEUzcDOHk7xpwYa1ffx
yZIgMs7Sb/exNW8LMPYmgnyj/f9eo5IdjiQvune+Zy5NrdzfyN6Sf/LSibrqCF2z
X5aFHqQrR8+PifD+se+g5HPa0ezSmBIhXzYUTOC6f+nywlrJjhwDXPDYI6Lcd//p
r4mpOmJS+G4=
=h2Jz
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk subsystem updates from Stephen Boyd:
"This pull request is full of clk driver changes. In fact, there aren't
any changes to the clk framework this time around. That's probably
because everyone was on vacation (yours truly included). We did lose a
couple clk drivers this time around because nobody was using those
devices. That skews the diffstat a bit, but either way, nothing looks
out of the ordinary here. The usual suspects are chugging along adding
support for more SoCs and fixing bugs.
If I had to choose, I'd say the theme for the past few months has been
"polish". There's quite a few patches that migrate to
devm_platform_ioremap_resource() in here. And there's more than a
handful of patches that move the NR_CLKS define from the DT binding
header to the driver. There's even patches that migrate drivers to use
clk_parent_data and clk_hw to describe clk tree topology. It seems
that the spring (summer?) cleaning bug got some folks, or the
semiconductor shortage finally hit the software side.
New Drivers:
- StarFive JH7110 SoC clock drivers
- Qualcomm IPQ5018 Global Clock Controller driver
- Versa3 clk generator to support 48KHz playback/record with audio
codec on RZ/G2L SMARC EVK
Removed Drivers:
- Remove non-OF mmp clk drivers
- Remove OXNAS clk driver
Updates:
- Add __counted_by to struct clk_hw_onecell_data and struct
spmi_pmic_div_clk_cc
- Move defines for numbers of clks (NR_CLKS) from DT headers to
drivers
- Introduce kstrdup_and_replace() and use it
- Add PLL rates for Rockchip rk3568
- Add the display clock tree for Rockchip rv1126
- Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and
RZ/G2 SoCs
- Convert sun9i-mmc clock to use
devm_platform_get_and_ioremap_resource()
- Fix function name in a comment in ccu_mmc_timing.c
- Parameter name correction for ccu_nkm_round_rate()
- Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e.
consider alternative parent rates when determining clock rates
- Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
- Support finding closest (as opposed to closest but not higher)
clock rate for NM, NKM, mux and div type clocks, as use it for
Allwinner A64 pll-video0
- Prefer current parent rate if able to generate ideal clock rate for
Allwinner NKM clocks
- Clean up Qualcomm SMD RPM driver, with interconnect bus clocks
moved out to the interconnect drivers
- Fix various PM runtime bugs across many Qualcomm clk drivers
- Migrate Qualcomm MDM9615 is to parent_hw and parent_data
- Add network related resets on Qualcomm IPQ4019
- Add a couple missing USB related clocks to Qualcomm IPQ9574
- Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock
controller
- In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs,
and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are
corrected
- Add missing GDSCs to and correct GDSCs for the SC8280XP global
clock controller driver
- Support retention for the Qualcomm SC8280XP display clock
controller GDSCs.
- Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE
to fix issues with missing parent clocks across sc7180, sm7150,
sm6350 and sm8250, while sm8450 is corrected to use floor ops
- Correct Qualcomm SM6350 GPU clock controller's clock supplies
- Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
- Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
- Change the delay in the Qualcomm reset controller to fsleep() for
correctness
- Extend the Qualcomm SM83550 Video clock controller to support
SC8280XP
- Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and
R-Car H3, M3-W, and M3-N SoCs
- Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
- Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
- Add the PDM IPC clock for i.MX93
- Add 519.75MHz frequency support for i.MX9 PLL
- Simplify the .determine_rate() implementation for i.MX GPR mux
- Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
- Add the audio mux clock to i.MX8
- Fix the SPLL2 MULT range for PLLv4
- Update the SPLL2 type in i.MX8ULP
- Fix the SAI4 clock on i.MX8MP
- Add silicon revision print for i.MX25 on clocks init
- Drop the return value from __mx25_clocks_init()
- Fix the clock pauses on no-op set_rate for i.MX8M composite clock
- Drop restrictions for i.MX PLL14xx and fix its max prediv value
- Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to
allow glitch free switching"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits)
clk: qcom: Fix SM_GPUCC_8450 dependencies
clk: lmk04832: Support using PLL1_LD as SPI readback pin
clk: lmk04832: Don't disable vco clock on probe fail
clk: lmk04832: Set missing parent_names for output clocks
clk: mvebu: Convert to devm_platform_ioremap_resource()
clk: nuvoton: Convert to devm_platform_ioremap_resource()
clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
clk: ti: Use devm_platform_get_and_ioremap_resource()
clk: mediatek: Convert to devm_platform_ioremap_resource()
clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
clk: gemini: Convert to devm_platform_ioremap_resource()
clk: fsl-sai: Convert to devm_platform_ioremap_resource()
clk: bm1880: Convert to devm_platform_ioremap_resource()
clk: axm5516: Convert to devm_platform_ioremap_resource()
clk: actions: Convert to devm_platform_ioremap_resource()
clk: cdce925: Remove redundant of_match_ptr()
clk: pxa910: Move number of clocks to driver source
clk: pxa1928: Move number of clocks to driver source
clk: pxa168: Move number of clocks to driver source
clk: mmp2: Move number of clocks to driver source
...
|
||
|
Linus Torvalds
|
a1c19328a1 |
ARM: SoC cleanups for 6.6
These are all minor cleanups for platform specific code in arch/arm/ and some of the associated drivers. The majority of these are work done by Rob Herring to improve the way devicetreee header files are handled. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTuaDEACgkQYKtH/8kJ UicmKQ/6A506T45KbbCLsqMuJsGdjMdOKdBecssLWhFNhRoJhJB6YilQVjBUAK4D vDqc425IcxXwaW+4OVBFCgVpKKMlrLSpHVJHl6QaGsxAZt5xdhwcA4ttQcFvoQtK csuwOadO9g1K4Px29J8GFR/FvFNt8kHRxbRC3xcGfFsFvgXISAiLUv8w6Z5O8Z5W /sp+EsOkJWTTKu+vtcMXccGqM9eGNOfPK1bCUElJ1+HW3jZrbRw0zZrQ2QS72N2P wpO2f6JUTpiiMH8XhQd3REi3Kli+g0GxVlCStZc/0qf/uW70YanF4CPDdSOVJ5OL l05Qfx+/XsGyqt3el03UoIXfM1YzvWn5BeqNG/QGHkai7Lp/c8LvSk1NiwaS0dzi QcPCEK67wjoaBCdSAMKGYM/qlmffuLh9/NJM5dzdBE8zQ5rC1XorR2aHGyISQJt6 tDlDXy14zyR3KRxOoqP6cWp+PFDcBksd44cxGbp/Lcc389UKxX8j4fM8yUNT+4Rh gZ5OtUMs5QhFJBhBbBxW6O3TMuhwjSdW7IEQafKiiHEOFucf6Zcxd9u9B2yzsdtU za6mpA/NEBIc3olv6IFIdT24+M3PLhqCbu6YL5YI4jBf0QNpXjRBr+EOtvt2mvC9 JkoggyCf5LdDt833G/TBPpx0VYi8h0m7cQnMw4JjOIA8FvCwIdc= =c9NM -----END PGP SIGNATURE----- Merge tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC cleanups from Arnd Bergmann: "These are all minor cleanups for platform specific code in arch/arm/ and some of the associated drivers. The majority of these are work done by Rob Herring to improve the way devicetreee header files are handled" * tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (49 commits) ARM: davinci: Drop unused includes ARM: s5pv210: Explicitly include correct DT includes ARM: dove: Drop unused includes ARM: mvebu: Explicitly include correct DT includes Documentation/process: maintainer-soc: document dtbs_check requirement for Samsung MAINTAINER: samsung: document dtbs_check requirement for Samsung Documentation/process: maintainer-soc: add clean platforms profile MAINTAINERS: soc: reference maintainer profile ARM: nspire: Remove unused header file mmio.h ARM: nspire: Use syscon-reboot to handle restart soc: fsl: Explicitly include correct DT includes soc: xilinx: Explicitly include correct DT includes soc: sunxi: Explicitly include correct DT includes soc: rockchip: Explicitly include correct DT includes soc: mediatek: Explicitly include correct DT includes soc: aspeed: Explicitly include correct DT includes firmware: Explicitly include correct DT includes bus: Explicitly include correct DT includes ARM: spear: Explicitly include correct DT includes ARM: mvebu: Explicitly include correct DT includes ... |
||
|
Yue Haibing
|
49e62a0462 |
net: mscc: ocelot: Remove unused declarations
Commit 6c30384eb1de ("net: mscc: ocelot: register devlink ports")
declared but never implemented ocelot_devlink_init() and
ocelot_devlink_teardown().
Commit 2096805497e2 ("net: mscc: ocelot: automatically detect VCAP constants")
declared but never implemented ocelot_detect_vcap_constants().
Commit 403ffc2c34de ("net: mscc: ocelot: add support for preemptible traffic classes")
declared but never implemented ocelot_port_update_preemptible_tcs().
Signed-off-by: Yue Haibing <yuehaibing@huawei.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20230821130218.19096-1-yuehaibing@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
||
|
Joerg Roedel
|
d8fe59f110 | Merge branches 'apple/dart', 'arm/mediatek', 'arm/renesas', 'arm/rockchip', 'arm/smmu', 'unisoc', 'x86/vt-d', 'x86/amd' and 'core' into next | ||
|
Martin Kaiser
|
b8a06b125c |
clk: imx25: print silicon revision during init
Print the imx25 silicon revision when the clocks are initialised. Use the same mechanism as for imx27, i.e. call mx25_revision. This function is unused at the moment. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230802184046.153394-2-martin@kaiser.cx Signed-off-by: Abel Vesa <abel.vesa@linaro.org> |
||
|
Arnd Bergmann
|
61029e2b37 |
AT91 SoC updates for 6.6:
It contains: - explicitly include correct DT includes from Rob - one cleanup which removes unused extern declaration on atmel_tcb.h -----BEGIN PGP SIGNATURE----- iI8EABYIADcWIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCZMx+PxkcY2xhdWRpdS5i ZXpuZWFAZ21haWwuY29tAAoJEJ6OuD83Zfv9RHAA/jMPJ6uQKDDP9iYzJD4moCC2 H614pQHGJx8PLnxt7kPaAP4xrN1l9+Yo0+31r8bDSjGBksmOK0g262shKXgsY79G AA== =ab+a -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXQ7MACgkQYKtH/8kJ Uidn1BAAuEEA+N3YAf6gRBQ7xJ1y+UuZr945SjKWZtU4gvKB04a8N1VdIGMUCP5Z QlmaXbMwrALPfs4oqu4NmjI5MsB9IZNLKb35C5LUAltHTfaG36FLmbrs0kIbQ6I9 ES3Sr5rHM+ec7RewbuVqx3DK4VzJJQN++CECTkRH9j6cGkGIGRyCtD3jHp+LROv0 73UJ0Iv7FBkDNprhhCjhSQwUiTb0kHiRORhOnvle6JcnIYHaN41/qL1M0VRVBmsb HQAT2KH7c2Br9hSTNYBJG77RXNt50CNIM5fviGFTQw+d6OugDjNwsrRzKFrM4uR+ XDHAAL9GK/QEZ2UClCuYY8q1oezoVeUjUZw70PzU8I6lXDi9373pY1E/K3HIG7WZ y7NrWLGCzxpc2/OBBNl57hiMbqdnV+a+53VMpKLtjobt3xHVMzpoluf1KRKcqf9Z SmOYV8wZs+pCAtTYBj5+RfQuLfTmJHRbSB42DHMWncHt5hRbGmAvTLMEPFy7Gyyw ogKN2VsqViQS0C5pI0EO4119Pv4OPJzJP1qvmtZgZbwMj7WVLaOq3tri6fNuIIsy Uy+uuEFyppAsegJ7VQmpsk8ql+R0XAc0fk8hw+iob+S0hPPBoSEtemL8mkYurTuN WeKTk1AHPtl5Ty7Fvo32G38SDxwuuBbc67IbiPzN44UZ6gATa+g= =8ksf -----END PGP SIGNATURE----- Merge tag 'at91-soc-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm AT91 SoC updates for 6.6: It contains: - explicitly include correct DT includes from Rob - one cleanup which removes unused extern declaration on atmel_tcb.h * tag 'at91-soc-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: Remove unused extern declarations ARM: at91: Explicitly include correct DT includes soc: microchip: Explicitly include correct DT includes Link: https://lore.kernel.org/r/20230804044118.231478-1-claudiu.beznea@tuxon.dev Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Chengci.Xu
|
946e719ce6 |
iommu/mediatek: Add enable IOMMU SMC command for INFRA masters
Prepare for MT8188. In MT8188, the register which enables IOMMU for INFRA masters are in the secure world for security concerns, therefore we add a SMC command for INFRA masters to enable IOMMU in ATF. Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230602090227.7264-5-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de> |
||
|
YueHaibing
|
96a49448c4 |
ARM: at91: Remove unused extern declarations
commit 157576d55233 ("misc: remove atmel_tclib")
left behind this.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20230725141105.26904-1-yuehaibing@huawei.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||
|
Arnd Bergmann
|
b1e052903c |
Memory controller drivers - fixes for v6.5
Two fixes are needed for Tegra194 memory controllers caused by the same Tegra PCI commit merged in v6.5-rc1. The Tegra PCI requires now interconnect from the memory controller, which was set only for Tegra234, but not for Tegra194, causing probe deferrals. Expose some dummy interconnect provider for Tegra194, to satisfy PCI driver needs. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmTA3VAQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1zj9D/4peXLyTUWFArNLAaq3PbOHQRuPbC1MMdWN VRCqjDVGNXEYPnbh1b2kMhi2iwoBk9HeAt6HFYHgABdNZBK5VBUMDuJnT1ocNExD 8OBV3qAM+ia3TqOlhE5PVGiMudhd1R020/tIrzHB+YaiT2JpqKXo8nlXVfhwti1c yyZmIAmi9uQkC3Zn7R+5I0A5atNLa7BXAmpy8A/l7K8ojwnAxiJLXAI/+YHs0moW GPB9Nk4oYzEJDyQESKNK0ddvggwaZNCbK+wIBcEBFXXvybVr72pMYSeIG+UNpTf+ uwc5nxgHwhqNTxO4WtGYpVuAA8uPelJ4YIbcEdoJoNn5/dfzdiBYhetWPquOBMxN p1BIVx/pFujzAAjY2VvPAEbSxctMUKmLmRRAbJC3II633JxjwKahVMTOCslvtuSr /jbChJ4Ih2RL15qMmj2O/mP2qjivG/HoywtG3Rp4w5E6CfWXs3b6ytEKdifW9IEk GjctklZm1E8Jz+nVhmPfm1A+pLxG80RMEgV9kp5bEjdeNjE/SQByTlhCxP/1SSHA yT4RO3GFdBFKjpfl2xK1f74ml/ZA9KOu8WO+laD0gZVfMzX68wQWc2jIpJYtPhtO p8n8zzC2fEbzvY1Adth7XR79P1e/3yp2NZv1vTRIP6T4y+d8e2v2mqNxZxH/SFRj PS2KDX7VMw== =1ARR -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTCc+YACgkQYKtH/8kJ UifQjQ//bIgDWLc6LsU0wnF8CEScqAxvTmXMXq0tp8o55uvUjdCjdNHRkrxQuPff /vfXJAhzvLlsovR/DghTeex8V1O1285TDt20J0UXXA7PdGTzvpjjW/+qH8OmmRDV IvP8WUWHHbgazJZaayYMLn5uAf1Ofz8ZzTkbrdYKQ9eORhwdMWC6bDNJHZF2cxEa X82FGvYL270x4IhIQpt5yg5aDFKCX6n/SEYb8H3kX61qb1TIQ1Yo3Fsr0Wr7L/1Y 6esl0zmMo7k0Jv9+9wA3u6AhYoYq6F9EvaQk9MdizG2h44o7MiO7SrSoEHuFbMbp NAyah59WSSiFV3GL9oKchgKFVqXwqiF0YZJyNTetbg70AK3Q9Yu0CDVuQFKvLtkN jh3t3XxBkX8YizDQQCCkxULEaqR2UpamoHXnnt84L4g92hYRLv0wXGWLQrAxKzIP jU+foYfkAfglfpdGI9pvz0gqdsvTfmFKKoLdlkCwgckWkydq9ZuVkAmuYFN17v2o /ihwqgZHFBZeXbLGmplb0uAHOJ7NymyNjVOSK+1C7m1WOcX4k43/MGk8KVYTuWXF V7PwiG2miUbUwkqRTUTsu+S4G7rF5MM8NoT8jLWHvlVqdig8Z5hbyvV2jPaLgEbT Z0lpoRNhBa5UP1Wgu0LNkuHPPCA7J0VVqnTCf1Wj7HrS7/rn57M= =NC+w -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-fixes-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/fixes Memory controller drivers - fixes for v6.5 Two fixes are needed for Tegra194 memory controllers caused by the same Tegra PCI commit merged in v6.5-rc1. The Tegra PCI requires now interconnect from the memory controller, which was set only for Tegra234, but not for Tegra194, causing probe deferrals. Expose some dummy interconnect provider for Tegra194, to satisfy PCI driver needs. * tag 'memory-controller-drv-fixes-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: tegra: make icc_set_bw return zero if BWMGR not supported memory: tegra: Add dummy implementation on Tegra194 Link: https://lore.kernel.org/r/20230726084811.124038-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Thierry Reding
|
d1478aea64 |
memory: tegra: Add dummy implementation on Tegra194
With the introduction of commit 9365bf006f53 ("PCI: tegra194: Add
interconnect support in Tegra234"), the PCI driver on Tegra194 and later
requires an interconnect provider. However, a provider is currently only
exposed on Tegra234 and this causes PCI on Tegra194 to defer probe
indefinitely.
Fix this by adding a dummy implementation on Tegra194. This allows nodes
to be provided to interconnect consumers, but doesn't do any bandwidth
accounting or frequency scaling.
Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234")
Reported-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Sumit Gupta <sumitg@nvidia.com>
Tested-by: Sumit Gupta <sumitg@nvidia.com>
Link: https://lore.kernel.org/r/20230629160132.768940-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||
|
Vladimir Oltean
|
c60819149b |
net: dsa: felix: make vsc9959_tas_guard_bands_update() visible to ocelot->ops
In a future change we will need to make ocelot_port_update_active_preemptible_tcs() call vsc9959_tas_guard_bands_update(), but that is currently not possible, since the ocelot switch lib does not have access to functions private to the DSA wrapper. Move the pointer to vsc9959_tas_guard_bands_update() from felix->info (which is private to the DSA driver) to ocelot->ops (which is also visible to the ocelot switch lib). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20230705104422.49025-3-vladimir.oltean@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
||
|
Vladimir Oltean
|
009d30f1a7 |
net: mscc: ocelot: extend ocelot->fwd_domain_lock to cover ocelot->tas_lock
In a future commit we will have to call vsc9959_tas_guard_bands_update()
from ocelot_port_update_active_preemptible_tcs(), and that will be
impossible due to the AB/BA locking dependencies between
ocelot->tas_lock and ocelot->fwd_domain_lock.
Just like we did in commit 3ff468ef987e ("net: mscc: ocelot: remove
struct ocelot_mm_state :: lock"), the only solution is to expand the
scope of ocelot->fwd_domain_lock for it to also serialize changes made
to the Time-Aware Shaper, because those will have to result in a
recalculation of cut-through TCs, which is something that depends on the
forwarding domain.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Message-ID: <20230705104422.49025-2-vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
||
|
Linus Torvalds
|
6843306689 |
Including fixes from bluetooth, bpf and wireguard.
Current release - regressions:
- nvme-tcp: fix comma-related oops after sendpage changes
Current release - new code bugs:
- ptp: make max_phase_adjustment sysfs device attribute invisible
when not supported
Previous releases - regressions:
- sctp: fix potential deadlock on &net->sctp.addr_wq_lock
- mptcp:
- ensure subflow is unhashed before cleaning the backlog
- do not rely on implicit state check in mptcp_listen()
Previous releases - always broken:
- net: fix net_dev_start_xmit trace event vs skb_transport_offset()
- Bluetooth:
- fix use-bdaddr-property quirk
- L2CAP: fix multiple UaFs
- ISO: use hci_sync for setting CIG parameters
- hci_event: fix Set CIG Parameters error status handling
- hci_event: fix parsing of CIS Established Event
- MGMT: fix marking SCAN_RSP as not connectable
- wireguard: queuing: use saner cpu selection wrapping
- sched: act_ipt: various bug fixes for iptables <> TC interactions
- sched: act_pedit: add size check for TCA_PEDIT_PARMS_EX
- dsa: fixes for receiving PTP packets with 8021q and sja1105 tagging
- eth: sfc: fix null-deref in devlink port without MAE access
- eth: ibmvnic: do not reset dql stats on NON_FATAL err
Misc:
- xsk: honor SO_BINDTODEVICE on bind
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE6jPA+I1ugmIBA4hXMUZtbf5SIrsFAmSlu+MACgkQMUZtbf5S
Irslgw//S7jf/GL8V6y8VL3te+/OPOZnLDTzFFOdy64/y97FE6XIacJUpyWRhtmz
oSzcSNHETPW9U+xSGa2ZQlKhAXt6n9iRNvUegql+VBb13Iz+l7AdTeoxRv/YuwDo
5lTOIB6cBw+ATd0oxS6wr8SyUlcvktUKBfTAItjbVM55aXfIUpXIa84+F7avJgIA
XP1u/3PHhwItmwo/hXhHH0+P0QA8ix1q2SvRB7DAlQLBsTuQhaKjXWQkYYTKw/Nt
dtvh8iQSs/YXaHMjTa5CK28HOD8+ywIizr+uJ9VaNqIzV0W5JE9IE8P4NFpBcY7t
kGjTYODOph7dkNmZ5RLj3N+B6CyC57OXDzoo/tr8940UytCLVj9EVyduarLGLx57
edqK9cUz5kWejyGoyZ4Pvlo/SKvCQ2HKMeiAJ0/nNpTJMFuygMoqGsaD6ttzkXMj
fZLPjRUK3axd+15ZzhLEf8HyL5Qh+qPqqX9p7NljfMKwhxMWJ5fuICJfdGOSdMJR
ndL+wPfRPFQwszZ4pbTY2Ivn29mo8ScBOSOEgQs2mOny+zFzTzmqNWz/jcFfQnjS
cylxBEHrgudT2FuCImZ/v66TM5yakHXqIdpTGG+zsvJWQqjM96Z3I7WRvi0g9d75
n84il+j34mnzl90j2xEutqUiK7BQ9ZpZBsutPVTKBIHKWWiortI=
=9yzk
-----END PGP SIGNATURE-----
Merge tag 'net-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Pull networking fixes from Jakub Kicinski:
"Including fixes from bluetooth, bpf and wireguard.
Current release - regressions:
- nvme-tcp: fix comma-related oops after sendpage changes
Current release - new code bugs:
- ptp: make max_phase_adjustment sysfs device attribute invisible
when not supported
Previous releases - regressions:
- sctp: fix potential deadlock on &net->sctp.addr_wq_lock
- mptcp:
- ensure subflow is unhashed before cleaning the backlog
- do not rely on implicit state check in mptcp_listen()
Previous releases - always broken:
- net: fix net_dev_start_xmit trace event vs skb_transport_offset()
- Bluetooth:
- fix use-bdaddr-property quirk
- L2CAP: fix multiple UaFs
- ISO: use hci_sync for setting CIG parameters
- hci_event: fix Set CIG Parameters error status handling
- hci_event: fix parsing of CIS Established Event
- MGMT: fix marking SCAN_RSP as not connectable
- wireguard: queuing: use saner cpu selection wrapping
- sched: act_ipt: various bug fixes for iptables <> TC interactions
- sched: act_pedit: add size check for TCA_PEDIT_PARMS_EX
- dsa: fixes for receiving PTP packets with 8021q and sja1105 tagging
- eth: sfc: fix null-deref in devlink port without MAE access
- eth: ibmvnic: do not reset dql stats on NON_FATAL err
Misc:
- xsk: honor SO_BINDTODEVICE on bind"
* tag 'net-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (70 commits)
nfp: clean mc addresses in application firmware when closing port
selftests: mptcp: pm_nl_ctl: fix 32-bit support
selftests: mptcp: depend on SYN_COOKIES
selftests: mptcp: userspace_pm: report errors with 'remove' tests
selftests: mptcp: userspace_pm: use correct server port
selftests: mptcp: sockopt: return error if wrong mark
selftests: mptcp: sockopt: use 'iptables-legacy' if available
selftests: mptcp: connect: fail if nft supposed to work
mptcp: do not rely on implicit state check in mptcp_listen()
mptcp: ensure subflow is unhashed before cleaning the backlog
s390/qeth: Fix vipa deletion
octeontx-af: fix hardware timestamp configuration
net: dsa: sja1105: always enable the send_meta options
net: dsa: tag_sja1105: fix MAC DA patching from meta frames
net: Replace strlcpy with strscpy
pptp: Fix fib lookup calls.
mlxsw: spectrum_router: Fix an IS_ERR() vs NULL check
net/sched: act_pedit: Add size check for TCA_PEDIT_PARMS_EX
xsk: Honor SO_BINDTODEVICE on bind
ptp: Make max_phase_adjustment sysfs device attribute invisible when not supported
...
|
||
|
Linus Torvalds
|
e4c8d01865 |
ARM: SoC drivers for 6.5
Nothing surprising in the SoC specific drivers, with the usual updates:
* Added or improved SoC driver support for Tegra234, Exynos4121, RK3588,
as well as multiple Mediatek and Qualcomm chips
* SCMI firmware gains support for multiple SMC/HVC transport and version
3.2 of the protocol
* Cleanups amd minor changes for the reset controller, memory controller,
firmware and sram drivers
* Minor changes to amd/xilinx, samsung, tegra, nxp, ti, qualcomm,
amlogic and renesas SoC specific drivers
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSdmbIACgkQYKtH/8kJ
UicewQ/6Aq8j5pBFYBimZoyQ0bi9z+prGrHoDDYLew2vKjtOXJl5z7ZnM3J1oyPt
Zvis3IaGkHJCuuqotPdsquZrzHq8slzXzwkHPfHORJBC4gV0V/vMS8w32tO5FfTq
ULrMyWnbsU7Udeywc2xuEpAoC9+bXX9brnCpa3H41peIGZKM+0g7EE6FASt3YaOk
O+ZMSGqF8QbCqSQrUH3GudFlFMy/VxIvwuUsbLt8aNkRACunQZXVgUdArvLV49nX
SElFN7hOVRoVDv0rgYMxlwElymrta/kMyjLba8GU1GIhzyDGozVqIJQAnsQ3f6CC
yyzaJm27zzJH0mx9jx4W+JLBdjqDL4ctE2WyllRVIpTGYMHiMQtutHNwtNupIuD5
j9j/fIVQWZqOdWXnA6V/CHYN1MZBRTH3KQcnLlYPC01dWKThPDnrHGfwOkfsrwtN
zuERJJ+gd5b8KW4dmy1ueDOSB8162LxbS7iHxpOBGySmqVOYj3XUqACZhKRfXfIQ
BVj9punCE/gO2fMb9IZByjeOzgtV+PBRmPxoglyaGkT4fVfL06kEbpKFYbXXq9b/
aAS/U84gGr8ebWsOXszwDnBzTZRzjMVv/T9KDTTJuWbBEPNyCR7fUG0cZ50rSKnJ
2cTPe3a0sS6LaBt71qfExCIfxG+cJ2c3N1U5/jb2C49Aob45obs=
=zvLr
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Nothing surprising in the SoC specific drivers, with the usual
updates:
- Added or improved SoC driver support for Tegra234, Exynos4121,
RK3588, as well as multiple Mediatek and Qualcomm chips
- SCMI firmware gains support for multiple SMC/HVC transport and
version 3.2 of the protocol
- Cleanups amd minor changes for the reset controller, memory
controller, firmware and sram drivers
- Minor changes to amd/xilinx, samsung, tegra, nxp, ti, qualcomm,
amlogic and renesas SoC specific drivers"
* tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (118 commits)
dt-bindings: interrupt-controller: Convert Amlogic Meson GPIO interrupt controller binding
MAINTAINERS: add PHY-related files to Amlogic SoC file list
drivers: meson: secure-pwrc: always enable DMA domain
tee: optee: Use kmemdup() to replace kmalloc + memcpy
soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer
dt-bindings: sram: qcom,imem: document qdu1000
soc: qcom: icc-bwmon: Fix MSM8998 count unit
dt-bindings: soc: qcom,rpmh-rsc: Require power-domains
soc: qcom: socinfo: Add Soc ID for IPQ5300
dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
soc: qcom: Fix a IS_ERR() vs NULL bug in probe
soc: qcom: socinfo: Add support for new fields in revision 19
soc: qcom: socinfo: Add support for new fields in revision 18
dt-bindings: firmware: scm: Add compatible for SDX75
soc: qcom: mdt_loader: Fix split image detection
dt-bindings: memory-controllers: drop unneeded quotes
soc: rockchip: dtpm: use C99 array init syntax
firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
soc/tegra: pmc: Use devm_clk_notifier_register()
soc/tegra: pmc: Simplify debugfs initialization
...
|
||
|
Vladimir Oltean
|
45d0fcb5bc |
net: mscc: ocelot: don't keep PTP configuration of all ports in single structure
In a future change, the driver will need to determine whether PTP RX
timestamping is enabled on a port (including whether traps were set up
on that port in particular) and that is currently not possible.
The driver supports different RX filters (L2, L4) and kinds of TX
timestamping (one-step, two-step) on its ports, but it saves all
configuration in a single struct hwtstamp_config that is global to the
switch. So, the latest timestamping configuration on one port
(including a request to disable timestamping) affects what gets reported
for all ports, even though the configuration itself is still individual
to each port.
The port timestamping configurations are only coupled because of the
common structure, so replace the hwtstamp_config with a mask of trapped
protocols saved per port. We also have the ptp_cmd to distinguish
between one-step and two-step PTP timestamping, so with those 2 bits of
information we can fully reconstruct a descriptive struct
hwtstamp_config for each port, during the SIOCGHWTSTAMP ioctl.
Fixes: 4e3b0468e6d7 ("net: mscc: PTP Hardware Clock (PHC) support")
Fixes: 96ca08c05838 ("net: mscc: ocelot: set up traps for PTP packets")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
|
||
|
Uwe Kleine-König
|
281bf6b94a |
clocksource/drivers/imx-gpt: Fold <soc/imx/timer.h> into its only user
Only the imx-gpt timer driver makes use of enum imx_gpt_type that is otherwise unused. Move its definition into the timer-imx-gpt driver. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230328100531.879485-3-u.kleine-koenig@pengutronix.de |
||
|
Arnd Bergmann
|
095ee35a33 |
memory: tegra: Changes for v6.5-rc1
This introduces an interconnect provider for the memory controller and external memory controller found on Tegra234 chips that will eventually be used to dynamically scale the EMC frequency based on a device's bandwidth needs. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmSDRTcTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoaKyD/4sjVTfnZ9YoXkcPFd6zr1I8pNMC2pk yyDtSHN0EGcw5goSHF+Akqv5O0JEh8YAW0pQ+fxO3KdEGlZEYNBlC9rgjpz7TzHE 6zsajiIvLYOwSTbjVVlFn2U4H6ihFdawzag/vRDqu1b3wExus9VigWnEgHtj/RJT q1ODZXkwZrOBR3Z034ji6jJIQXVg54sEvt/Zlq7iYXabLXg8u5NDEbSd4GVBNwPB SwBUfc9ja/Y5xUKaXA/hqQ7gIfm4Hs5XVyCbLT75j259qVantbxtlURB3cme080m rRdyScngYFxuyBzQtQzLq+6u5tYJN6q3WUlXWvxI/gMw2IezFH6p0jXfCByriSMD 6d7h6Jk2d6bub3RUWLsurruHYSPqqvM9tI5sN6ZY4nq4uo0MplFEcrQBFXIJAJhy X/JaO9166K0mX73wNFoEmmay5ZTd8wLKvGdlfaHUdUKJcldhh3Ivhl2r0w9Ij6qE w1+QjUxtgabSb/69+3o2m4iil2I5Scc8jr3Vu1riW1yemKSQX7xS0PZ4a6k5/78O 2NGaFZqvs7Uo1EYGz91f50Go1hGLZOH0MMMjd+NSj3pZQvpB+BZ8rlGG7umbjIUF aTBj5hcXN3bBx4VQGnLFwUEbEd6GIog+d6COtpmQzixwdXxw8aUB/m7ouFSegz34 MMEoE0i11HMlyg== =OJYg -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSTVC0ACgkQYKtH/8kJ UieyxRAAiJKwY9bILWnKTPIJ+AlTDzp5ramSVsjD7KzlH6/pgWydgzRRhP/9zz87 f1/wnmMJ2vgWWa1g1NfeX4P8vZyHYsGiuBvQrevzP6Ekc0q19j6CI5tu5zDTy1aF dqZtkpOTqO5+ioTL5bTem2XISvWNnK1TyaWzSHnvbNgfvrWtMiqij9mJyeaF3hdm yCN0XbO8UaChbUobjgjzwg09BvrsN2CtG/2DATIgHUWDrkW0vER0QZRCF0V9mg3O 5kszkfLAsm/7TcQiPAeHEc2IXNRnYl1f4Gkjg7e47Itxkv5+rm/liejdYMZfIQmc Kj0eQerTB974qrcBsrwVE12lNwDK4+3FbAWOZjbXaLtYf27+pSjoG0YVduv8VUNi H81ehi+pHma7Boekf2i9XMVC1+EBBlpPBjxCpaDN5ck7kIkO2bBMX9avTGE9qfn5 9lpU64z6xHv/3YEcnOty4Ggs0V3ZLz4iRkFfWUDtYYsXnFyes1K9ooaDzHojisk0 /vE0KqImlZdlBuBUYpgEBcM/s4V1PtpN3nQtVpUUb77M90GmTLGwLjM8+Y1+JuXV N9eGiPR8YhuMzy4eQR4YEfIqPqwEstRqkOicctJaCDi3Hg4OXmUdUDS66vV9wm+V ntfdphilxBp2EHG42IhKkVH5LdSm/17xbxd2t1RwZ7cMZ7Q5hpw= =7PpG -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.5-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers memory: tegra: Changes for v6.5-rc1 This introduces an interconnect provider for the memory controller and external memory controller found on Tegra234 chips that will eventually be used to dynamically scale the EMC frequency based on a device's bandwidth needs. * tag 'tegra-for-6.5-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Make CPU cluster BW request a multiple of MC channels memory: tegra: Add software memory clients in Tegra234 memory: tegra: Add memory clients for Tegra234 memory: tegra: Add interconnect support for DRAM scaling in Tegra234 dt-bindings: tegra: Add ICC IDs for dummy memory clients dt-bindings: tegra: Document compatible for IGX Link: https://lore.kernel.org/r/20230609193620.2275240-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Sumit Gupta
|
e852af72a7 |
memory: tegra: Make CPU cluster BW request a multiple of MC channels
Make CPU cluster's bandwidth (BW) request a multiple of MC channels. CPU OPP tables have BW info per MC channel. But, the actual BW depends on the number of MC channels which can change as per the boot config. Get the number of MC channels which are actually enabled in current boot configuration and multiply the BW request from a CPU cluster with the number of enabled MC channels. This is not required to be done for other MC clients. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Sumit Gupta
|
9a38cb2766 |
memory: tegra: Add interconnect support for DRAM scaling in Tegra234
Add Interconnect framework support to dynamically set the DRAM bandwidth from different clients. Both the MC and EMC drivers are added as ICC providers. The path for any request is: MC-Client[1-n] -> MC -> EMC -> EMEM/DRAM MC client's request for bandwidth will go to the MC driver which passes the client request info like BPMP Client ID, Client type and the Bandwidth to the BPMP-FW. The final DRAM freq to achieve the requested bandwidth is set by the BPMP-FW based on the passed parameters. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |