Palmer Dabbelt 075fde5818 Merge patch series "riscv: Userspace pointer masking and tagged address ABI" ... Samuel Holland <samuel.holland@sifive.com> says: RISC-V defines three extensions for pointer masking[1]: - Smmpm: configured in M-mode, affects M-mode - Smnpm: configured in M-mode, affects the next lower mode (S or U-mode) - Ssnpm: configured in S-mode, affects the next lower mode (VS, VU, or U-mode) This series adds support for configuring Smnpm or Ssnpm (depending on which privilege mode the kernel is running in) to allow pointer masking in userspace (VU or U-mode), extending the PR_SET_TAGGED_ADDR_CTRL API from arm64. Unlike arm64 TBI, userspace pointer masking is not enabled by default on RISC-V. Additionally, the tag width (referred to as PMLEN) is variable, so userspace needs to ask the kernel for a specific tag width, which is interpreted as a lower bound on the number of tag bits. This series also adds support for a tagged address ABI similar to arm64 and x86. Since accesses from the kernel to user memory use the kernel's pointer masking configuration, not the user's, the kernel must untag user pointers in software before dereferencing them. And since the tag width is variable, as with LAM on x86, it must be kept the same across all threads in a process so untagged_addr_remote() can work. [1]: https://github.com/riscv/riscv-j-extension/raw/d70011dde6c2/zjpm-spec.pdf * b4-shazam-merge: KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests riscv: hwprobe: Export the Supm ISA extension riscv: selftests: Add a pointer masking test riscv: Allow ptrace control of the tagged address ABI riscv: Add support for the tagged address ABI riscv: Add support for userspace pointer masking riscv: Add CSR definitions for pointer masking riscv: Add ISA extension parsing for pointer masking dt-bindings: riscv: Add pointer masking ISA extensions Link: https://lore.kernel.org/r/20241016202814.4061541-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-10-24 14:13:03 -07:00
..
acpi.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot-image-header.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
cmodx.rst	documentation: Fix riscv cmodx example	2024-07-01 10:50:18 -07:00
features.rst	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
hwprobe.rst	Merge patch series "riscv: Userspace pointer masking and tagged address ABI"	2024-10-24 14:13:03 -07:00
index.rst	documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl	2024-04-18 08:10:59 -07:00
patch-acceptance.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
uabi.rst	riscv: Add support for the tagged address ABI	2024-10-24 14:12:56 -07:00
vector.rst	Documentation: Fix spelling mistakes	2024-09-05 14:35:45 -06:00
vm-layout.rst	Revert "RISC-V: mm: Document mmap changes"	2024-08-29 06:03:24 -07:00