mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2024-12-28 16:53:49 +00:00
57e5c814e9
This has a bunch of {read,write}q() calls, so it won't work on 32-bit
systems. I don't think there's any 32-bit StarFive systems, so for now
just require 64-bit.
Fixes: cabff60ca7
("cache: Add StarFive StarLink cache management")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Link: https://lore.kernel.org/r/20240722154519.25375-2-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
28 lines
730 B
Plaintext
28 lines
730 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
menu "Cache Drivers"
|
|
|
|
config AX45MP_L2_CACHE
|
|
bool "Andes Technology AX45MP L2 Cache controller"
|
|
depends on RISCV
|
|
select RISCV_NONSTANDARD_CACHE_OPS
|
|
help
|
|
Support for the L2 cache controller on Andes Technology AX45MP platforms.
|
|
|
|
config SIFIVE_CCACHE
|
|
bool "Sifive Composable Cache controller"
|
|
depends on ARCH_SIFIVE || ARCH_STARFIVE
|
|
help
|
|
Support for the composable cache controller on SiFive platforms.
|
|
|
|
config STARFIVE_STARLINK_CACHE
|
|
bool "StarFive StarLink Cache controller"
|
|
depends on RISCV
|
|
depends on ARCH_STARFIVE
|
|
depends on 64BIT
|
|
select RISCV_DMA_NONCOHERENT
|
|
select RISCV_NONSTANDARD_CACHE_OPS
|
|
help
|
|
Support for the StarLink cache controller IP from StarFive.
|
|
|
|
endmenu
|