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68682e9578
Introduce device driver for PCIe implementation of RISC-V IOMMU architected hardware. IOMMU hardware and system support for MSI or MSI-X is required by this implementation. Vendor and device identifiers used in this patch matches QEMU implementation of the RISC-V IOMMU PCIe device, from Rivos VID (0x1efd) range allocated by the PCI-SIG. MAINTAINERS | added iommu-pci.c already covered by matching pattern. Link: https://lore.kernel.org/qemu-devel/20240307160319.675044-1-dbarboza@ventanamicro.com/ Co-developed-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/12f3bdbe519ebb7ca482191e7334d38b25b8ae8f.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright © 2022-2024 Rivos Inc.
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* Copyright © 2023 FORTH-ICS/CARV
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*
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* RISCV IOMMU as a PCIe device
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*
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* Authors
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* Tomasz Jeznach <tjeznach@rivosinc.com>
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#include <linux/compiler.h>
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#include <linux/init.h>
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#include <linux/iommu.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include "iommu-bits.h"
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#include "iommu.h"
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/* QEMU RISC-V IOMMU implementation */
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#define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014
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/* Rivos Inc. assigned PCI Vendor and Device IDs */
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#ifndef PCI_VENDOR_ID_RIVOS
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#define PCI_VENDOR_ID_RIVOS 0x1efd
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#endif
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#define PCI_DEVICE_ID_RIVOS_RISCV_IOMMU_GA 0x0008
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static int riscv_iommu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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struct riscv_iommu_device *iommu;
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int rc, vec;
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM))
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return -ENODEV;
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if (pci_resource_len(pdev, 0) < RISCV_IOMMU_REG_SIZE)
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return -ENODEV;
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rc = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
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if (rc)
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return dev_err_probe(dev, rc, "pcim_iomap_regions failed\n");
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iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
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if (!iommu)
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return -ENOMEM;
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iommu->dev = dev;
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iommu->reg = pcim_iomap_table(pdev)[0];
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pci_set_master(pdev);
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dev_set_drvdata(dev, iommu);
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/* Check device reported capabilities / features. */
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iommu->caps = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAPABILITIES);
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iommu->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL);
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/* The PCI driver only uses MSIs, make sure the IOMMU supports this */
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switch (FIELD_GET(RISCV_IOMMU_CAPABILITIES_IGS, iommu->caps)) {
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case RISCV_IOMMU_CAPABILITIES_IGS_MSI:
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case RISCV_IOMMU_CAPABILITIES_IGS_BOTH:
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break;
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default:
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return dev_err_probe(dev, -ENODEV,
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"unable to use message-signaled interrupts\n");
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}
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/* Allocate and assign IRQ vectors for the various events */
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rc = pci_alloc_irq_vectors(pdev, 1, RISCV_IOMMU_INTR_COUNT,
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PCI_IRQ_MSIX | PCI_IRQ_MSI);
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if (rc <= 0)
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return dev_err_probe(dev, -ENODEV,
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"unable to allocate irq vectors\n");
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iommu->irqs_count = rc;
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for (vec = 0; vec < iommu->irqs_count; vec++)
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iommu->irqs[vec] = msi_get_virq(dev, vec);
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/* Enable message-signaled interrupts, fctl.WSI */
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if (iommu->fctl & RISCV_IOMMU_FCTL_WSI) {
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iommu->fctl ^= RISCV_IOMMU_FCTL_WSI;
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl);
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}
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return riscv_iommu_init(iommu);
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}
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static void riscv_iommu_pci_remove(struct pci_dev *pdev)
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{
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struct riscv_iommu_device *iommu = dev_get_drvdata(&pdev->dev);
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riscv_iommu_remove(iommu);
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}
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static const struct pci_device_id riscv_iommu_pci_tbl[] = {
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{PCI_VDEVICE(REDHAT, PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), 0},
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{PCI_VDEVICE(RIVOS, PCI_DEVICE_ID_RIVOS_RISCV_IOMMU_GA), 0},
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{0,}
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};
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static struct pci_driver riscv_iommu_pci_driver = {
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.name = KBUILD_MODNAME,
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.id_table = riscv_iommu_pci_tbl,
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.probe = riscv_iommu_pci_probe,
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.remove = riscv_iommu_pci_remove,
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.driver = {
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.suppress_bind_attrs = true,
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},
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};
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builtin_pci_driver(riscv_iommu_pci_driver);
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