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5bd0d8e687
The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller IP supports the following features, among others: * Fixed Rate Link (FRL) * Display Stream Compression (DSC) * 4K@120Hz and 8K@60Hz video modes * Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka Cinema VRR * Fast Vactive (FVA), aka Quick Frame Transport (QFT) * SCDC I2C DDC access * TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4 * YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds * Multi-stream audio * Enhanced Audio Return Channel (EARC) Add library containing common helpers to enable basic support, i.e. RGB output up to 4K@30Hz, without audio, CEC or any HDMI 2.1 specific features. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20241016-b4-rk3588-bridge-upstream-v10-1-87ef92a6d14e@collabora.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
33 lines
910 B
C
33 lines
910 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2024 Collabora Ltd.
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*/
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#ifndef __DW_HDMI_QP__
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#define __DW_HDMI_QP__
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struct device;
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struct drm_encoder;
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struct dw_hdmi_qp;
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struct platform_device;
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struct dw_hdmi_qp_phy_ops {
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int (*init)(struct dw_hdmi_qp *hdmi, void *data);
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void (*disable)(struct dw_hdmi_qp *hdmi, void *data);
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enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, void *data);
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void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data);
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};
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struct dw_hdmi_qp_plat_data {
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const struct dw_hdmi_qp_phy_ops *phy_ops;
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void *phy_data;
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int main_irq;
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};
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struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
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struct drm_encoder *encoder,
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const struct dw_hdmi_qp_plat_data *plat_data);
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void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi);
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#endif /* __DW_HDMI_QP__ */
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