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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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6a46b75a91
Add #defines for Mobileye clock controller:
- EyeQ5 core 0 thru 3 clocks. Internally:
EQ5C_PLL_CPU: already exposed
└── EQ5C_CPU_OCC: unexposed, no reason to do so
├── EQ5C_CPU_CORE0: new!
├── EQ5C_CPU_CORE1: new!
├── EQ5C_CPU_CORE2: new!
└── EQ5C_CPU_CORE3: new!
- EyeQ5 peripheral clocks. Internally:
EQ5C_PLL_PER: already exposed
├── EQ5C_PER_OCC: new!
│ ├── EQ5C_PER_SPI: new!
│ ├── EQ5C_PER_I2C: new!
│ ├── EQ5C_PER_GPIO: new!
│ └── EQ5C_PER_UART: new!
├── EQ5C_PER_EMMC: new!
└── EQ5C_PER_OCC_PCI: new!
- EyeQ6H central OLB. Internally:
EQ6HC_CENTRAL_PLL_CPU: new!
└── EQ6HC_CENTRAL_CPU_OCC: new!
- EyeQ6H west OLB. Internally:
EQ6HC_WEST_PLL_PER: new!
└── EQ6HC_WEST_PER_OCC: new!
└── EQ6HC_WEST_PER_UART: new!
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2024 Mobileye Vision Technologies Ltd.
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*/
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#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
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#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
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#define EQ5C_PLL_CPU 0
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#define EQ5C_PLL_VMP 1
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#define EQ5C_PLL_PMA 2
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#define EQ5C_PLL_VDI 3
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#define EQ5C_PLL_DDR0 4
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#define EQ5C_PLL_PCI 5
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#define EQ5C_PLL_PER 6
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#define EQ5C_PLL_PMAC 7
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#define EQ5C_PLL_MPC 8
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#define EQ5C_PLL_DDR1 9
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#define EQ5C_DIV_OSPI 10
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/* EQ5C_PLL_CPU children */
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#define EQ5C_CPU_CORE0 11
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#define EQ5C_CPU_CORE1 12
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#define EQ5C_CPU_CORE2 13
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#define EQ5C_CPU_CORE3 14
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/* EQ5C_PLL_PER children */
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#define EQ5C_PER_OCC 15
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#define EQ5C_PER_UART 16
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#define EQ5C_PER_SPI 17
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#define EQ5C_PER_I2C 18
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#define EQ5C_PER_GPIO 19
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#define EQ5C_PER_EMMC 20
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#define EQ5C_PER_OCC_PCI 21
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#define EQ6LC_PLL_DDR 0
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#define EQ6LC_PLL_CPU 1
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#define EQ6LC_PLL_PER 2
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#define EQ6LC_PLL_VDI 3
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#define EQ6HC_CENTRAL_PLL_CPU 0
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#define EQ6HC_CENTRAL_CPU_OCC 1
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#define EQ6HC_WEST_PLL_PER 0
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#define EQ6HC_WEST_PER_OCC 1
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#define EQ6HC_WEST_PER_UART 2
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#define EQ6HC_SOUTH_PLL_VDI 0
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#define EQ6HC_SOUTH_PLL_PCIE 1
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#define EQ6HC_SOUTH_PLL_PER 2
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#define EQ6HC_SOUTH_PLL_ISP 3
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#define EQ6HC_SOUTH_DIV_EMMC 4
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#define EQ6HC_SOUTH_DIV_OSPI_REF 5
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#define EQ6HC_SOUTH_DIV_OSPI_SYS 6
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#define EQ6HC_SOUTH_DIV_TSU 7
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#define EQ6HC_ACC_PLL_XNN 0
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#define EQ6HC_ACC_PLL_VMP 1
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#define EQ6HC_ACC_PLL_PMA 2
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#define EQ6HC_ACC_PLL_MPC 3
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#define EQ6HC_ACC_PLL_NOC 4
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#endif
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