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111481020a
Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
34 lines
898 B
C
34 lines
898 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
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* Copyright (c) 2024, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H
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/* GPU_CC clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CRC_AHB_CLK 1
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#define GPU_CC_CX_FF_CLK 2
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#define GPU_CC_CX_GMU_CLK 3
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#define GPU_CC_CXO_AON_CLK 4
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#define GPU_CC_CXO_CLK 5
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#define GPU_CC_FF_CLK_SRC 6
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#define GPU_CC_GMU_CLK_SRC 7
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#define GPU_CC_GX_GMU_CLK 8
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 9
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#define GPU_CC_HUB_AON_CLK 10
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#define GPU_CC_HUB_CLK_SRC 11
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#define GPU_CC_HUB_CX_INT_CLK 12
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#define GPU_CC_MEMNOC_GFX_CLK 13
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#define GPU_CC_PLL0 14
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#define GPU_CC_PLL1 15
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#define GPU_CC_SLEEP_CLK 16
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/* GDSCs */
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#define GPU_GX_GDSC 0
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#define GPU_CX_GDSC 1
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#endif
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