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bc2bb73216
Add bindings for the Network of Connects (NoC) present on the Qualcomm SAR2130P platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241018-sar2130p-icc-v2-1-c58c73dcd19d@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2024, Linaro Ltd.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H
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#define MASTER_QUP_CORE_0 0
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#define MASTER_QUP_CORE_1 1
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#define SLAVE_QUP_CORE_0 2
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#define SLAVE_QUP_CORE_1 3
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#define MASTER_GEM_NOC_CNOC 0
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#define MASTER_GEM_NOC_PCIE_SNOC 1
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#define MASTER_QDSS_DAP 2
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#define SLAVE_AHB2PHY_SOUTH 3
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#define SLAVE_AOSS 4
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#define SLAVE_CAMERA_CFG 5
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#define SLAVE_CLK_CTL 6
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#define SLAVE_CDSP_CFG 7
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#define SLAVE_RBCPR_CX_CFG 8
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#define SLAVE_RBCPR_MMCX_CFG 9
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#define SLAVE_RBCPR_MXA_CFG 10
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#define SLAVE_RBCPR_MXC_CFG 11
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#define SLAVE_CPR_NSPCX 12
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#define SLAVE_CRYPTO_0_CFG 13
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#define SLAVE_CX_RDPM 14
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#define SLAVE_DISPLAY_CFG 15
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#define SLAVE_GFX3D_CFG 16
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#define SLAVE_IMEM_CFG 17
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#define SLAVE_IPC_ROUTER_CFG 18
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#define SLAVE_LPASS 19
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#define SLAVE_MX_RDPM 20
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#define SLAVE_PCIE_0_CFG 21
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#define SLAVE_PCIE_1_CFG 22
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#define SLAVE_PDM 23
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#define SLAVE_PIMEM_CFG 24
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#define SLAVE_PRNG 25
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#define SLAVE_QDSS_CFG 26
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#define SLAVE_QSPI_0 27
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#define SLAVE_QUP_0 28
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#define SLAVE_QUP_1 29
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#define SLAVE_SDCC_1 30
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#define SLAVE_TCSR 31
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#define SLAVE_TLMM 32
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#define SLAVE_TME_CFG 33
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#define SLAVE_USB3_0 34
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#define SLAVE_VENUS_CFG 35
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#define SLAVE_VSENSE_CTRL_CFG 36
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#define SLAVE_WLAN_Q6_CFG 37
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#define SLAVE_DDRSS_CFG 38
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#define SLAVE_CNOC_MNOC_CFG 39
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#define SLAVE_SNOC_CFG 40
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#define SLAVE_IMEM 41
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#define SLAVE_PIMEM 42
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#define SLAVE_SERVICE_CNOC 43
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#define SLAVE_PCIE_0 44
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#define SLAVE_PCIE_1 45
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#define SLAVE_QDSS_STM 46
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#define SLAVE_TCU 47
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#define MASTER_GPU_TCU 0
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_GFX3D 3
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#define MASTER_MNOC_HF_MEM_NOC 4
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#define MASTER_MNOC_SF_MEM_NOC 5
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#define MASTER_COMPUTE_NOC 6
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#define MASTER_ANOC_PCIE_GEM_NOC 7
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#define MASTER_SNOC_GC_MEM_NOC 8
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#define MASTER_SNOC_SF_MEM_NOC 9
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#define MASTER_WLAN_Q6 10
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#define SLAVE_GEM_NOC_CNOC 11
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#define SLAVE_LLCC 12
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#define SLAVE_MEM_NOC_PCIE_SNOC 13
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#define MASTER_CNOC_LPASS_AG_NOC 0
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#define MASTER_LPASS_PROC 1
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#define SLAVE_LPASS_CORE_CFG 2
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#define SLAVE_LPASS_LPI_CFG 3
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#define SLAVE_LPASS_MPU_CFG 4
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#define SLAVE_LPASS_TOP_CFG 5
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#define SLAVE_LPASS_SNOC 6
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#define SLAVE_SERVICES_LPASS_AML_NOC 7
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#define SLAVE_SERVICE_LPASS_AG_NOC 8
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_CAMNOC_HF 0
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#define MASTER_CAMNOC_ICP 1
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#define MASTER_CAMNOC_SF 2
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#define MASTER_LSR 3
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#define MASTER_MDP 4
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#define MASTER_CNOC_MNOC_CFG 5
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#define MASTER_VIDEO 6
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#define MASTER_VIDEO_CV_PROC 7
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#define MASTER_VIDEO_PROC 8
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#define MASTER_VIDEO_V_PROC 9
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#define SLAVE_MNOC_HF_MEM_NOC 10
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#define SLAVE_MNOC_SF_MEM_NOC 11
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#define SLAVE_SERVICE_MNOC 12
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#define MASTER_CDSP_NOC_CFG 0
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#define MASTER_CDSP_PROC 1
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#define SLAVE_CDSP_MEM_NOC 2
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#define SLAVE_SERVICE_NSP_NOC 3
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#define MASTER_PCIE_0 0
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#define MASTER_PCIE_1 1
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#define SLAVE_ANOC_PCIE_GEM_NOC 2
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#define MASTER_GIC_AHB 0
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#define MASTER_QDSS_BAM 1
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#define MASTER_QSPI_0 2
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#define MASTER_QUP_0 3
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#define MASTER_QUP_1 4
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#define MASTER_A2NOC_SNOC 5
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#define MASTER_CNOC_DATAPATH 6
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#define MASTER_LPASS_ANOC 7
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#define MASTER_SNOC_CFG 8
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#define MASTER_CRYPTO 9
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#define MASTER_PIMEM 10
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#define MASTER_GIC 11
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#define MASTER_QDSS_ETR 12
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#define MASTER_QDSS_ETR_1 13
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#define MASTER_SDCC_1 14
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#define MASTER_USB3_0 15
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#define SLAVE_A2NOC_SNOC 16
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#define SLAVE_SNOC_GEM_NOC_GC 17
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#define SLAVE_SNOC_GEM_NOC_SF 18
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#define SLAVE_SERVICE_SNOC 19
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#endif
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