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b472b996a4
Modify license to include dual licensing as GPL-2.0-only OR MIT license for TI specific phy header files. This allows for Linux kernel files to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Trent Piepho <tpiepho@impinj.com> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Kip Broadhurst <kbroadhurst@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
54 lines
1.8 KiB
C
54 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/*
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* Device Tree constants for the Texas Instruments DP83867 PHY
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*
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* Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef _DT_BINDINGS_TI_DP83867_H
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#define _DT_BINDINGS_TI_DP83867_H
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
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#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
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#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
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#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
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/* RGMIIDCTL internal delay for rx and tx */
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#define DP83867_RGMIIDCTL_250_PS 0x0
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#define DP83867_RGMIIDCTL_500_PS 0x1
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#define DP83867_RGMIIDCTL_750_PS 0x2
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#define DP83867_RGMIIDCTL_1_NS 0x3
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#define DP83867_RGMIIDCTL_1_25_NS 0x4
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#define DP83867_RGMIIDCTL_1_50_NS 0x5
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#define DP83867_RGMIIDCTL_1_75_NS 0x6
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#define DP83867_RGMIIDCTL_2_00_NS 0x7
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#define DP83867_RGMIIDCTL_2_25_NS 0x8
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#define DP83867_RGMIIDCTL_2_50_NS 0x9
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#define DP83867_RGMIIDCTL_2_75_NS 0xa
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#define DP83867_RGMIIDCTL_3_00_NS 0xb
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#define DP83867_RGMIIDCTL_3_25_NS 0xc
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#define DP83867_RGMIIDCTL_3_50_NS 0xd
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#define DP83867_RGMIIDCTL_3_75_NS 0xe
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#define DP83867_RGMIIDCTL_4_00_NS 0xf
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/* IO_MUX_CFG - Clock output selection */
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#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
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#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
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#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
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#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
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#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
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#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
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#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
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#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
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#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
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#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
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#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
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#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
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#define DP83867_CLK_O_SEL_REF_CLK 0xC
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/* Special flag to indicate clock should be off */
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#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
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#endif
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